OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

x86: optimize AND/OR with twice the same register

Browse Source 
It seems to be not uncommon for people to use AND or OR in this form for
just setting the status flags. TEST, which doesn't write to any
register other than EFLAGS, ought to be preferred. Make the change only
for -O2 and above though, at least for now.
This commit is contained in:
Jan Beulich 2019-07-01 08:35:08 +02:00
parent 79dec6b7ba
commit 5641ec015a
13 changed files with 445 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
gas/ChangeLog
View File

@ -1,3 +1,17 @@
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Handle AND / OR with
both operands being the same register.
* doc/c-i386.texi: Update -O2 documentation.
* testsuite/gas/i386/optimize-2.s,
testsuite/gas/i386/x86-64-optimize-3.s: Add cases of AND / OR
with both operands being the same register.
* testsuite/gas/i386/optimize-2.d,
testsuite/gas/i386/x86-64-optimize-3.d: Adjust expectations.
* testsuite/gas/i386/optimize-2b.d,
testsuite/gas/i386/x86-64-optimize-3b.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (commutative): New.

23
gas/config/tc-i386.c
View File

@ -4040,6 +4040,29 @@ optimize_encoding (void)
}
}
}
else if (optimize > 1
&& !optimize_for_space
&& i.reg_operands == 2
&& i.op[0].regs == i.op[1].regs
&& ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8
|| (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20)
&& (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
{
/* Optimize: -O2:
andb %rN, %rN -> testb %rN, %rN
andw %rN, %rN -> testw %rN, %rN
andq %rN, %rN -> testq %rN, %rN
orb %rN, %rN -> testb %rN, %rN
orw %rN, %rN -> testw %rN, %rN
orq %rN, %rN -> testq %rN, %rN
and outside of 64-bit mode
andl %rN, %rN -> testl %rN, %rN
orl %rN, %rN -> testl %rN, %rN
*/
i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
}
else if (i.reg_operands == 3
&& i.op[0].regs == i.op[1].regs
&& !i.types[2].bitfield.xmmword

3
gas/doc/c-i386.texi
View File

@ -477,7 +477,8 @@ instructions with 128-bit/256-bit VEX packed integer logical.
EVEX vector register clearing instructions. In 64-bit mode VEX encoded
instructions with commutative source operands will also have their
source operands swapped if this allows using the 2-byte VEX prefix form
instead of the 3-byte one.
instead of the 3-byte one. Certain forms of AND as well as OR with the
same (register) operand specified twice will also be changed to TEST.
@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
and 64-bit register tests with immediate as 8-bit register test with

2
gas/testsuite/gas/i386/i386.exp
View File

@ -488,6 +488,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "optimize-1"
run_dump_test "optimize-1a"
run_dump_test "optimize-2"
run_dump_test "optimize-2b"
run_dump_test "optimize-3"
run_dump_test "optimize-4"
run_dump_test "optimize-5"
@ -1016,6 +1017,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-optimize-2a"
run_dump_test "x86-64-optimize-2b"
run_dump_test "x86-64-optimize-3"
run_dump_test "x86-64-optimize-3b"
run_dump_test "x86-64-optimize-4"
run_dump_test "x86-64-optimize-5"
run_dump_test "x86-64-optimize-6"

6
gas/testsuite/gas/i386/optimize-2.d
View File

@ -16,6 +16,12 @@ Disassembly of section .text:
+[a-f0-9]+: f6 c3 7f test \$0x7f,%bl
+[a-f0-9]+: f7 c7 7f 00 00 00 test \$0x7f,%edi
+[a-f0-9]+: 66 f7 c7 7f 00 test \$0x7f,%di
+[a-f0-9]+: 20 c9 and %cl,%cl
+[a-f0-9]+: 66 21 d2 and %dx,%dx
+[a-f0-9]+: 21 db and %ebx,%ebx
+[a-f0-9]+: 08 e4 or %ah,%ah
+[a-f0-9]+: 66 09 ed or %bp,%bp
+[a-f0-9]+: 09 f6 or %esi,%esi
+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2

8
gas/testsuite/gas/i386/optimize-2.s
View File

@ -12,6 +12,14 @@ _start:
test $0x7f, %edi
test $0x7f, %di
and %cl, %cl
and %dx, %dx
and %ebx, %ebx
or %ah, %ah
or %bp, %bp
or %esi, %esi
vandnpd %zmm1, %zmm1, %zmm5
vmovdqa32 %xmm1, %xmm2

163
gas/testsuite/gas/i386/optimize-2b.d Normal file
View File

@ -0,0 +1,163 @@
#source: optimize-2.s
#as: -O2
#objdump: -drw
#name: optimized encoding 2 with -O2
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: a9 7f 00 00 00 test \$0x7f,%eax
+[a-f0-9]+: 66 a9 7f 00 test \$0x7f,%ax
+[a-f0-9]+: a8 7f test \$0x7f,%al
+[a-f0-9]+: f7 c3 7f 00 00 00 test \$0x7f,%ebx
+[a-f0-9]+: 66 f7 c3 7f 00 test \$0x7f,%bx
+[a-f0-9]+: f6 c3 7f test \$0x7f,%bl
+[a-f0-9]+: f7 c7 7f 00 00 00 test \$0x7f,%edi
+[a-f0-9]+: 66 f7 c7 7f 00 test \$0x7f,%di
+[a-f0-9]+: 84 c9 test %cl,%cl
+[a-f0-9]+: 66 85 d2 test %dx,%dx
+[a-f0-9]+: 85 db test %ebx,%ebx
+[a-f0-9]+: 84 e4 test %ah,%ah
+[a-f0-9]+: 66 85 ed test %bp,%bp
+[a-f0-9]+: 85 f6 test %esi,%esi
+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c5 f9 6f 50 7f vmovdqa 0x7f\(%eax\),%xmm2
+[a-f0-9]+: c5 f9 6f 50 7f vmovdqa 0x7f\(%eax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%eax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%eax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%eax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%eax\),%xmm2
+[a-f0-9]+: 62 f1 7d 08 7f 48 08 vmovdqa32 %xmm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 fd 08 7f 48 08 vmovdqa64 %xmm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 7f 08 7f 48 08 vmovdqu8 %xmm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 ff 08 7f 48 08 vmovdqu16 %xmm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 7e 08 7f 48 08 vmovdqu32 %xmm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 fe 08 7f 48 08 vmovdqu64 %xmm1,0x80\(%eax\)
+[a-f0-9]+: c5 fd 6f d1 vmovdqa %ymm1,%ymm2
+[a-f0-9]+: c5 fd 6f d1 vmovdqa %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c5 fd 6f 50 7f vmovdqa 0x7f\(%eax\),%ymm2
+[a-f0-9]+: c5 fd 6f 50 7f vmovdqa 0x7f\(%eax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%eax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%eax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%eax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%eax\),%ymm2
+[a-f0-9]+: 62 f1 7d 28 7f 48 04 vmovdqa32 %ymm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 fd 28 7f 48 04 vmovdqa64 %ymm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 7f 28 7f 48 04 vmovdqu8 %ymm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 ff 28 7f 48 04 vmovdqu16 %ymm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%eax\)
+[a-f0-9]+: 62 f1 7d 48 6f d1 vmovdqa32 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 fd 48 6f d1 vmovdqa64 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 7f 48 6f d1 vmovdqu8 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 ff 48 6f d1 vmovdqu16 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 7e 48 6f d1 vmovdqu32 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 fe 48 6f d1 vmovdqu64 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 fd 28 6f d1 vmovdqa64 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 7f 08 6f d1 vmovdqu8 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 ff 08 6f d1 vmovdqu16 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 7e 08 6f d1 vmovdqu32 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 fe 08 6f d1 vmovdqu64 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 7d 29 6f d1 vmovdqa32 %ymm1,%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 fd 29 6f d1 vmovdqa64 %ymm1,%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 7f 09 6f d1 vmovdqu8 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 ff 09 6f d1 vmovdqu16 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7e 09 6f d1 vmovdqu32 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 fe 09 6f d1 vmovdqu64 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7d 29 6f 10 vmovdqa32 \(%eax\),%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 fd 29 6f 10 vmovdqa64 \(%eax\),%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 7f 09 6f 10 vmovdqu8 \(%eax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 ff 09 6f 10 vmovdqu16 \(%eax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7e 09 6f 10 vmovdqu32 \(%eax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 fe 09 6f 10 vmovdqu64 \(%eax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7d 29 7f 08 vmovdqa32 %ymm1,\(%eax\)\{%k1\}
+[a-f0-9]+: 62 f1 fd 29 7f 08 vmovdqa64 %ymm1,\(%eax\)\{%k1\}
+[a-f0-9]+: 62 f1 7f 09 7f 08 vmovdqu8 %xmm1,\(%eax\)\{%k1\}
+[a-f0-9]+: 62 f1 ff 09 7f 08 vmovdqu16 %xmm1,\(%eax\)\{%k1\}
+[a-f0-9]+: 62 f1 7e 09 7f 08 vmovdqu32 %xmm1,\(%eax\)\{%k1\}
+[a-f0-9]+: 62 f1 fe 09 7f 08 vmovdqu64 %xmm1,\(%eax\)\{%k1\}
+[a-f0-9]+: 62 f1 7d 89 6f d1 vmovdqa32 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 fd 89 6f d1 vmovdqa64 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 7f 89 6f d1 vmovdqu8 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 ff 89 6f d1 vmovdqu16 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 7e 89 6f d1 vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 fe 89 6f d1 vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpand 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpandn 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpor 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpxor 0x70\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpand 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpandn 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpor 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpxor 0x60\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandd 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandnd 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandnq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpord 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4\{%k5\}
+[a-f0-9]+: 62 .* vpandq %ymm2,%ymm3,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm3,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm4\{%k5\}
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4\{%k5\}
+[a-f0-9]+: 62 .* vporq %ymm2,%ymm3,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm3,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm4\{%k5\}
+[a-f0-9]+: 62 .* vpandd \(%eax\)\{1to8\},%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandq \(%eax\)\{1to2\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnd \(%eax\)\{1to4\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnq \(%eax\)\{1to4\},%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpord \(%eax\)\{1to8\},%ymm2,%ymm3
+[a-f0-9]+: 62 .* vporq \(%eax\)\{1to2\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxord \(%eax\)\{1to4\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxorq \(%eax\)\{1to4\},%ymm2,%ymm3
#pass

8
gas/testsuite/gas/i386/x86-64-optimize-3.d
View File

@ -24,6 +24,14 @@ Disassembly of section .text:
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+[a-f0-9]+: 20 c9 and %cl,%cl
+[a-f0-9]+: 66 21 d2 and %dx,%dx
+[a-f0-9]+: 21 db and %ebx,%ebx
+[a-f0-9]+: 48 21 e4 and %rsp,%rsp
+[a-f0-9]+: 40 08 ed or %bpl,%bpl
+[a-f0-9]+: 66 09 f6 or %si,%si
+[a-f0-9]+: 09 ff or %edi,%edi
+[a-f0-9]+: 4d 09 c0 or %r8,%r8
+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2

10
gas/testsuite/gas/i386/x86-64-optimize-3.s
View File

@ -20,6 +20,16 @@ _start:
test $0x7f, %r9w
test $0x7f, %r9b
and %cl, %cl
and %dx, %dx
and %ebx, %ebx
and %rsp, %rsp
or %bpl, %bpl
or %si, %si
or %edi, %edi
or %r8, %r8
vandnpd %zmm1, %zmm1, %zmm5
vmovdqa32 %xmm1, %xmm2

199
gas/testsuite/gas/i386/x86-64-optimize-3b.d Normal file
View File

@ -0,0 +1,199 @@
#source: x86-64-optimize-3.s
#as: -O2
#objdump: -drw
#name: x86-64 optimized encoding 3 with -O2
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
+[a-f0-9]+: a9 7f 00 00 00 test \$0x7f,%eax
+[a-f0-9]+: a9 7f 00 00 00 test \$0x7f,%eax
+[a-f0-9]+: 66 a9 7f 00 test \$0x7f,%ax
+[a-f0-9]+: a8 7f test \$0x7f,%al
+[a-f0-9]+: f7 c3 7f 00 00 00 test \$0x7f,%ebx
+[a-f0-9]+: f7 c3 7f 00 00 00 test \$0x7f,%ebx
+[a-f0-9]+: 66 f7 c3 7f 00 test \$0x7f,%bx
+[a-f0-9]+: f6 c3 7f test \$0x7f,%bl
+[a-f0-9]+: f7 c7 7f 00 00 00 test \$0x7f,%edi
+[a-f0-9]+: f7 c7 7f 00 00 00 test \$0x7f,%edi
+[a-f0-9]+: 66 f7 c7 7f 00 test \$0x7f,%di
+[a-f0-9]+: 40 f6 c7 7f test \$0x7f,%dil
+[a-f0-9]+: 41 f7 c1 7f 00 00 00 test \$0x7f,%r9d
+[a-f0-9]+: 41 f7 c1 7f 00 00 00 test \$0x7f,%r9d
+[a-f0-9]+: 66 41 f7 c1 7f 00 test \$0x7f,%r9w
+[a-f0-9]+: 41 f6 c1 7f test \$0x7f,%r9b
+[a-f0-9]+: 84 c9 test %cl,%cl
+[a-f0-9]+: 66 85 d2 test %dx,%dx
+[a-f0-9]+: 21 db and %ebx,%ebx
+[a-f0-9]+: 48 85 e4 test %rsp,%rsp
+[a-f0-9]+: 40 84 ed test %bpl,%bpl
+[a-f0-9]+: 66 85 f6 test %si,%si
+[a-f0-9]+: 09 ff or %edi,%edi
+[a-f0-9]+: 4d 85 c0 test %r8,%r8
+[a-f0-9]+: c5 f1 55 e9 vandnpd %xmm1,%xmm1,%xmm5
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 f9 6f d1 vmovdqa %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c5 fa 6f d1 vmovdqu %xmm1,%xmm2
+[a-f0-9]+: c4 41 79 6f e3 vmovdqa %xmm11,%xmm12
+[a-f0-9]+: c4 41 79 6f e3 vmovdqa %xmm11,%xmm12
+[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+[a-f0-9]+: c4 41 7a 6f e3 vmovdqu %xmm11,%xmm12
+[a-f0-9]+: c5 f9 6f 50 7f vmovdqa 0x7f\(%rax\),%xmm2
+[a-f0-9]+: c5 f9 6f 50 7f vmovdqa 0x7f\(%rax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+[a-f0-9]+: c5 fa 6f 50 7f vmovdqu 0x7f\(%rax\),%xmm2
+[a-f0-9]+: 62 f1 7d 08 7f 48 08 vmovdqa32 %xmm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 fd 08 7f 48 08 vmovdqa64 %xmm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7f 08 7f 48 08 vmovdqu8 %xmm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 ff 08 7f 48 08 vmovdqu16 %xmm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7e 08 7f 48 08 vmovdqu32 %xmm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 fe 08 7f 48 08 vmovdqu64 %xmm1,0x80\(%rax\)
+[a-f0-9]+: c5 fd 6f d1 vmovdqa %ymm1,%ymm2
+[a-f0-9]+: c5 fd 6f d1 vmovdqa %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c5 fe 6f d1 vmovdqu %ymm1,%ymm2
+[a-f0-9]+: c4 41 7d 6f e3 vmovdqa %ymm11,%ymm12
+[a-f0-9]+: c4 41 7d 6f e3 vmovdqa %ymm11,%ymm12
+[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+[a-f0-9]+: c4 41 7e 6f e3 vmovdqu %ymm11,%ymm12
+[a-f0-9]+: c5 fd 6f 50 7f vmovdqa 0x7f\(%rax\),%ymm2
+[a-f0-9]+: c5 fd 6f 50 7f vmovdqa 0x7f\(%rax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+[a-f0-9]+: c5 fe 6f 50 7f vmovdqu 0x7f\(%rax\),%ymm2
+[a-f0-9]+: 62 f1 7d 28 7f 48 04 vmovdqa32 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 fd 28 7f 48 04 vmovdqa64 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7f 28 7f 48 04 vmovdqu8 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 ff 28 7f 48 04 vmovdqu16 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 7e 28 7f 48 04 vmovdqu32 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 f1 fe 28 7f 48 04 vmovdqu64 %ymm1,0x80\(%rax\)
+[a-f0-9]+: 62 b1 7d 08 6f d5 vmovdqa32 %xmm21,%xmm2
+[a-f0-9]+: 62 b1 fd 08 6f d5 vmovdqa64 %xmm21,%xmm2
+[a-f0-9]+: 62 b1 7f 08 6f d5 vmovdqu8 %xmm21,%xmm2
+[a-f0-9]+: 62 b1 ff 08 6f d5 vmovdqu16 %xmm21,%xmm2
+[a-f0-9]+: 62 b1 7e 08 6f d5 vmovdqu32 %xmm21,%xmm2
+[a-f0-9]+: 62 b1 fe 08 6f d5 vmovdqu64 %xmm21,%xmm2
+[a-f0-9]+: 62 f1 7d 48 6f d1 vmovdqa32 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 fd 48 6f d1 vmovdqa64 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 7f 48 6f d1 vmovdqu8 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 ff 48 6f d1 vmovdqu16 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 7e 48 6f d1 vmovdqu32 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 fe 48 6f d1 vmovdqu64 %zmm1,%zmm2
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 fd 28 6f d1 vmovdqa64 %ymm1,%ymm2
+[a-f0-9]+: 62 f1 7f 08 6f d1 vmovdqu8 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 ff 08 6f d1 vmovdqu16 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 7e 08 6f d1 vmovdqu32 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 fe 08 6f d1 vmovdqu64 %xmm1,%xmm2
+[a-f0-9]+: 62 f1 7d 29 6f d1 vmovdqa32 %ymm1,%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 fd 29 6f d1 vmovdqa64 %ymm1,%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 7f 09 6f d1 vmovdqu8 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 ff 09 6f d1 vmovdqu16 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7e 09 6f d1 vmovdqu32 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 fe 09 6f d1 vmovdqu64 %xmm1,%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7d 29 6f 10 vmovdqa32 \(%rax\),%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 fd 29 6f 10 vmovdqa64 \(%rax\),%ymm2\{%k1\}
+[a-f0-9]+: 62 f1 7f 09 6f 10 vmovdqu8 \(%rax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 ff 09 6f 10 vmovdqu16 \(%rax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7e 09 6f 10 vmovdqu32 \(%rax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 fe 09 6f 10 vmovdqu64 \(%rax\),%xmm2\{%k1\}
+[a-f0-9]+: 62 f1 7d 29 7f 08 vmovdqa32 %ymm1,\(%rax\)\{%k1\}
+[a-f0-9]+: 62 f1 fd 29 7f 08 vmovdqa64 %ymm1,\(%rax\)\{%k1\}
+[a-f0-9]+: 62 f1 7f 09 7f 08 vmovdqu8 %xmm1,\(%rax\)\{%k1\}
+[a-f0-9]+: 62 f1 ff 09 7f 08 vmovdqu16 %xmm1,\(%rax\)\{%k1\}
+[a-f0-9]+: 62 f1 7e 09 7f 08 vmovdqu32 %xmm1,\(%rax\)\{%k1\}
+[a-f0-9]+: 62 f1 fe 09 7f 08 vmovdqu64 %xmm1,\(%rax\)\{%k1\}
+[a-f0-9]+: 62 f1 7d 89 6f d1 vmovdqa32 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 fd 89 6f d1 vmovdqa64 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 7f 89 6f d1 vmovdqu8 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 ff 89 6f d1 vmovdqu16 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 7e 89 6f d1 vmovdqu32 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: 62 f1 fe 89 6f d1 vmovdqu64 %xmm1,%xmm2\{%k1\}\{z\}
+[a-f0-9]+: c5 .* vpand %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpand %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpandn %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpor %xmm2,%xmm3,%xmm4
+[a-f0-9]+: c5 .* vpor %xmm3,%xmm12,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm13,%xmm4
+[a-f0-9]+: c5 .* vpxor %xmm2,%xmm3,%xmm14
+[a-f0-9]+: c5 .* vpand %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpand %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpandn %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpor %ymm2,%ymm3,%ymm4
+[a-f0-9]+: c5 .* vpor %ymm3,%ymm12,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm13,%ymm4
+[a-f0-9]+: c5 .* vpxor %ymm2,%ymm3,%ymm14
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpand 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpandn 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpor 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpxor 0x70\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%xmm2,%xmm3
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpand 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpandn 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpor 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: c5 .* vpxor 0x60\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandd 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandnd 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandnq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpord 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandd %xmm22,%xmm23,%xmm24
+[a-f0-9]+: 62 .* vpandq %ymm22,%ymm3,%ymm4
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm23,%ymm4
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm24
+[a-f0-9]+: 62 .* vpord %xmm22,%xmm23,%xmm24
+[a-f0-9]+: 62 .* vporq %ymm22,%ymm3,%ymm4
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm23,%ymm4
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm24
+[a-f0-9]+: 62 .* vpandd %xmm2,%xmm3,%xmm4\{%k5\}
+[a-f0-9]+: 62 .* vpandq %ymm12,%ymm3,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpandnd %ymm2,%ymm13,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpandnq %xmm2,%xmm3,%xmm14\{%k5\}
+[a-f0-9]+: 62 .* vpord %xmm2,%xmm3,%xmm4\{%k5\}
+[a-f0-9]+: 62 .* vporq %ymm12,%ymm3,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpxord %ymm2,%ymm13,%ymm4\{%k5\}
+[a-f0-9]+: 62 .* vpxorq %xmm2,%xmm3,%xmm14\{%k5\}
+[a-f0-9]+: 62 .* vpandd \(%rax\)\{1to8\},%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpandq \(%rax\)\{1to2\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnd \(%rax\)\{1to4\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpandnq \(%rax\)\{1to4\},%ymm2,%ymm3
+[a-f0-9]+: 62 .* vpord \(%rax\)\{1to8\},%ymm2,%ymm3
+[a-f0-9]+: 62 .* vporq \(%rax\)\{1to2\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxord \(%rax\)\{1to4\},%xmm2,%xmm3
+[a-f0-9]+: 62 .* vpxorq \(%rax\)\{1to4\},%ymm2,%ymm3
#pass

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (and, or): Add Optimize to forms allowing two
register operands.
* i386-tbl.h: Re-generate.
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (C): New.

4
opcodes/i386-opc.tbl
View File

@ -213,12 +213,12 @@ test, 2, 0x84, None, 1, 0, W|Modrm|No_sSuf|No_ldSuf, { Byte|Word|Dword|Qword|Uns
test, 2, 0xa8, None, 1, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
test, 2, 0xf6, 0x0, 1, 0, W|Modrm|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
and, 2, 0x20, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
and, 2, 0x20, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
and, 2, 0x83, 0x4, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
and, 2, 0x24, None, 1, 0, W|No_sSuf|No_ldSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
and, 2, 0x80, 0x4, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
or, 2, 0x8, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
or, 2, 0x8, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
or, 2, 0x83, 0x1, 1, 0, Modrm|No_bSuf|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
or, 2, 0xc, None, 1, 0, W|No_sSuf|No_ldSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
or, 2, 0x80, 0x1, 1, 0, W|Modrm|No_sSuf|No_ldSuf|IsLockable|HLEPrefixOk, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }

4
opcodes/i386-tbl.h
View File

@ -1713,7 +1713,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0 } },
@ -1777,7 +1777,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0 } },