x86: further refine SSE check (SSE4a, SHA, GFNI)
In ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went
both a little too far and not quite far enough:
- GFNI insns also have AVX512 variants, which also shouldn't get
diagnosed,
- SSE4a insns should get diagnosed just like SSE4.x ones,
- SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
This commit is contained in:
Jan Beulich
parent
d8edc8b768
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569d50f1c6
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@ -1,3 +1,13 @@
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2018-12-11 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (md_assemble): Extend SSE check conditional.
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* testsuite/gas/i386/sse-check.s: Add SSE4a and SHA tests.
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Extend GFNI tests.
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* testsuite/gas/i386/sse-check.d: Adjust expectations.
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* testsuite/gas/i386/sse-check-error.l,
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testsuite/gas/i386/x86-64-sse-check-error.l: Likewise.
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* testsuite/gas/i386/sse-check-warn.e: Likewise.
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2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>
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* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
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@ -4286,14 +4286,17 @@ md_assemble (char *line)
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if (sse_check != check_none
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&& !i.tm.opcode_modifier.noavx
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&& !i.tm.cpu_flags.bitfield.cpuavx
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&& !i.tm.cpu_flags.bitfield.cpuavx512f
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&& (i.tm.cpu_flags.bitfield.cpusse
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|| i.tm.cpu_flags.bitfield.cpusse2
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|| i.tm.cpu_flags.bitfield.cpusse3
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|| i.tm.cpu_flags.bitfield.cpussse3
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|| i.tm.cpu_flags.bitfield.cpusse4_1
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|| i.tm.cpu_flags.bitfield.cpusse4_2
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|| i.tm.cpu_flags.bitfield.cpusse4a
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|| i.tm.cpu_flags.bitfield.cpupclmul
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|| i.tm.cpu_flags.bitfield.cpuaes
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|| i.tm.cpu_flags.bitfield.cpusha
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|| i.tm.cpu_flags.bitfield.cpugfni))
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{
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(sse_check == check_warning
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@ -8,6 +8,8 @@
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.*:23: Error: .*
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.*:26: Error: .*
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.*:29: Error: .*
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.*:32: Error: .*
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.*:35: Error: .*
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GAS LISTING .*
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@ -42,17 +44,33 @@ GAS LISTING .*
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.* Error: SSE instruction `pcmpgtq' is used
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[ ]*20[ ]+C1
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[ ]*21[ ]+
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[ ]*22[ ]+\# PCMUL instruction
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[ ]*23[ ]+\?\?\?\? 660F3A44 pclmulqdq \$-1,%xmm1,%xmm2
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.* Error: SSE instruction `pclmulqdq' is used
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[ ]*23[ ]+D1FF
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[ ]*22[ ]+\# SSE4a instruction
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[ ]*23[ ]+\?\?\?\? 660F78C0 extrq \$0, \$0, %xmm0
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.* Error: SSE instruction `extrq' is used
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[ ]*23[ ]+0000
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[ ]*24[ ]+
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[ ]*25[ ]+\# AES instructions
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[ ]*26[ ]+\?\?\?\? 660F38DE aesdec %xmm1,%xmm2
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.* Error: SSE instruction `aesdec' is used
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[ ]*26[ ]+D1
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[ ]*25[ ]+\# PCMUL instruction
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[ ]*26[ ]+\?\?\?\? 660F3A44 pclmulqdq \$-1,%xmm1,%xmm2
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.* Error: SSE instruction `pclmulqdq' is used
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[ ]*26[ ]+D1FF
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[ ]*27[ ]+
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[ ]*28[ ]+\# GFNI instructions
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[ ]*29[ ]+\?\?\?\? 660F38CF gf2p8mulb %xmm1,%xmm2
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.* Error: SSE instruction `gf2p8mulb' is used
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[ ]*28[ ]+\# AES instructions
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[ ]*29[ ]+\?\?\?\? 660F38DE aesdec %xmm1,%xmm2
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.* Error: SSE instruction `aesdec' is used
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[ ]*29[ ]+D1
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[ ]*30[ ]+
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[ ]*31[ ]+\# SHA instruction
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[ ]*32[ ]+\?\?\?\? 0F38C8C0 sha1nexte %xmm0, %xmm0
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.* Error: SSE instruction `sha1nexte' is used
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[ ]*33[ ]+
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[ ]*34[ ]+\# GFNI instructions
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[ ]*35[ ]+\?\?\?\? 660F38CF gf2p8mulb %xmm1,%xmm2
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.* Error: SSE instruction `gf2p8mulb' is used
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[ ]*35[ ]+D1
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[ ]*36[ ]+\?\?\?\? 62F27D09 vgf2p8mulb %xmm0, %xmm0, %xmm0\{%k1\}
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[ ]*36[ ]+CFC0
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[ ]*37[ ]+\?\?\?\? 62F27D48 vgf2p8mulb %zmm0, %zmm0, %zmm0
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GAS LISTING .*
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[ ]*37[ ]+CFC0
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@ -5,6 +5,8 @@
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.*:16: Warning: SSE instruction `phaddw' is used
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.*:19: Warning: SSE instruction `blendvpd' is used
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.*:20: Warning: SSE instruction `pcmpgtq' is used
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.*:23: Warning: SSE instruction `pclmulqdq' is used
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.*:26: Warning: SSE instruction `aesdec' is used
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.*:29: Warning: SSE instruction `gf2p8mulb' is used
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.*:23: Warning: SSE instruction `extrq' is used
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.*:26: Warning: SSE instruction `pclmulqdq' is used
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.*:29: Warning: SSE instruction `aesdec' is used
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.*:32: Warning: SSE instruction `sha1nexte' is used
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.*:35: Warning: SSE instruction `gf2p8mulb' is used
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@ -13,7 +13,11 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 38 01 ca phaddw %xmm2,%xmm1
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[ ]*[a-f0-9]+: 66 0f 38 15 c1 blendvpd %xmm0,%xmm1,%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 37 c1 pcmpgtq %xmm1,%xmm0
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[ ]*[a-f0-9]+: 66 0f 78 c0 00 00 extrq \$0x0,\$0x0,%xmm0
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[ ]*[a-f0-9]+: 66 0f 3a 44 d1 ff pclmulqdq \$0xff,%xmm1,%xmm2
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[ ]*[a-f0-9]+: 66 0f 38 de d1 aesdec %xmm1,%xmm2
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[ ]*[a-f0-9]+: 0f 38 c8 c0 sha1nexte %xmm0,%xmm0
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[ ]*[a-f0-9]+: 66 0f 38 cf d1 gf2p8mulb %xmm1,%xmm2
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[ ]*[a-f0-9]+: 62 f2 7d 09 cf c0 vgf2p8mulb %xmm0,%xmm0,%xmm0\{%k1\}
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[ ]*[a-f0-9]+: 62 f2 7d 48 cf c0 vgf2p8mulb %zmm0,%zmm0,%zmm0
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#pass
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@ -19,11 +19,19 @@ _start:
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blendvpd %xmm0,%xmm1,%xmm0
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pcmpgtq %xmm1,%xmm0
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# SSE4a instruction
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extrq $0, $0, %xmm0
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# PCMUL instruction
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pclmulqdq $-1,%xmm1,%xmm2
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# AES instructions
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aesdec %xmm1,%xmm2
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# SHA instruction
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sha1nexte %xmm0, %xmm0
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# GFNI instructions
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gf2p8mulb %xmm1,%xmm2
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vgf2p8mulb %xmm0, %xmm0, %xmm0{%k1}
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vgf2p8mulb %zmm0, %zmm0, %zmm0
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@ -8,6 +8,8 @@
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.*:23: Error: .*
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.*:26: Error: .*
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.*:29: Error: .*
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.*:32: Error: .*
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.*:35: Error: .*
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GAS LISTING .*
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@ -42,17 +44,33 @@ GAS LISTING .*
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.* Error: SSE instruction `pcmpgtq' is used
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[ ]*20[ ]+C1
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[ ]*21[ ]+
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[ ]*22[ ]+\# PCMUL instruction
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[ ]*23[ ]+\?\?\?\? 660F3A44 pclmulqdq \$-1,%xmm1,%xmm2
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.* Error: SSE instruction `pclmulqdq' is used
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[ ]*23[ ]+D1FF
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[ ]*22[ ]+\# SSE4a instruction
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[ ]*23[ ]+\?\?\?\? 660F78C0 extrq \$0, \$0, %xmm0
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.* Error: SSE instruction `extrq' is used
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[ ]*23[ ]+0000
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[ ]*24[ ]+
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[ ]*25[ ]+\# AES instructions
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[ ]*26[ ]+\?\?\?\? 660F38DE aesdec %xmm1,%xmm2
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.* Error: SSE instruction `aesdec' is used
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[ ]*26[ ]+D1
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[ ]*25[ ]+\# PCMUL instruction
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[ ]*26[ ]+\?\?\?\? 660F3A44 pclmulqdq \$-1,%xmm1,%xmm2
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.* Error: SSE instruction `pclmulqdq' is used
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[ ]*26[ ]+D1FF
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[ ]*27[ ]+
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[ ]*28[ ]+\# GFNI instructions
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[ ]*29[ ]+\?\?\?\? 660F38CF gf2p8mulb %xmm1,%xmm2
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.* Error: SSE instruction `gf2p8mulb' is used
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[ ]*28[ ]+\# AES instructions
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[ ]*29[ ]+\?\?\?\? 660F38DE aesdec %xmm1,%xmm2
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.* Error: SSE instruction `aesdec' is used
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[ ]*29[ ]+D1
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[ ]*30[ ]+
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[ ]*31[ ]+\# SHA instruction
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[ ]*32[ ]+\?\?\?\? 0F38C8C0 sha1nexte %xmm0, %xmm0
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.* Error: SSE instruction `sha1nexte' is used
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[ ]*33[ ]+
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[ ]*34[ ]+\# GFNI instructions
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[ ]*35[ ]+\?\?\?\? 660F38CF gf2p8mulb %xmm1,%xmm2
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.* Error: SSE instruction `gf2p8mulb' is used
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[ ]*35[ ]+D1
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[ ]*36[ ]+\?\?\?\? 62F27D09 vgf2p8mulb %xmm0, %xmm0, %xmm0\{%k1\}
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[ ]*36[ ]+CFC0
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[ ]*37[ ]+\?\?\?\? 62F27D48 vgf2p8mulb %zmm0, %zmm0, %zmm0
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GAS LISTING .*
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[ ]*37[ ]+CFC0
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