* Enlarged PKE testing mini bucket. Not yet converted to dejagnu.
This commit is contained in:
Frank Ch. Eigler
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9495a61e55
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574edea8b2
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@ -1,3 +1,8 @@
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Wed Feb 25 14:24:04 1998 Frank Ch. Eigler <fche@cygnus.com>
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* t-pke3.trc: Added tests for PKEcode[i] stalling and masking,
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FBRST register STP and STC, erroneous register accesses.
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Tue Feb 24 19:32:10 1998 Frank Ch. Eigler <fche@cygnus.com>
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* ChangeLog, Makefile.in, configure, configure.in, t-pke1.trc,
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@ -88,7 +88,7 @@
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? 0x10003830 0x00001234 0xffffffff
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#
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#
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# ---- ERROR/ER1 ----
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# ---- bad PKEcode/ER1, interrupts ----
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#
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# A bad PKEcode
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1 0x00000000_00000000_00000000_08000000 0x00000000 PPPP
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@ -101,6 +101,35 @@
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! 0x10003c10 0x00000001
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# Read STAT register; confirm ER1 no longer set
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? 0x10003c00 0x00000000 0x00002000
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#
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# Mask ME1 (ER1 stall) this time
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! 0x10003c20 0x00000004
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# A bad PKEcode with ER1 masked
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1 0x00000000_00000000_00000000_08000000 0x00000000 PPPP
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# should not put PKE into stalled mode, should execute following PKENOPs
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# Read STAT register; confirm ER1 bit set
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? 0x10003c00 0x00002000 0x00002000
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# Read CODE register; confirm PKE went past bad code
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? 0x10003c80 0x00000000 0xffffffff
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# Reset PKE
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! 0x10003c10 0x00000001
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# Read STAT register; confirm ER1 no longer set
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? 0x10003c00 0x00000000 0x00002000
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#
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#
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# A good PKEcode (STMOD) with interrupt
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1 0x00000000_00000000_00000000_85000000 0x00000000 PPPP
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# should put PKE into stalled mode, not executing following PKENOPs
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# Read STAT register; confirm PIS & INT bits set
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? 0x10003c00 0x00000c00 0x00000c00
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# Read CODE register; confirm PKE is stuck at bad code
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? 0x10003c80 0x85000000 0xffffffff
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# Resume PKE with STC
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! 0x10003c10 0x00000008
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# Read STAT register; confirm PIS & INT no longer set
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? 0x10003c00 0x00000000 0x00000c00
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# Read CODE register; confirm PKE executed trailing no-ops
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? 0x10003c80 0x00000000 0xffffffff
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#
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#
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# ---- STMASK/MASK ----
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@ -304,6 +333,37 @@
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# Read STAT register; confirm ER1 not set
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? 0x10003800 0x00000000 0x00002000
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#
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# Try stopping using STP bit this time
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# Test STCOL instruction; leave operand out for now
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1 0x31000000_00000000_00000000_00000000 0x00000000 PPPP
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# Read STAT register; confirm PPS field set at WAIT
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? 0x10003c00 0x00000001 0x00000003
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# Stop PKE after current instruction with STP bit
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! 0x10003c10 0x00000004
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# Supply operand - four words
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1 0x1234abcd_2345bcde_5432dcba_76543210 0x00000000 ....
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# Check column registers for value
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? 0x10003d40 0x76543210 0xffffffff
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? 0x10003d50 0x5432dcba 0xffffffff
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? 0x10003d60 0x2345bcde 0xffffffff
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? 0x10003d70 0x1234abcd 0xffffffff
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# Now send a new instruction with operands; this should stall
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1 0x31000000_00000000_00000000_00000000 0x00000000 PPPP
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1 0x11111111_22222222_33333333_44444444 0x00000000 ....
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# Confirm that PKE is continuing to stall due to PSS
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? 0x10003c00 0x00000100 0x00000100
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? 0x10003c00 0x00000100 0x00000100
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? 0x10003c00 0x00000100 0x00000100
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# Resume PKE with STC bit; it should process pent-up STCOL
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! 0x10003c10 0x00000008
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# Check column registers for value
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? 0x10003d40 0x44444444 0xffffffff
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? 0x10003d50 0x33333333 0xffffffff
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? 0x10003d60 0x22222222 0xffffffff
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? 0x10003d70 0x11111111 0xffffffff
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# Read STAT register; confirm ER1 not set
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? 0x10003c00 0x00000000 0x00002000
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#
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#
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# ---- MSKPATH3 ----
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#
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@ -331,3 +391,44 @@
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? 0x10005008 0x00000000 0xffffffff
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? 0x1000500c 0x00000000 0xffffffff
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#
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# Erroneously read PKE1-only registers on PKE0
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? 0x100038a0 0x00000000 0xffffffff
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? 0x100038b0 0x00000000 0xffffffff
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? 0x100038c0 0x00000000 0xffffffff
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? 0x100038e0 0x00000000 0xffffffff
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? 0x100038f0 0x00000000 0xffffffff
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#
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# Erroneously write PKE1-only registers on PKE0
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! 0x100038a0 0x00000000
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! 0x100038b0 0x00000000
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! 0x100038c0 0x00000000
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! 0x100038e0 0x00000000
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! 0x100038f0 0x00000000
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#
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# Erroneously read write-only registers
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? 0x10003810 0x00000000 0xffffffff
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? 0x10003c10 0x00000000 0xffffffff
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#
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# Erroneously write read-only registers
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! 0x10003c00 0x00000000
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! 0x10003c40 0x00000000
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! 0x10003c50 0x00000000
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! 0x10003c60 0x00000000
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! 0x10003c70 0x00000000
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! 0x10003c80 0x00000000
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! 0x10003c90 0x00000000
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! 0x10003ca0 0x00000000
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! 0x10003cb0 0x00000000
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! 0x10003cc0 0x00000000
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! 0x10003cd0 0x00000000
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! 0x10003ce0 0x00000000
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! 0x10003cf0 0x00000000
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! 0x10003d00 0x00000000
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! 0x10003d10 0x00000000
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! 0x10003d20 0x00000000
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! 0x10003d30 0x00000000
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! 0x10003d40 0x00000000
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! 0x10003d50 0x00000000
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! 0x10003d60 0x00000000
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! 0x10003d70 0x00000000
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#
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