Fix bugs in the simulation of the AArch64's ADDP, FADDP, LD1, CCMP and CCMP instructions.
* simulator.c (set_flags_for_sub32): Correct type of signbit. (CondCompare): Swap interpretation of bit 30. (DO_ADDP): Delete macro. (do_vec_ADDP): Copy source registers before starting to update destination register. (do_vec_FADDP): Likewise. (do_vec_load_store): Fix computation of sizeof_operation. (rbit64): Fix type of constant. (aarch64_step): When displaying insn value, display all 32 bits.
This commit is contained in:
Nick Clifton
parent
c40c8d4b67
commit
57aa174243
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@ -1,3 +1,15 @@
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2016-03-03 Nick Clifton <nickc@redhat.com>
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* simulator.c (set_flags_for_sub32): Correct type of signbit.
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(CondCompare): Swap interpretation of bit 30.
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(DO_ADDP): Delete macro.
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(do_vec_ADDP): Copy source registers before starting to update
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destination register.
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(do_vec_FADDP): Likewise.
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(do_vec_load_store): Fix computation of sizeof_operation.
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(rbit64): Fix type of constant.
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(aarch64_step): When displaying insn value, display all 32 bits.
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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@ -1625,7 +1625,7 @@ set_flags_for_sub32 (sim_cpu *cpu, uint32_t value1, uint32_t value2)
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{
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uint32_t result = value1 - value2;
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uint32_t flags = 0;
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uint32_t signbit = 1ULL << 31;
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uint32_t signbit = 1U << 31;
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if (result == 0)
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flags |= Z;
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@ -2454,7 +2454,7 @@ static void
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CondCompare (sim_cpu *cpu) /* aka: ccmp and ccmn */
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{
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/* instr[31] = size : 0 ==> 32 bit, 1 ==> 64 bit
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instr[30] = compare with positive (0) or negative value (1)
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instr[30] = compare with positive (1) or negative value (0)
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instr[29,21] = 1 1101 0010
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instr[20,16] = Rm or const
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instr[15,12] = cond
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@ -2477,7 +2477,7 @@ CondCompare (sim_cpu *cpu) /* aka: ccmp and ccmn */
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return;
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}
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negate = uimm (aarch64_get_instr (cpu), 30, 30) ? -1 : 1;
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negate = uimm (aarch64_get_instr (cpu), 30, 30) ? 1 : -1;
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rm = uimm (aarch64_get_instr (cpu), 20, 16);
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rn = uimm (aarch64_get_instr (cpu), 9, 5);
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@ -5089,21 +5089,6 @@ do_vec_sub_long (sim_cpu *cpu)
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}
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}
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#define DO_ADDP(FN) \
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do \
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{ \
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for (i = 0; i < range; i++) \
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{ \
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aarch64_set_vec_##FN (cpu, vd, i, \
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aarch64_get_vec_##FN (cpu, vn, i * 2) \
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+ aarch64_get_vec_##FN (cpu, vn, i * 2 + 1)); \
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aarch64_set_vec_##FN (cpu, vd, i + range, \
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aarch64_get_vec_##FN (cpu, vm, i * 2) \
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+ aarch64_get_vec_##FN (cpu, vm, i * 2 + 1)); \
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} \
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} \
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while (0)
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static void
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do_vec_ADDP (sim_cpu *cpu)
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{
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@ -5117,6 +5102,8 @@ do_vec_ADDP (sim_cpu *cpu)
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instr[9,5] = Vn
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instr[4,0] = V dest. */
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FRegister copy_vn;
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FRegister copy_vm;
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unsigned full = uimm (aarch64_get_instr (cpu), 30, 30);
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unsigned size = uimm (aarch64_get_instr (cpu), 23, 22);
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unsigned vm = uimm (aarch64_get_instr (cpu), 20, 16);
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@ -5128,28 +5115,50 @@ do_vec_ADDP (sim_cpu *cpu)
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NYI_assert (21, 21, 1);
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NYI_assert (15, 10, 0x2F);
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/* Make copies of the source registers in case vd == vn/vm. */
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copy_vn = cpu->fr[vn];
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copy_vm = cpu->fr[vm];
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switch (size)
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{
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case 0:
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range = full ? 8 : 4;
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DO_ADDP (u8);
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for (i = 0; i < range; i++)
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{
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aarch64_set_vec_u8 (cpu, vd, i,
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copy_vn.b[i * 2] + copy_vn.b[i * 2 + 1]);
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aarch64_set_vec_u8 (cpu, vd, i + range,
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copy_vm.b[i * 2] + copy_vm.b[i * 2 + 1]);
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}
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return;
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case 1:
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range = full ? 4 : 2;
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DO_ADDP (u16);
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for (i = 0; i < range; i++)
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{
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aarch64_set_vec_u16 (cpu, vd, i,
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copy_vn.h[i * 2] + copy_vn.h[i * 2 + 1]);
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aarch64_set_vec_u16 (cpu, vd, i + range,
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copy_vm.h[i * 2] + copy_vm.h[i * 2 + 1]);
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}
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return;
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case 2:
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range = full ? 2 : 1;
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DO_ADDP (u32);
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for (i = 0; i < range; i++)
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{
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aarch64_set_vec_u32 (cpu, vd, i,
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copy_vn.w[i * 2] + copy_vn.w[i * 2 + 1]);
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aarch64_set_vec_u32 (cpu, vd, i + range,
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copy_vm.w[i * 2] + copy_vm.w[i * 2 + 1]);
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}
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return;
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case 3:
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if (! full)
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HALT_UNALLOC;
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range = 1;
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DO_ADDP (u64);
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aarch64_set_vec_u64 (cpu, vd, 0, copy_vn.v[0] + copy_vn.v[1]);
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aarch64_set_vec_u64 (cpu, vd, 1, copy_vm.v[0] + copy_vm.v[1]);
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return;
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default:
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@ -6054,28 +6063,43 @@ do_vec_FADDP (sim_cpu *cpu)
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if (uimm (aarch64_get_instr (cpu), 22, 22))
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{
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/* Extract values before adding them incase vd == vn/vm. */
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double tmp1 = aarch64_get_vec_double (cpu, vn, 0);
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double tmp2 = aarch64_get_vec_double (cpu, vn, 1);
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double tmp3 = aarch64_get_vec_double (cpu, vm, 0);
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double tmp4 = aarch64_get_vec_double (cpu, vm, 1);
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if (! full)
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HALT_UNALLOC;
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aarch64_set_vec_double (cpu, vd, 0, aarch64_get_vec_double (cpu, vn, 0)
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+ aarch64_get_vec_double (cpu, vn, 1));
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aarch64_set_vec_double (cpu, vd, 1, aarch64_get_vec_double (cpu, vm, 0)
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+ aarch64_get_vec_double (cpu, vm, 1));
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aarch64_set_vec_double (cpu, vd, 0, tmp1 + tmp2);
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aarch64_set_vec_double (cpu, vd, 1, tmp3 + tmp4);
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}
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else
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{
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aarch64_set_vec_float (cpu, vd, 0, aarch64_get_vec_float (cpu, vn, 0)
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+ aarch64_get_vec_float (cpu, vn, 1));
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/* Extract values before adding them incase vd == vn/vm. */
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float tmp1 = aarch64_get_vec_float (cpu, vn, 0);
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float tmp2 = aarch64_get_vec_float (cpu, vn, 1);
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float tmp5 = aarch64_get_vec_float (cpu, vm, 0);
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float tmp6 = aarch64_get_vec_float (cpu, vm, 1);
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if (full)
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aarch64_set_vec_float (cpu, vd, 1, aarch64_get_vec_float (cpu, vn, 2)
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+ aarch64_get_vec_float (cpu, vn, 3));
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aarch64_set_vec_float (cpu, vd, full ? 2 : 1,
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aarch64_get_vec_float (cpu, vm, 0)
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+ aarch64_get_vec_float (cpu, vm, 1));
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if (full)
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aarch64_set_vec_float (cpu, vd, 3,
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aarch64_get_vec_float (cpu, vm, 2)
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+ aarch64_get_vec_float (cpu, vm, 3));
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{
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float tmp3 = aarch64_get_vec_float (cpu, vn, 2);
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float tmp4 = aarch64_get_vec_float (cpu, vn, 3);
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float tmp7 = aarch64_get_vec_float (cpu, vm, 2);
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float tmp8 = aarch64_get_vec_float (cpu, vm, 3);
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aarch64_set_vec_float (cpu, vd, 0, tmp1 + tmp2);
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aarch64_set_vec_float (cpu, vd, 1, tmp3 + tmp4);
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aarch64_set_vec_float (cpu, vd, 2, tmp5 + tmp6);
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aarch64_set_vec_float (cpu, vd, 3, tmp7 + tmp8);
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}
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else
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{
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aarch64_set_vec_float (cpu, vd, 0, tmp1 + tmp2);
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aarch64_set_vec_float (cpu, vd, 1, tmp5 + tmp6);
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}
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}
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}
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@ -10937,11 +10961,24 @@ do_vec_load_store (sim_cpu *cpu)
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sizeof_operation <<= uimm (aarch64_get_instr (cpu), 11, 10);
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break;
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case 2:
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case 6:
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case 10:
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case 7:
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sizeof_operation = 2 << uimm (aarch64_get_instr (cpu), 11, 10);
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/* One register, immediate offset variant. */
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sizeof_operation = 8;
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break;
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case 10:
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/* Two registers, immediate offset variant. */
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sizeof_operation = 16;
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break;
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case 6:
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/* Three registers, immediate offset variant. */
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sizeof_operation = 24;
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break;
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case 2:
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/* Four registers, immediate offset variant. */
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sizeof_operation = 32;
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break;
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default:
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@ -11421,7 +11458,7 @@ rbit64 (sim_cpu *cpu)
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for (i = 0; i < 64; i++)
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{
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result <<= 1;
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result |= (value & 1L);
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result |= (value & 1UL);
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value >>= 1;
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}
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aarch64_set_reg_u64 (cpu, rd, NO_SP, result);
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@ -13019,7 +13056,7 @@ aarch64_step (sim_cpu *cpu)
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aarch64_set_next_PC (cpu, pc + 4);
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aarch64_get_instr (cpu) = aarch64_get_mem_u32 (cpu, pc);
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TRACE_INSN (cpu, " pc = %" PRIx64 " instr = %x", pc,
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TRACE_INSN (cpu, " pc = %" PRIx64 " instr = %08x", pc,
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aarch64_get_instr (cpu));
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TRACE_DISASM (cpu, pc);
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