added vr5400 stuff, fixed "not" mask
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@ -1,3 +1,8 @@
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Mon Oct 27 22:34:03 1997 Ken Raeburn <raeburn@cygnus.com>
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* mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
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(WR_HILO, RD_HILO, MOD_HILO): New macros.
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Thu Oct 23 14:57:58 1997 Nick Clifton <nickc@cygnus.com>
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* v850-dis.c (disassemble): Replace // with /* ... */
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@ -62,6 +62,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define RD_HI INSN_READ_HI
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#define RD_LO INSN_READ_LO
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#define I1 INSN_ISA1
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#define I2 INSN_ISA2
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#define I3 INSN_ISA3
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@ -70,7 +71,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define L1 INSN_4010
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#define V1 INSN_4100
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#define T3 INSN_3900
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/* start-sanitize-r5900 */
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#define T5 INSN_5900
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/* end-sanitize-r5900 */
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@ -590,7 +590,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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/* nop is at the start of the table. */
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{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO },
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{"not", "d,v", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
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{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
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{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO },
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{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
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