Add files for ARM auto-IT patch
This commit is contained in:
Nick Clifton
parent
8d63875c54
commit
58ed6ca642
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@ -0,0 +1,15 @@
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#name: ARM IT automatic instruction generation 2
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#as: -mthumb -march=armv7a -mimplicit-it=always
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#objdump: -d --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: +file format .*arm.*
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Disassembly of section .text:
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00000000 <.text> 3a40 subs r2, #64
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00000002 <.text\+0x2> bfa1 itttt ge
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00000004 <.text\+0x4> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr}
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00000008 <.text\+0x8> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr}
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0000000c <.text\+0xc> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr}
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00000010 <.text\+0x10> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr}
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00000014 <.text\+0x14> dcf4 bgt.n 00000000 <.text>
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@ -0,0 +1,8 @@
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.syntax unified
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2: subs r2, r2, #64
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@ IT generated automatically
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stmge r0!, {r1, r3, ip, lr} @ 64 bytes at a time.
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stmge r0!, {r1, r3, ip, lr}
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stmge r0!, {r1, r3, ip, lr}
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stmge r0!, {r1, r3, ip, lr}
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bgt 2b @ This should not generate a new IT block
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@ -0,0 +1,15 @@
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#name: ARM IT automatic instruction generation 3
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#as: -mthumb -march=armv7a -mimplicit-it=always
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#objdump: -d --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: +file format .*arm.*
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Disassembly of section .text.one:
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00000000 <.text.one> 2800 cmp r0, #0
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00000002 <.text.one\+0x2> bf08 it eq
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00000004 <.text.one\+0x4> 3102 addeq r1, #2
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Disassembly of section .text.two:
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00000000 <.text.two> bf08 it eq
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00000002 <.text.two\+0x2> 3103 addeq r1, #3
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@ -0,0 +1,10 @@
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.syntax unified
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.thumb
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.section .text.one
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cmp r0, #0
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addeq r1, #2
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.data
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.word 33
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.section .text.two
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addeq r1, #3
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@ -0,0 +1,81 @@
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#name: ARM IT automatic instruction generation
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#as: -mthumb -march=armv7 -mimplicit-it=always
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#objdump: -d --prefix-addresses --show-raw-insn
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#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
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.*: +file format .*arm.*
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Disassembly of section .text:
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00000000 <main> f000 f821 bl 00000046 <main\+0x46>
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00000004 <main\+0x4> f000 f80c bl 00000020 <main\+0x20>
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00000008 <main\+0x8> f000 f813 bl 00000032 <main\+0x32>
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0000000c <main\+0xc> d142 bne.n 00000094 <main\+0x94>
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0000000e <main\+0xe> bf18 it ne
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00000010 <main\+0x10> 4487 addne pc, r0
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00000012 <main\+0x12> bf18 it ne
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00000014 <main\+0x14> e8d0 f001 tbbne \[r0, r1\]
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00000018 <main\+0x18> bf08 it eq
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0000001a <main\+0x1a> e8d1 f010 tbheq \[r1, r0, lsl #1\]
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0000001e <main\+0x1e> bf0a itet eq
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00000020 <main\+0x20> 2002 moveq r0, #2
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00000022 <main\+0x22> 2003 movne r0, #3
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00000024 <main\+0x24> 2004 moveq r0, #4
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00000026 <main\+0x26> bf16 itet ne
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00000028 <main\+0x28> 2002 movne r0, #2
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0000002a <main\+0x2a> 2003 moveq r0, #3
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0000002c <main\+0x2c> 2004 movne r0, #4
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0000002e <main\+0x2e> bf18 it ne
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00000030 <main\+0x30> 2001 movne r0, #1
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00000032 <main\+0x32> bf0c ite eq
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00000034 <main\+0x34> 2002 moveq r0, #2
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00000036 <main\+0x36> f8d1 f000 ldrne.w pc, \[r1\]
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0000003a <main\+0x3a> bf18 it ne
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0000003c <main\+0x3c> f000 f82a blne 00000094 <main\+0x94>
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00000040 <main\+0x40> bfb8 it lt
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00000042 <main\+0x42> f000 f828 bllt 00000096 <main\+0x96>
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00000046 <main\+0x46> bf17 itett ne
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00000048 <main\+0x48> 202d movne r0, #45
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0000004a <main\+0x4a> 2005 moveq r0, #5
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0000004c <main\+0x4c> 2006 movne r0, #6
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0000004e <main\+0x4e> 4487 addne pc, r0
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00000050 <main\+0x50> bf0d iteet eq
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00000052 <main\+0x52> 2007 moveq r0, #7
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00000054 <main\+0x54> 2008 movne r0, #8
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00000056 <main\+0x56> 2003 movne r0, #3
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00000058 <main\+0x58> 2004 moveq r0, #4
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0000005a <main\+0x5a> bf0b itete eq
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0000005c <main\+0x5c> 2005 moveq r0, #5
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0000005e <main\+0x5e> 2006 movne r0, #6
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00000060 <main\+0x60> 2007 moveq r0, #7
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00000062 <main\+0x62> 2008 movne r0, #8
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00000064 <main\+0x64> bf0c ite eq
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00000066 <main\+0x66> 2005 moveq r0, #5
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00000068 <main\+0x68> 2006 movne r0, #6
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0000006a <main\+0x6a> 4687 mov pc, r0
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0000006c <main\+0x6c> bf0b itete eq
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0000006e <main\+0x6e> 2007 moveq r0, #7
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00000070 <main\+0x70> 2008 movne r0, #8
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00000072 <main\+0x72> 2005 moveq r0, #5
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00000074 <main\+0x74> 2006 movne r0, #6
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00000076 <main\+0x76> 4487 add pc, r0
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00000078 <main\+0x78> bf0c ite eq
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0000007a <main\+0x7a> 2007 moveq r0, #7
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0000007c <main\+0x7c> 2008 movne r0, #8
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0000007e <main\+0x7e> bfcc ite gt
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00000080 <main\+0x80> 2009 movgt r0, #9
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00000082 <main\+0x82> 200a movle r0, #10
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00000084 <main\+0x84> bf08 it eq
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00000086 <main\+0x86> 200b moveq r0, #11
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00000088 <main\+0x88> bfd8 it le
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0000008a <main\+0x8a> 200c movle r0, #12
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0000008c <main\+0x8c> bf18 it ne
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0000008e <main\+0x8e> 200d movne r0, #13
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00000090 <main\+0x90> f... f... bl 0000000. <f.*>
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00000094 <f\+0x94> bd10 pop {r4, pc}
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00000096 <f\+0x96> f... f... bl 0000000. <f.*>
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0000009a <f\+0x9a> bfb8 it lt
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0000009c <f\+0x9c> 2000 movlt r0, #0
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0000009e <f\+0x9e> 4348 muls r0, r1
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000000a0 <f\+0xa0> bfb8 it lt
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000000a2 <f\+0xa2> 2000 movlt r0, #0
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000000a4 <f\+0xa4> 4348 muls r0, r1
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@ -0,0 +1,110 @@
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.syntax unified
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.arch armv7
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.thumb
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main:
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@These branches are to see the labels in the generated file
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bl .L888
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bl .L111
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bl .L777
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@No IT block here:
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bne .L4
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@The following groups should be an IT block each.
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@it ne
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addne.n pc, r0
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@it ne
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tbbne [r0, r1]
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@it eq
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tbheq [r1, r0]
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@The following group should be left as is:
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itet eq
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.L111: moveq r0, #2
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movne r0, #3
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moveq r0, #4
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@Same, reverted condition:
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itet ne
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movne r0, #2
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moveq r0, #3
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movne r0, #4
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@Two groups shall be generated, due to the label:
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movne r0, #1
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@ second group, the label should be at the IT insn
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.L777: moveq r0, #2
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ldrne pc, [r1]
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@it ne
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blne .L4
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@it lt
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bllt .L9
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@itett ne
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.L888: movne r0, #45
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moveq r0, #5
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movne r0, #6
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addne.n pc, r0
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@iteet eq
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moveq r0, #7
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movne r0, #8
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movne r0, #3
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moveq r0, #4
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@itete eq
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moveq r0, #5
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movne r0, #6
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moveq r0, #7
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movne r0, #8
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@ite eq - this group finishes due to the mov.n pc, rn
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moveq r0, #5
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movne r0, #6
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mov.n pc, r0
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@itete eq
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moveq r0, #7
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movne r0, #8
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moveq r0, #5
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movne r0, #6
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@this shall not generate an IT block
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add.n pc, r0
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@ite eq - testing condition change (eq -> gt)
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moveq r0, #7
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movne r0, #8
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@ite gt (group shall finish due to another condition change)
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movgt r0, #9
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movle r0, #10
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@it eq
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moveq r0, #11
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@it le
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movle r0, #12
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@it ne
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movne r0, #13
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bl f
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.L4:
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pop {r4, pc}
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.L9:
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bl f
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@Only the movlt shall be enclosed in the IT block
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movlt r0, #0
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muls r0, r0, r1
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@Same here:
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movlt r0, #0
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muls r0, r0, r1
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@ -0,0 +1,4 @@
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#name: Test unclosed IT block validation.
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#as: -march=armv7a
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#skip: *-*-*aout* *-*-pe
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#error-output: arm-it-bad-2.l
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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[^:]*:9: Warning: section '.text' finished with an open IT block.
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[^:]*:9: Warning: section 'second' finished with an open IT block.
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@ -0,0 +1,9 @@
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.syntax unified
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.text
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cmp r0, #0
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itt eq
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moveq r0, r1
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.section second
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itt ne
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movne r0, r1
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@ -0,0 +1,3 @@
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#name: Test automatic IT generation in Thumb-1 architectures.
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#as: -mimplicit-it=always
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#error-output: arm-it-bad-3.l
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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[^:]*:4: Error: thumb conditional instruction should be in IT block -- `moveq r1,r8'
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[^:]*:5: Error: thumb conditional instruction should be in IT block -- `movne r1,r9'
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@ -0,0 +1,6 @@
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.syntax unified
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.arch armv6
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.thumb
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moveq r1, r8
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movne r1, r9
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@ -0,0 +1,3 @@
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#name: Test IT block validation in ARM mode.
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#as: -march=armv7a -mimplicit-it=never
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#error-output: arm-it-bad.l
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@ -0,0 +1,3 @@
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[^:]*: Assembler messages:
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[^:]*:8: Error: incorrect condition in IT block -- `moveq r0,r1'
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[^:]*:10: Warning: conditional outside an IT block for Thumb.
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@ -0,0 +1,10 @@
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.syntax unified
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.text
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.global x
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x:
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mov r0, r1
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cmp r0, #0
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it ne
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moveq r0, r1
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bx lr
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movgt r1, r2
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@ -0,0 +1,62 @@
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# name: Mixed 16 and 32-bit Thumb conditional instructions
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# as: -march=armv6kt2 -mimplicit-it=always
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#skip: *-*-*aout*
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# source: thumb2_it.s
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# objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]+> bf05 ittet eq
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0+002 <[^>]+> 1880 addeq r0, r0, r2
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0+004 <[^>]+> 4440 addeq r0, r8
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0+006 <[^>]+> 1888 addne r0, r1, r2
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0+008 <[^>]+> eb11 0002 addseq.w r0, r1, r2
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0+00c <[^>]+> 4410 add r0, r2
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0+00e <[^>]+> 4440 add r0, r8
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0+010 <[^>]+> 1880 adds r0, r0, r2
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0+012 <[^>]+> eb10 0008 adds.w r0, r0, r8
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0+016 <[^>]+> 1888 adds r0, r1, r2
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0+018 <[^>]+> bf0a itet eq
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0+01a <[^>]+> 4310 orreq r0, r2
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0+01c <[^>]+> ea40 0008 orrne.w r0, r0, r8
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0+020 <[^>]+> ea50 0002 orrseq.w r0, r0, r2
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0+024 <[^>]+> ea40 0002 orr.w r0, r0, r2
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0+028 <[^>]+> ea40 0008 orr.w r0, r0, r8
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0+02c <[^>]+> 4310 orrs r0, r2
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0+02e <[^>]+> bf01 itttt eq
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0+030 <[^>]+> 4090 lsleq r0, r2
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0+032 <[^>]+> fa00 f008 lsleq.w r0, r0, r8
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0+036 <[^>]+> fa01 f002 lsleq.w r0, r1, r2
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0+03a <[^>]+> fa10 f002 lslseq.w r0, r0, r2
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0+03e <[^>]+> bf02 ittt eq
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0+040 <[^>]+> 0048 lsleq r0, r1, #1
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0+042 <[^>]+> ea4f 0048 moveq.w r0, r8, lsl #1
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0+046 <[^>]+> ea5f 0040 movseq.w r0, r0, lsl #1
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0+04a <[^>]+> fa00 f002 lsl.w r0, r0, r2
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0+04e <[^>]+> 4090 lsls r0, r2
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0+050 <[^>]+> ea4f 0041 mov.w r0, r1, lsl #1
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0+054 <[^>]+> 0048 lsls r0, r1, #1
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0+056 <[^>]+> bf01 itttt eq
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0+058 <[^>]+> 4288 cmpeq r0, r1
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0+05a <[^>]+> 4540 cmpeq r0, r8
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0+05c <[^>]+> 4608 moveq r0, r1
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0+05e <[^>]+> ea5f 0001 movseq.w r0, r1
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0+062 <[^>]+> bf08 it eq
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0+064 <[^>]+> 4640 moveq r0, r8
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0+066 <[^>]+> 4608 mov r0, r1
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0+068 <[^>]+> 1c08 adds r0, r1, #0
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0+06a <[^>]+> ea5f 0008 movs.w r0, r8
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0+06e <[^>]+> bf01 itttt eq
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0+070 <[^>]+> 43c8 mvneq r0, r1
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0+072 <[^>]+> ea6f 0008 mvneq.w r0, r8
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0+076 <[^>]+> ea7f 0001 mvnseq.w r0, r1
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0+07a <[^>]+> 42c8 cmneq r0, r1
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0+07c <[^>]+> ea6f 0001 mvn.w r0, r1
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0+080 <[^>]+> 43c8 mvns r0, r1
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0+082 <[^>]+> bf02 ittt eq
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0+084 <[^>]+> 4248 negeq r0, r1
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0+086 <[^>]+> f1c8 0000 rsbeq r0, r8, #0 ; 0x0
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0+08a <[^>]+> f1d1 0000 rsbseq r0, r1, #0 ; 0x0
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0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 ; 0x0
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0+092 <[^>]+> 4248 negs r0, r1
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@ -0,0 +1,4 @@
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#name: Invalid IT instructions
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#as: -mimplicit-it=always
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#source: thumb2_it_bad.s
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#error-output: thumb2_it_bad.l
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