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RISC-V: Fix wrong use of s0 register name. 

s0 is listed as both an int register name and an FP register name.  The FP reg
name is wrong.  This looks like a simple editting error, and has an easy fix.
Tested with riscv64-linux build and check, with no regressions.

	gdb/
	* riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8.
This commit is contained in:
Jim Wilson 2019-01-03 11:12:17 -08:00
parent ef1ad42b8b
commit 592d8c0a5d
2 changed files with 5 additions and 1 deletions
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4
gdb/ChangeLog
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@ -1,3 +1,7 @@
2019-01-03 Jim Wilson <jimw@sifive.com>
* riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8.
2019-01-02 Tom Tromey <tom@tromey.com>
* xml-tdesc.c (xml_cache): Hold a target_desc_up.

2
gdb/riscv-tdep.c
View File

@ -185,7 +185,7 @@ static const struct riscv_register_feature riscv_freg_feature =
{ RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
{ RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
{ RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
{ RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true },
{ RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true },
{ RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
{ RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
{ RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },