2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* NEWS: Mention XSAVE.  Change CLMUL to PCLMUL.

	* config/tc-i386.c (cpu_arch): Add .pclmul.
	(md_show_usage): Replace clmul with pclmul.
	* doc/c-i386.texi: Likewise.

gas/testsuite/

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/arch-10.s: Likewise.
	* gas/i386/clmul-intel.d: Likewise.
	* gas/i386/clmul.d: Likewise.
	* gas/i386/clmul.s: Likewise.
	* gas/i386/x86-64-arch-2.s: Likewise.
	* gas/i386/x86-64-clmul-intel.d: Likewise.
	* gas/i386/x86-64-clmul.d: Likewise.
	* gas/i386/x86-64-clmul.s: Likewise.

	* gas/i386/arch-10.d: Replace clmul with pclmul.
	* gas/i386/x86-64-arch-2.d: Likewise.

opcodes/

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.
This commit is contained in:
H.J. Lu 2008-04-04 16:34:23 +00:00
parent aad4b0482f
commit 594ab6a333
24 changed files with 75 additions and 33 deletions

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@ -1,3 +1,11 @@
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
* config/tc-i386.c (cpu_arch): Add .pclmul.
(md_show_usage): Replace clmul with pclmul.
* doc/c-i386.texi: Likewise.
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.

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@ -2,7 +2,7 @@
* New command line option -msse2avx for x86 target to encode SSE
instructions with VEX prefix.
* Add Intel AES, CLMUL, AVX/FMA support for x86 target.
* Add Intel XSAVE, AES, PCLMUL, AVX/FMA support for x86 target.
* New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
-mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg,

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@ -647,8 +647,10 @@ static const arch_entry cpu_arch[] =
CPU_XSAVE_FLAGS },
{ ".aes", PROCESSOR_UNKNOWN,
CPU_AES_FLAGS },
{ ".pclmul", PROCESSOR_UNKNOWN,
CPU_PCLMUL_FLAGS },
{ ".clmul", PROCESSOR_UNKNOWN,
CPU_CLMUL_FLAGS },
CPU_PCLMUL_FLAGS },
{ ".fma", PROCESSOR_UNKNOWN,
CPU_FMA_FLAGS },
{ ".3dnow", PROCESSOR_UNKNOWN,
@ -8045,7 +8047,7 @@ md_show_usage (stream)
generic32, generic64\n\
EXTENSION is combination of:\n\
mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
avx, vmx, smx, xsave, aes, clmul, fma, 3dnow,\n\
avx, vmx, smx, xsave, aes, pclmul, fma, 3dnow,\n\
3dnowa, sse4a, sse5, svme, abm, padlock\n"));
fprintf (stream, _("\
-mtune=CPU optimize for CPU, CPU is one of:\n\

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@ -125,7 +125,7 @@ accept various extension mnemonics. For example,
@code{smx},
@code{xsave},
@code{aes},
@code{clmul},
@code{pclmul},
@code{fma},
@code{3dnow},
@code{3dnowa},
@ -832,7 +832,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
@item @samp{.aes} @tab @samp{.clmul} @tab @samp{.fma}
@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.svme} @tab @samp{.abm}
@item @samp{.padlock}

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@ -1,3 +1,21 @@
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.s: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/arch-10.d: Replace clmul with pclmul.
* gas/i386/x86-64-arch-2.d: Likewise.
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,

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@ -53,7 +53,7 @@ GAS LISTING .*
[ ]*26[ ]+xgetbv
[ ]*27[ ]+\# AES
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
[ ]*29[ ]+\# CLMUL
[ ]*29[ ]+\# PCLMUL
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
[ ]*31[ ]+\# FMA
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

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@ -52,7 +52,7 @@ GAS LISTING .*
[ ]*26[ ]+xgetbv
[ ]*27[ ]+\# AES
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
[ ]*29[ ]+\# CLMUL
[ ]*29[ ]+\# PCLMUL
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
[ ]*31[ ]+\# FMA
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

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@ -48,7 +48,7 @@ GAS LISTING .*
[ ]*26[ ]+xgetbv
[ ]*27[ ]+\# AES
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
[ ]*29[ ]+\# CLMUL
[ ]*29[ ]+\# PCLMUL
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
[ ]*31[ ]+\# FMA
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

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@ -46,7 +46,7 @@ GAS LISTING .*
[ ]*26[ ]+xgetbv
[ ]*27[ ]+\# AES
[ ]*28[ ]+aesenc \(%ecx\),%xmm0
[ ]*29[ ]+\# CLMUL
[ ]*29[ ]+\# PCLMUL
[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
[ ]*31[ ]+\# FMA
[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

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@ -1,4 +1,4 @@
#as: -march=i686+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
#objdump: -dw
#name: i386 arch 10

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@ -26,7 +26,7 @@ getsec
xgetbv
# AES
aesenc (%ecx),%xmm0
# CLMUL
# PCLMUL
pclmulqdq $8,%xmm1,%xmm0
# FMA
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

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@ -1,6 +1,6 @@
#source: clmul.s
#objdump: -dw -Mintel
#name: i386 CLMUL (Intel mode)
#name: i386 PCLMUL (Intel mode)
.*: +file format .*

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@ -1,5 +1,5 @@
#objdump: -dw
#name: i386 CLMUL
#name: i386 PCLMUL
.*: +file format .*

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@ -1,4 +1,4 @@
# Check CLMUL new instructions.
# Check PCLMUL new instructions.
.text
foo:

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@ -1,4 +1,4 @@
#as: -march=generic64+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
#objdump: -dw
#name: x86-64 arch 2

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@ -26,7 +26,7 @@ getsec
xgetbv
# AES
aesenc (%rcx),%xmm0
# CLMUL
# PCLMUL
pclmulqdq $8,%xmm1,%xmm0
# FMA
vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7

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@ -1,7 +1,7 @@
#source: x86-64-clmul.s
#as: -J
#objdump: -dw -Mintel
#name: x86-64 CLMUL (Intel mode)
#name: x86-64 PCLMUL (Intel mode)
.*: +file format .*

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@ -1,6 +1,6 @@
#as: -J
#objdump: -dw
#name: x86-64 CLMUL
#name: x86-64 PCLMUL
.*: +file format .*

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@ -1,4 +1,4 @@
# Check 64bit CLMUL new instructions.
# Check 64bit PCLMUL new instructions.
.text
foo:

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@ -1,3 +1,17 @@
2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
with CPU_PCLMUL_FLAGS/CpuPCLMUL.
(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
* i386-opc.tbl: Likewise.
* i386-opc.h (CpuCLMUL): Renamed to ...
(CpuPCLMUL): This.
(CpuFMA): Updated.
(i386_cpu_flags): Replace cpuclmul with cpupclmul.
* i386-init.h: Regenerated.
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.

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@ -104,8 +104,8 @@ static initializer cpu_flag_init [] =
"CpuXsave" },
{ "CPU_AES_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
{ "CPU_CLMUL_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuCLMUL" },
{ "CPU_PCLMUL_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" },
{ "CPU_FMA_FLAGS",
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
{ "CPU_3DNOW_FLAGS",
@ -263,7 +263,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuABM),
BITFIELD (CpuXsave),
BITFIELD (CpuAES),
BITFIELD (CpuCLMUL),
BITFIELD (CpuPCLMUL),
BITFIELD (CpuFMA),
BITFIELD (CpuLM),
BITFIELD (Cpu64),

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@ -146,7 +146,7 @@
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
#define CPU_CLMUL_FLAGS \
#define CPU_PCLMUL_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }

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@ -86,10 +86,10 @@
#define CpuXsave (CpuAVX + 1)
/* AES support required */
#define CpuAES (CpuXsave + 1)
/* CLMUL support required */
#define CpuCLMUL (CpuAES + 1)
/* PCLMUL support required */
#define CpuPCLMUL (CpuAES + 1)
/* FMA support required */
#define CpuFMA (CpuCLMUL + 1)
#define CpuFMA (CpuPCLMUL + 1)
/* 64bit support available, used by -march= in assembler. */
#define CpuLM (CpuFMA + 1)
/* 64bit support required */
@ -142,7 +142,7 @@ typedef union i386_cpu_flags
unsigned int cpuavx:1;
unsigned int cpuxsave:1;
unsigned int cpuaes:1;
unsigned int cpuclmul:1;
unsigned int cpupclmul:1;
unsigned int cpufma:1;
unsigned int cpulm:1;
unsigned int cpu64:1;

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@ -1722,13 +1722,13 @@ aesenclast, 2, 0x660f38dd, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_
aesimc, 2, 0x660f38db, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
aeskeygenassist, 3, 0x660f3adf, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
// CLMUL
// PCLMUL
pclmulqdq, 3, 0x660f3a44, None, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmulqdq, 3, 0x660f3a44, None, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
// AVX instructions.