gas/
2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE. Change CLMUL to PCLMUL. * config/tc-i386.c (cpu_arch): Add .pclmul. (md_show_usage): Replace clmul with pclmul. * doc/c-i386.texi: Likewise. gas/testsuite/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/arch-10.d: Replace clmul with pclmul. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL with CPU_PCLMUL_FLAGS/CpuPCLMUL. (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. * i386-opc.tbl: Likewise. * i386-opc.h (CpuCLMUL): Renamed to ... (CpuPCLMUL): This. (CpuFMA): Updated. (i386_cpu_flags): Replace cpuclmul with cpupclmul. * i386-init.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
aad4b0482f
commit
594ab6a333
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@ -1,3 +1,11 @@
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2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
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* NEWS: Mention XSAVE. Change CLMUL to PCLMUL.
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* config/tc-i386.c (cpu_arch): Add .pclmul.
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(md_show_usage): Replace clmul with pclmul.
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* doc/c-i386.texi: Likewise.
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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
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* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
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2
gas/NEWS
2
gas/NEWS
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@ -2,7 +2,7 @@
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* New command line option -msse2avx for x86 target to encode SSE
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instructions with VEX prefix.
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* Add Intel AES, CLMUL, AVX/FMA support for x86 target.
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* Add Intel XSAVE, AES, PCLMUL, AVX/FMA support for x86 target.
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* New command line options, -march=CPU[,+EXTENSION...], -mtune=CPU,
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-mmnemonic=[att|intel], -msyntax=[att|intel], -mindex-reg,
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@ -647,8 +647,10 @@ static const arch_entry cpu_arch[] =
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CPU_XSAVE_FLAGS },
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{ ".aes", PROCESSOR_UNKNOWN,
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CPU_AES_FLAGS },
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{ ".pclmul", PROCESSOR_UNKNOWN,
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CPU_PCLMUL_FLAGS },
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{ ".clmul", PROCESSOR_UNKNOWN,
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CPU_CLMUL_FLAGS },
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CPU_PCLMUL_FLAGS },
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{ ".fma", PROCESSOR_UNKNOWN,
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CPU_FMA_FLAGS },
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{ ".3dnow", PROCESSOR_UNKNOWN,
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@ -8045,7 +8047,7 @@ md_show_usage (stream)
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generic32, generic64\n\
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EXTENSION is combination of:\n\
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mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
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avx, vmx, smx, xsave, aes, clmul, fma, 3dnow,\n\
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avx, vmx, smx, xsave, aes, pclmul, fma, 3dnow,\n\
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3dnowa, sse4a, sse5, svme, abm, padlock\n"));
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fprintf (stream, _("\
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-mtune=CPU optimize for CPU, CPU is one of:\n\
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@ -125,7 +125,7 @@ accept various extension mnemonics. For example,
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@code{smx},
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@code{xsave},
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@code{aes},
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@code{clmul},
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@code{pclmul},
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@code{fma},
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@code{3dnow},
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@code{3dnowa},
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@ -832,7 +832,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
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@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
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@item @samp{.aes} @tab @samp{.clmul} @tab @samp{.fma}
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@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.svme} @tab @samp{.abm}
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@item @samp{.padlock}
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@ -1,3 +1,21 @@
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2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL.
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* gas/i386/arch-10-2.l: Likewise.
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* gas/i386/arch-10-3.l: Likewise.
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* gas/i386/arch-10-4.l: Likewise.
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* gas/i386/arch-10.s: Likewise.
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* gas/i386/clmul-intel.d: Likewise.
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* gas/i386/clmul.d: Likewise.
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* gas/i386/clmul.s: Likewise.
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* gas/i386/x86-64-arch-2.s: Likewise.
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* gas/i386/x86-64-clmul-intel.d: Likewise.
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* gas/i386/x86-64-clmul.d: Likewise.
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* gas/i386/x86-64-clmul.s: Likewise.
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* gas/i386/arch-10.d: Replace clmul with pclmul.
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* gas/i386/x86-64-arch-2.d: Likewise.
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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
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@ -53,7 +53,7 @@ GAS LISTING .*
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[ ]*26[ ]+xgetbv
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[ ]*27[ ]+\# AES
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[ ]*28[ ]+aesenc \(%ecx\),%xmm0
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[ ]*29[ ]+\# CLMUL
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[ ]*29[ ]+\# PCLMUL
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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@ -52,7 +52,7 @@ GAS LISTING .*
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[ ]*26[ ]+xgetbv
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[ ]*27[ ]+\# AES
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[ ]*28[ ]+aesenc \(%ecx\),%xmm0
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[ ]*29[ ]+\# CLMUL
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[ ]*29[ ]+\# PCLMUL
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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@ -48,7 +48,7 @@ GAS LISTING .*
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[ ]*26[ ]+xgetbv
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[ ]*27[ ]+\# AES
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[ ]*28[ ]+aesenc \(%ecx\),%xmm0
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[ ]*29[ ]+\# CLMUL
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[ ]*29[ ]+\# PCLMUL
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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@ -46,7 +46,7 @@ GAS LISTING .*
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[ ]*26[ ]+xgetbv
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[ ]*27[ ]+\# AES
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[ ]*28[ ]+aesenc \(%ecx\),%xmm0
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[ ]*29[ ]+\# CLMUL
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[ ]*29[ ]+\# PCLMUL
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[ ]*30[ ]+pclmulqdq \$8,%xmm1,%xmm0
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[ ]*31[ ]+\# FMA
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[ ]*32[ ]+vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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@ -1,4 +1,4 @@
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#as: -march=i686+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
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#as: -march=i686+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
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#objdump: -dw
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#name: i386 arch 10
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@ -26,7 +26,7 @@ getsec
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xgetbv
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# AES
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aesenc (%ecx),%xmm0
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# CLMUL
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# PCLMUL
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pclmulqdq $8,%xmm1,%xmm0
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# FMA
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vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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@ -1,6 +1,6 @@
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#source: clmul.s
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#objdump: -dw -Mintel
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#name: i386 CLMUL (Intel mode)
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#name: i386 PCLMUL (Intel mode)
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.*: +file format .*
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@ -1,5 +1,5 @@
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#objdump: -dw
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#name: i386 CLMUL
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#name: i386 PCLMUL
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.*: +file format .*
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@ -1,4 +1,4 @@
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# Check CLMUL new instructions.
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# Check PCLMUL new instructions.
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.text
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foo:
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@ -1,4 +1,4 @@
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#as: -march=generic64+avx+vmx+smx+xsave+aes+clmul+fma+sse5+3dnowa+svme+padlock
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#as: -march=generic64+avx+vmx+smx+xsave+aes+pclmul+fma+sse5+3dnowa+svme+padlock
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#objdump: -dw
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#name: x86-64 arch 2
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@ -26,7 +26,7 @@ getsec
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xgetbv
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# AES
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aesenc (%rcx),%xmm0
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# CLMUL
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# PCLMUL
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pclmulqdq $8,%xmm1,%xmm0
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# FMA
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vfmaddpd %ymm4,%ymm6,%ymm2,%ymm7
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@ -1,7 +1,7 @@
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#source: x86-64-clmul.s
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#as: -J
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#objdump: -dw -Mintel
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#name: x86-64 CLMUL (Intel mode)
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#name: x86-64 PCLMUL (Intel mode)
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.*: +file format .*
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@ -1,6 +1,6 @@
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#as: -J
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#objdump: -dw
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#name: x86-64 CLMUL
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#name: x86-64 PCLMUL
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.*: +file format .*
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@ -1,4 +1,4 @@
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# Check 64bit CLMUL new instructions.
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# Check 64bit PCLMUL new instructions.
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.text
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foo:
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@ -1,3 +1,17 @@
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2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
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with CPU_PCLMUL_FLAGS/CpuPCLMUL.
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(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
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* i386-opc.tbl: Likewise.
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* i386-opc.h (CpuCLMUL): Renamed to ...
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(CpuPCLMUL): This.
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(CpuFMA): Updated.
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(i386_cpu_flags): Replace cpuclmul with cpupclmul.
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* i386-init.h: Regenerated.
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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (OP_E_register): New.
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@ -104,8 +104,8 @@ static initializer cpu_flag_init [] =
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"CpuXsave" },
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{ "CPU_AES_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" },
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{ "CPU_CLMUL_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuCLMUL" },
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{ "CPU_PCLMUL_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" },
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{ "CPU_FMA_FLAGS",
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"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
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{ "CPU_3DNOW_FLAGS",
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@ -263,7 +263,7 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuABM),
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BITFIELD (CpuXsave),
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BITFIELD (CpuAES),
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BITFIELD (CpuCLMUL),
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BITFIELD (CpuPCLMUL),
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BITFIELD (CpuFMA),
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BITFIELD (CpuLM),
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BITFIELD (Cpu64),
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@ -146,7 +146,7 @@
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
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0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
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#define CPU_CLMUL_FLAGS \
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#define CPU_PCLMUL_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \
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0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
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@ -86,10 +86,10 @@
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#define CpuXsave (CpuAVX + 1)
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/* AES support required */
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#define CpuAES (CpuXsave + 1)
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/* CLMUL support required */
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#define CpuCLMUL (CpuAES + 1)
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/* PCLMUL support required */
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#define CpuPCLMUL (CpuAES + 1)
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/* FMA support required */
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#define CpuFMA (CpuCLMUL + 1)
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#define CpuFMA (CpuPCLMUL + 1)
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/* 64bit support available, used by -march= in assembler. */
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#define CpuLM (CpuFMA + 1)
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/* 64bit support required */
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@ -142,7 +142,7 @@ typedef union i386_cpu_flags
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unsigned int cpuavx:1;
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unsigned int cpuxsave:1;
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unsigned int cpuaes:1;
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unsigned int cpuclmul:1;
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unsigned int cpupclmul:1;
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unsigned int cpufma:1;
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unsigned int cpulm:1;
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unsigned int cpu64:1;
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@ -1722,13 +1722,13 @@ aesenclast, 2, 0x660f38dd, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_
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aesimc, 2, 0x660f38db, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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aeskeygenassist, 3, 0x660f3adf, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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// CLMUL
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// PCLMUL
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pclmulqdq, 3, 0x660f3a44, None, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmulqdq, 3, 0x660f3a44, None, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
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// AVX instructions.
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Loading…
Reference in New Issue