bfd/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * cpu-ia64-opc.c (ins_immu5b): New. (ext_immu5b): Likewise. (elf64_ia64_operands): Add IMMU5b. gas/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b. gas/testsuite/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/opc-i.s: Add tests for tf. * gas/ia64/pseudo.s: Likewise. * gas/ia64/opc-i.d: Updated. * gas/ia64/pseudo.d: Likewise. include/opcode/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. opcodes/ 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> * ia64-opc-i.c (bXc): New. (mXc): Likewise. (OpX2TaTbYaXcC): Likewise. (TF). Likewise. (TFCM). Likewise. (ia64_opcodes_i): Add instructions for tf. * ia64-opc.h (IMMU5b): New. * ia64-asmtab.c: Regenerated.
This commit is contained in:
H.J. Lu
parent
921286914f
commit
59cf82fe74
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@ -1,3 +1,9 @@
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2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
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* cpu-ia64-opc.c (ins_immu5b): New.
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(ext_immu5b): Likewise.
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(elf64_ia64_operands): Add IMMU5b.
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2006-02-21 Alan Modra <amodra@bigpond.net.au>
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PR ld/2218
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@ -1,4 +1,4 @@
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/* Copyright 1998, 1999, 2000, 2001, 2002, 2003
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/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
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Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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@ -113,6 +113,29 @@ ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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return 0;
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}
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static const char*
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ins_immu5b (const struct ia64_operand *self, ia64_insn value,
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ia64_insn *code)
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{
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if (value < 32 || value > 63)
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return "value must be between 32 and 63";
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return ins_immu (self, value - 32, code);
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}
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static const char*
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ext_immu5b (const struct ia64_operand *self, ia64_insn code,
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ia64_insn *valuep)
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{
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const char *result;
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result = ext_immu (self, code, valuep);
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if (result)
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return result;
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*valuep = *valuep + 32;
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return 0;
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}
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static const char*
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ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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@ -506,6 +529,8 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
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"a 1-bit integer (-1, 0)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
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"a 2-bit unsigned (0-3)" },
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{ ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */
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"a 5-bit unsigned (32 + (0-31))" },
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{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
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"a 7-bit unsigned (0-127)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
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@ -1,3 +1,7 @@
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2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
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2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-ia64.c: Update copyright years.
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@ -5914,6 +5914,17 @@ operand_match (idesc, index, e)
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return OPERAND_MATCH;
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break;
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case IA64_OPND_IMMU5b:
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if (e->X_op == O_constant)
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{
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val = e->X_add_number;
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if (val >= 32 && val <= 63)
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return OPERAND_MATCH;
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else
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return OPERAND_OUT_OF_RANGE;
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}
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break;
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case IA64_OPND_CCNT5:
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case IA64_OPND_CNT5:
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case IA64_OPND_CNT6:
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@ -1,3 +1,10 @@
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2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
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* gas/ia64/opc-i.s: Add tests for tf.
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* gas/ia64/pseudo.s: Likewise.
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* gas/ia64/opc-i.d: Updated.
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* gas/ia64/pseudo.d: Likewise.
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2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
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* gas/ia64/dv-raw-err.s: Add check for vmsw.0.
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@ -259,6 +259,54 @@ Disassembly of section \.text:
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ab0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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ab6: 01 00 00 03 80 03 \(p07\) hint\.i 0x0
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abc: 00 00 06 00 \(p07\) hint\.i 0x0
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ac0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0
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ac6: 00 00 00 02 80 e3 nop\.f 0x0
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acc: ff ff 07 08 \(p07\) hint\.i 0x1fffff;;
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ac0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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ac6: f1 ff ff 03 04 40 \(p07\) hint\.i 0x1fffff
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acc: f0 04 0c 50 tf\.z p2,p3=39
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ad0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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ad6: 20 7c 02 06 28 40 tf\.z\.unc p2,p3=39
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adc: f0 04 0c 58 tf\.z\.and p2,p3=39
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ae0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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ae6: 20 78 02 86 28 40 tf\.z\.or p2,p3=39
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aec: f0 04 0c 59 tf\.z\.or\.andcm p2,p3=39
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af0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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af6: 30 7c 02 84 28 60 tf\.nz\.or p3,p2=39
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afc: f8 04 08 58 tf\.nz\.and p3,p2=39
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b00: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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b06: 30 7c 02 84 2c 60 tf\.nz\.or\.andcm p3,p2=39
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b0c: f0 04 08 50 tf\.z p3,p2=39
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b10: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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b16: 30 7c 02 04 28 40 tf\.z\.unc p3,p2=39
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b1c: f8 04 0c 58 tf\.nz\.and p2,p3=39
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b20: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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b26: 20 7c 02 86 28 40 tf\.nz\.or p2,p3=39
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b2c: f8 04 0c 59 tf\.nz\.or\.andcm p2,p3=39
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b30: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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b36: 30 78 02 84 28 60 tf\.z\.or p3,p2=39
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b3c: f0 04 08 58 tf\.z\.and p3,p2=39
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b40: 00 00 00 00 01 00 \[MII\] nop\.m 0x0
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b46: 30 78 02 84 ac 43 tf\.z\.or\.andcm p3,p2=39
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b4c: f0 04 0c 50 \(p07\) tf\.z p2,p3=39
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b50: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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b56: 21 7c 02 06 a8 43 \(p07\) tf\.z\.unc p2,p3=39
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b5c: f0 04 0c 58 \(p07\) tf\.z\.and p2,p3=39
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b60: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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b66: 21 78 02 86 a8 43 \(p07\) tf\.z\.or p2,p3=39
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b6c: f0 04 0c 59 \(p07\) tf\.z\.or\.andcm p2,p3=39
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b70: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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b76: 31 7c 02 84 a8 63 \(p07\) tf\.nz\.or p3,p2=39
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b7c: f8 04 08 58 \(p07\) tf\.nz\.and p3,p2=39
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b80: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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b86: 31 7c 02 84 ac 63 \(p07\) tf\.nz\.or\.andcm p3,p2=39
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b8c: f0 04 08 50 \(p07\) tf\.z p3,p2=39
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b90: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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b96: 31 7c 02 04 a8 43 \(p07\) tf\.z\.unc p3,p2=39
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b9c: f8 04 0c 58 \(p07\) tf\.nz\.and p2,p3=39
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ba0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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ba6: 21 7c 02 86 a8 43 \(p07\) tf\.nz\.or p2,p3=39
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bac: f8 04 0c 59 \(p07\) tf\.nz\.or\.andcm p2,p3=39
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bb0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0
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bb6: 31 78 02 84 a8 63 \(p07\) tf\.z\.or p3,p2=39
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bbc: f0 04 08 58 \(p07\) tf\.z\.and p3,p2=39
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bc0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0
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bc6: 00 00 00 02 80 63 nop\.f 0x0
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bcc: f0 04 08 59 \(p07\) tf\.z\.or\.andcm p3,p2=39;;
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@ -220,3 +220,39 @@ _start:
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(p7) hint.i 0
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(p7) hint.i @pause
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(p7) hint.i 0x1fffff
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# instructions added by SDM2.2:
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tf.z p2, p3 = 39
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tf.z.unc p2, p3 = 39
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tf.z.and p2, p3 = 39
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tf.z.or p2, p3 = 39
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tf.z.or.andcm p2, p3 = 39
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tf.z.orcm p2, p3 = 39
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tf.z.andcm p2, p3 = 39
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tf.z.and.orcm p2, p3 = 39
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tf.nz p2, p3 = 39
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tf.nz.unc p2, p3 = 39
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tf.nz.and p2, p3 = 39
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tf.nz.or p2, p3 = 39
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tf.nz.or.andcm p2, p3 = 39
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tf.nz.orcm p2, p3 = 39
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tf.nz.andcm p2, p3 = 39
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tf.nz.and.orcm p2, p3 = 39
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(p7) tf.z p2, p3 = 39
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(p7) tf.z.unc p2, p3 = 39
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(p7) tf.z.and p2, p3 = 39
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(p7) tf.z.or p2, p3 = 39
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(p7) tf.z.or.andcm p2, p3 = 39
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(p7) tf.z.orcm p2, p3 = 39
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(p7) tf.z.andcm p2, p3 = 39
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(p7) tf.z.and.orcm p2, p3 = 39
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(p7) tf.nz p2, p3 = 39
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(p7) tf.nz.unc p2, p3 = 39
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(p7) tf.nz.and p2, p3 = 39
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(p7) tf.nz.or p2, p3 = 39
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(p7) tf.nz.or.andcm p2, p3 = 39
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(p7) tf.nz.orcm p2, p3 = 39
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(p7) tf.nz.andcm p2, p3 = 39
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(p7) tf.nz.and.orcm p2, p3 = 39
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@ -25,3 +25,5 @@ Disassembly of section \.text:
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[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+st16 \[r0\]=r0,ar\.csd
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[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tbit\.z p0,p12=r0,0
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[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tnat\.z p0,p13=r0(;;)?
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#...
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[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tf\.z p3,p2=33(;;)?
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@ -13,3 +13,7 @@ _start:
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st16 [r0] = r0
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tbit.nz p12 = r0, 0
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tnat.nz p13 = r0
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# instructions added by SDM2.2:
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tf.nz p2, p3 = 33
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@ -1,3 +1,7 @@
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2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
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* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
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2006-01-31 Paul Brook <paul@codesourcery.com>
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Richard Earnshaw <rearnsha@arm.com>
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|
|
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@ -1,6 +1,7 @@
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/* ia64.h -- Header file for ia64 opcode table
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Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
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Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006
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Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
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#ifndef opcode_ia64_h
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#define opcode_ia64_h
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@ -102,6 +103,7 @@ enum ia64_opnd
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IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
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IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
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IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
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IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */
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IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
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IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
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IA64_OPND_SOF, /* 8-bit stack frame size */
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|
|
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|||
|
|
@ -1,3 +1,16 @@
|
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2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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* ia64-opc-i.c (bXc): New.
|
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(mXc): Likewise.
|
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(OpX2TaTbYaXcC): Likewise.
|
||||
(TF). Likewise.
|
||||
(TFCM). Likewise.
|
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(ia64_opcodes_i): Add instructions for tf.
|
||||
|
||||
* ia64-opc.h (IMMU5b): New.
|
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|
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* ia64-asmtab.c: Regenerated.
|
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|
||||
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
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|
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* ia64-gen.c: Update copyright years.
|
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|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,6 @@
|
|||
/* ia64-opc-i.c -- IA-64 `I' opcode table.
|
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Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc.
|
||||
Copyright 1998, 1999, 2000, 2002, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
|
@ -36,6 +37,7 @@
|
|||
#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20)
|
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#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
|
||||
#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22)
|
||||
#define bXc(x) (((ia64_insn) ((x) & 0x1)) << 19)
|
||||
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
|
||||
#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28)
|
||||
|
|
@ -58,6 +60,7 @@
|
|||
#define mWh bWh (-1)
|
||||
#define mX bX (-1)
|
||||
#define mXb bXb (-1)
|
||||
#define mXc bXc (-1)
|
||||
#define mX2 bX2 (-1)
|
||||
#define mX2a bX2a (-1)
|
||||
#define mX2b bX2b (-1)
|
||||
|
|
@ -83,6 +86,9 @@
|
|||
#define OpX2TaTbYaC(a,b,c,d,e,f) \
|
||||
(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
|
||||
(mOp | mX2 | mTa | mTb | mYa | mC)
|
||||
#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \
|
||||
(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \
|
||||
(mOp | mX2 | mTa | mTb | mYa | mXc | mC)
|
||||
#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
|
||||
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
|
||||
(mOp | mX3 | mX6)
|
||||
|
|
@ -164,6 +170,28 @@ struct ia64_opcode ia64_opcodes_i[] =
|
|||
{"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
|
||||
{"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
|
||||
{"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
|
||||
#define TF(a,b,c) \
|
||||
I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY
|
||||
#define TFCM(a,b,c) \
|
||||
I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL
|
||||
{"tf.z", TF (0, 0, 0)},
|
||||
{"tf.nz", TFCM (0, 0, 0)},
|
||||
{"tf.z.unc", TF (0, 0, 1)},
|
||||
{"tf.nz.unc", TFCM (0, 0, 1)},
|
||||
{"tf.z.and", TF (0, 1, 0)},
|
||||
{"tf.nz.andcm", TFCM (0, 1, 0)},
|
||||
{"tf.nz.and", TF (0, 1, 1)},
|
||||
{"tf.z.andcm", TFCM (0, 1, 1)},
|
||||
{"tf.z.or", TF (1, 0, 0)},
|
||||
{"tf.nz.orcm", TFCM (1, 0, 0)},
|
||||
{"tf.nz.or", TF (1, 0, 1)},
|
||||
{"tf.z.orcm", TFCM (1, 0, 1)},
|
||||
{"tf.z.or.andcm", TF (1, 1, 0)},
|
||||
{"tf.nz.and.orcm", TFCM (1, 1, 0)},
|
||||
{"tf.nz.or.andcm", TF (1, 1, 1)},
|
||||
{"tf.z.and.orcm", TFCM (1, 1, 1)},
|
||||
#undef TF
|
||||
#undef TFCM
|
||||
#define TBIT(a,b,c,d) \
|
||||
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
|
||||
#define TBITCM(a,b,c,d) \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
/* ia64-opc.h -- IA-64 opcode table.
|
||||
Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
|
||||
Copyright 1998, 1999, 2000, 2002, 2005, 2006
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
|
@ -112,6 +113,7 @@
|
|||
#define IMMU24 IA64_OPND_IMMU24
|
||||
#define IMMU62 IA64_OPND_IMMU62
|
||||
#define IMMU64 IA64_OPND_IMMU64
|
||||
#define IMMU5b IA64_OPND_IMMU5b
|
||||
#define IMMU7a IA64_OPND_IMMU7a
|
||||
#define IMMU7b IA64_OPND_IMMU7b
|
||||
#define IMMU9 IA64_OPND_IMMU9
|
||||
|
|
|
|||
Loading…
Reference in New Issue