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X86: Allow additional ISAs for IAMCU in assembler 

Originally only Pentium integer instructions are allowed for IAMCU.
This patch removes such a restriction.  For example, 387 and SSE2
instructions can be enabled by passing "-march=iamcu+sse2+387" to
assembler.

gas/

	* config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
	(set_cpu_arch): Updated.
	(md_parse_option): Likewise.
	* testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5.  Remove
	iamcu-inval-2 and iamcu-inval-3.
	* testsuite/gas/i386/iamcu-4.d: New file.
	* testsuite/gas/i386/iamcu-4.s: Likewise.
	* testsuite/gas/i386/iamcu-5.d: Likewise.
	* testsuite/gas/i386/iamcu-5.s: Likewise.
	* testsuite/gas/i386/iamcu-inval-2.l: Removed.
	* testsuite/gas/i386/iamcu-inval-2.s: Likewise.
	* testsuite/gas/i386/iamcu-inval-3.l: Likewise.
	* testsuite/gas/i386/iamcu-inval-3.s: Likewise.

opcodes/

	* i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
	* i386-init.h: Regenerated.
This commit is contained in:
H.J. Lu 2016-09-07 09:16:25 -07:00
parent 27e5a27096
commit 5b64d091e9
14 changed files with 55 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
gas/ChangeLog
View File

@ -1,3 +1,19 @@
2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (valid_iamcu_cpu_flags): Removed.
(set_cpu_arch): Updated.
(md_parse_option): Likewise.
* testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove
iamcu-inval-2 and iamcu-inval-3.
* testsuite/gas/i386/iamcu-4.d: New file.
* testsuite/gas/i386/iamcu-4.s: Likewise.
* testsuite/gas/i386/iamcu-5.d: Likewise.
* testsuite/gas/i386/iamcu-5.s: Likewise.
* testsuite/gas/i386/iamcu-inval-2.l: Removed.
* testsuite/gas/i386/iamcu-inval-2.s: Likewise.
* testsuite/gas/i386/iamcu-inval-3.l: Likewise.
* testsuite/gas/i386/iamcu-inval-3.s: Likewise.
2016-09-07 Richard Earnshaw <rearnsha@arm.com>
* config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all

23
gas/config/tc-i386.c
View File

@ -1520,20 +1520,6 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
return x;
}
static int
valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
{
if (cpu_arch_isa == PROCESSOR_IAMCU)
{
static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
i386_cpu_flags compat_flags;
compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
return cpu_flags_all_zero (&compat_flags);
}
else
return 1;
}
#define CPU_FLAGS_ARCH_MATCH 0x1
#define CPU_FLAGS_64BIT_MATCH 0x2
#define CPU_FLAGS_AES_MATCH 0x4
@ -2424,10 +2410,7 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
flags = cpu_flags_or (cpu_arch_flags,
cpu_arch[j].flags);
if (!valid_iamcu_cpu_flags (&flags))
as_fatal (_("`%s' isn't valid for Intel MCU"),
cpu_arch[j].name);
else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
if (!cpu_flags_equal (&flags, &cpu_arch_flags))
{
if (cpu_sub_arch_name)
{
@ -10021,9 +10004,7 @@ md_parse_option (int c, const char *arg)
flags = cpu_flags_or (cpu_arch_flags,
cpu_arch[j].flags);
if (!valid_iamcu_cpu_flags (&flags))
as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
if (!cpu_flags_equal (&flags, &cpu_arch_flags))
{
if (cpu_sub_arch_name)
{

4
gas/testsuite/gas/i386/i386.exp
View File

@ -441,9 +441,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "iamcu-1"
run_dump_test "iamcu-2"
run_dump_test "iamcu-3"
run_dump_test "iamcu-4"
run_dump_test "iamcu-5"
run_list_test "iamcu-inval-1" "-march=iamcu -al"
run_list_test "iamcu-inval-2" "-march=iamcu -al"
run_list_test "iamcu-inval-3" "-march=iamcu+sse4 -al"
}
}

12
gas/testsuite/gas/i386/iamcu-4.d Normal file
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@ -0,0 +1,12 @@
#as: -J -march=iamcu+sse2+387
#objdump: -dw
#not-target: *-*-nacl*
.*: +file format elf32-iamcu.*
Disassembly of section .text:
0+ <.text>:
+[a-f0-9]+: d9 ff fcos
+[a-f0-9]+: 66 0f 58 01 addpd \(%ecx\),%xmm0
#pass

3
gas/testsuite/gas/i386/iamcu-4.s Normal file
View File

@ -0,0 +1,3 @@
.text
fcos
addpd (%ecx),%xmm0

12
gas/testsuite/gas/i386/iamcu-5.d Normal file
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@ -0,0 +1,12 @@
#as: -J -march=iamcu -I${srcdir}/$subdir
#objdump: -dw
#not-target: *-*-nacl*
.*: +file format elf32-iamcu.*
Disassembly of section .text:
0+ <.text>:
+[a-f0-9]+: d9 ff fcos
+[a-f0-9]+: 66 0f 58 01 addpd \(%ecx\),%xmm0
#pass

3
gas/testsuite/gas/i386/iamcu-5.s Normal file
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@ -0,0 +1,3 @@
.arch .sse2
.arch .387
.include "iamcu-4.s"

2
gas/testsuite/gas/i386/iamcu-inval-2.l
View File

@ -1,2 +0,0 @@
.*: Assembler messages:
.*:2: Fatal error: `.sse4.1' isn't valid for Intel MCU

2
gas/testsuite/gas/i386/iamcu-inval-2.s
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@ -1,2 +0,0 @@
# Invalid .arch for Intel MCU
.arch .sse4.1

2
gas/testsuite/gas/i386/iamcu-inval-3.l
View File

@ -1,2 +0,0 @@
Assembler messages:
Fatal error: `sse4' isn't valid for Intel MCU

1
gas/testsuite/gas/i386/iamcu-inval-3.s
View File

@ -1 +0,0 @@
.include "iamcu-1.s"

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
* i386-init.h: Regenerated.
2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
* opcodes/arc-dis.c (print_insn_arc): Changed.

2
opcodes/i386-gen.c
View File

@ -223,8 +223,6 @@ static initializer cpu_flag_init[] =
"unknown" },
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586" },
{ "CPU_IAMCU_COMPAT_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuNo64|CpuNop" },
{ "CPU_ADX_FLAGS",
"CpuADX" },
{ "CPU_RDSEED_FLAGS",

7
opcodes/i386-init.h
View File

@ -641,13 +641,6 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
#define CPU_IAMCU_COMPAT_FLAGS \
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }
#define CPU_ADX_FLAGS \
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \