Decode properly flags of %ccr register on sparc64.
While at it, decode also properly one-bit flags for %fsr (accrued and
current exception flags were mixed up).
ChangeLog entry:
2017-03-21 Ivo Raisr <ivo.raisr@oracle.com>
PR tdep/20928
* gdb/sparc-tdep.h (gdbarch_tdep) <sparc64_ccr_type>: New field.
* gdb/sparc64-tdep.c (sparc64_ccr_type): New function.
(sparc64_fsr_type): Fix %fsr decoding.
ChangeLog entry for testsuite:
2017-03-21 Ivo Raisr <ivo.raisr@oracle.com>
PR tdep/20928
* gdb.arch/sparc64-regs.exp: New file.
* gdb.arch/sparc64-regs.S: Likewise.
This commit is contained in:
Ivo Raisr
Jose E. Marchesi
parent
2170171889
commit
5badf10a18
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@ -1,3 +1,10 @@
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2017-03-21 Ivo Raisr <ivo.raisr@oracle.com>
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PR tdep/20928
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* gdb/sparc-tdep.h (gdbarch_tdep) <sparc64_ccr_type>: New field.
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* gdb/sparc64-tdep.c (sparc64_ccr_type): New function.
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(sparc64_fsr_type): Fix %fsr decoding.
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2017-03-21 Tim Wiederhake <tim.wiederhake@intel.com>
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* python/py-record-btrace.c (btpy_insn_data): Change return type
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@ -88,6 +88,7 @@ struct gdbarch_tdep
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/* ISA-specific data types. */
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struct type *sparc_psr_type;
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struct type *sparc_fsr_type;
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struct type *sparc64_ccr_type;
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struct type *sparc64_pstate_type;
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struct type *sparc64_fsr_type;
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struct type *sparc64_fprs_type;
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@ -173,6 +173,31 @@ sparc64_pstate_type (struct gdbarch *gdbarch)
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return tdep->sparc64_pstate_type;
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}
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static struct type *
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sparc64_ccr_type (struct gdbarch *gdbarch)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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if (tdep->sparc64_ccr_type == NULL)
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{
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struct type *type;
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type = arch_flags_type (gdbarch, "builtin_type_sparc64_ccr", 8);
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append_flags_type_flag (type, 0, "icc.c");
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append_flags_type_flag (type, 1, "icc.v");
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append_flags_type_flag (type, 2, "icc.z");
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append_flags_type_flag (type, 3, "icc.n");
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append_flags_type_flag (type, 4, "xcc.c");
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append_flags_type_flag (type, 5, "xcc.v");
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append_flags_type_flag (type, 6, "xcc.z");
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append_flags_type_flag (type, 7, "xcc.n");
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tdep->sparc64_ccr_type = type;
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}
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return tdep->sparc64_ccr_type;
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}
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static struct type *
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sparc64_fsr_type (struct gdbarch *gdbarch)
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{
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@ -183,16 +208,16 @@ sparc64_fsr_type (struct gdbarch *gdbarch)
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struct type *type;
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type = arch_flags_type (gdbarch, "builtin_type_sparc64_fsr", 8);
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append_flags_type_flag (type, 0, "NXA");
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append_flags_type_flag (type, 1, "DZA");
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append_flags_type_flag (type, 2, "UFA");
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append_flags_type_flag (type, 3, "OFA");
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append_flags_type_flag (type, 4, "NVA");
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append_flags_type_flag (type, 5, "NXC");
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append_flags_type_flag (type, 6, "DZC");
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append_flags_type_flag (type, 7, "UFC");
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append_flags_type_flag (type, 8, "OFC");
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append_flags_type_flag (type, 9, "NVC");
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append_flags_type_flag (type, 0, "NXC");
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append_flags_type_flag (type, 1, "DZC");
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append_flags_type_flag (type, 2, "UFC");
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append_flags_type_flag (type, 3, "OFC");
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append_flags_type_flag (type, 4, "NVC");
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append_flags_type_flag (type, 5, "NXA");
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append_flags_type_flag (type, 6, "DZA");
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append_flags_type_flag (type, 7, "UFA");
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append_flags_type_flag (type, 8, "OFA");
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append_flags_type_flag (type, 9, "NVA");
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append_flags_type_flag (type, 22, "NS");
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append_flags_type_flag (type, 23, "NXM");
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append_flags_type_flag (type, 24, "DZM");
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@ -319,7 +344,7 @@ sparc64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
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if (regnum == SPARC64_ASI_REGNUM)
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return builtin_type (gdbarch)->builtin_int64;
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if (regnum == SPARC64_CCR_REGNUM)
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return builtin_type (gdbarch)->builtin_int64;
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return sparc64_ccr_type (gdbarch);
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if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D62_REGNUM)
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return builtin_type (gdbarch)->builtin_double;
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if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q60_REGNUM)
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@ -1,3 +1,9 @@
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2017-03-21 Ivo Raisr <ivo.raisr@oracle.com>
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PR tdep/20928
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* gdb.arch/sparc64-regs.exp: New file.
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* gdb.arch/sparc64-regs.S: Likewise.
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2017-03-21 Tim Wiederhake <tim.wiederhake@intel.com>
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* gdb.python/py-record-btrace.exp: Check for buffer on Python 2
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@ -0,0 +1,136 @@
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/* Copyright 2017 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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This file is part of the gdb testsuite.
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KAT for decoding various sparc64 registers. */
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.section ".text"
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.align 4
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.global main
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.type main, #function
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main:
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call test_ccr
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nop
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call test_fsr
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nop
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retl
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nop
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.size main, .-main
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.type test_ccr, #function
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test_ccr:
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.cfi_startproc
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wr %g0, 0x01, %ccr
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wr %g0, 0x02, %ccr
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wr %g0, 0x03, %ccr
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wr %g0, 0x04, %ccr
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wr %g0, 0x05, %ccr
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wr %g0, 0x06, %ccr
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wr %g0, 0x07, %ccr
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wr %g0, 0x08, %ccr
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wr %g0, 0x09, %ccr
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wr %g0, 0x0a, %ccr
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wr %g0, 0x0b, %ccr
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wr %g0, 0x0c, %ccr
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wr %g0, 0x0d, %ccr
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wr %g0, 0x0e, %ccr
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wr %g0, 0x0f, %ccr
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wr %g0, 0x10, %ccr
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wr %g0, 0x20, %ccr
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wr %g0, 0x30, %ccr
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wr %g0, 0x40, %ccr
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wr %g0, 0x50, %ccr
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wr %g0, 0x60, %ccr
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wr %g0, 0x70, %ccr
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wr %g0, 0x80, %ccr
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wr %g0, 0x90, %ccr
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wr %g0, 0xa0, %ccr
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wr %g0, 0xb0, %ccr
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wr %g0, 0xc0, %ccr
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wr %g0, 0xd0, %ccr
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wr %g0, 0xe0, %ccr
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wr %g0, 0xf0, %ccr
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retl
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nop
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.cfi_endproc
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.size test_ccr, .-test_ccr
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.type test_fsr, #function
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test_fsr:
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.cfi_startproc
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wr %g0, 4, %fprs
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setx flags, %l1, %l0
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mov 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1 ! sparc64-regs.exp: after first %fsr
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 14, %l1 ! move to fsr.tem fields
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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stx %l1, [%l0]
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ldx [%l0], %fsr
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sllx %l1, 1, %l1
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retl
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nop
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.cfi_endproc
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.size test_fsr, .-test_fsr
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.section ".data"
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.align 8
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flags: .xword 0x0000000000000000
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.size flags, .-flags
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@ -0,0 +1,118 @@
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# Copyright 2017 Free Software Foundation, Inc.
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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# This file is part of the gdb testsuite.
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# Tests decoding of various sparc64 registers.
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# At the moment, only few registers are tested, but more can be added in future.
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if ![istarget "sparc64*-*-linux*"] then {
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verbose "Skipping sparc64 register tests."
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return 0
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}
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standard_testfile .S
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set additional_flags "-Wa,-g"
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if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} \
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[list debug $additional_flags]] } {
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return -1
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}
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if ![runto_main] then {
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untested "could not run to main"
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return 0
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}
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##########################################
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gdb_test "break $srcfile:test_ccr" "Breakpoint \[0-9\] at .*"
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gdb_test "continue" "Continuing.*"
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gdb_test "si" "wr .*" "single step to the first %ccr test"
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proc test_ccr {exp_value exp_text {exp_insn "wr .*"}} {
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gdb_test "info register ccr" \
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"ccr $exp_value .*$exp_text.*" \
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"check %ccr register value equal to $exp_text"
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gdb_test "si" "$exp_insn" "single step to a next %ccr test after $exp_text"
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}
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test_ccr "0x1" "icc.c"
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test_ccr "0x2" "icc.v"
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test_ccr "0x3" "icc.c icc.v"
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test_ccr "0x4" "icc.z"
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test_ccr "0x5" "icc.c icc.z"
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test_ccr "0x6" "icc.v icc.z"
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test_ccr "0x7" "icc.c icc.v icc.z"
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test_ccr "0x8" "icc.n"
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test_ccr "0x9" "icc.c icc.n"
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test_ccr "0xa" "icc.v icc.n"
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test_ccr "0xb" "icc.c icc.v icc.n"
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test_ccr "0xc" "icc.z icc.n"
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test_ccr "0xd" "icc.c icc.z icc.n"
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test_ccr "0xe" "icc.v icc.z icc.n"
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test_ccr "0xf" "icc.c icc.v icc.z icc.n"
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test_ccr "0x10" "xcc.c"
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test_ccr "0x20" "xcc.v"
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test_ccr "0x30" "xcc.c xcc.v"
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test_ccr "0x40" "xcc.z"
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test_ccr "0x50" "xcc.c xcc.z"
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test_ccr "0x60" "xcc.v xcc.z"
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test_ccr "0x70" "xcc.c xcc.v xcc.z"
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test_ccr "0x80" "xcc.n"
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test_ccr "0x90" "xcc.c xcc.n"
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test_ccr "0xa0" "xcc.v xcc.n"
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test_ccr "0xb0" "xcc.c xcc.v xcc.n"
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test_ccr "0xc0" "xcc.z xcc.n"
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test_ccr "0xd0" "xcc.c xcc.z xcc.n"
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test_ccr "0xe0" "xcc.v xcc.z xcc.n" "retl"
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test_ccr "0xf0" "xcc.c xcc.v xcc.z xcc.n" "nop"
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##########################################
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##########################################
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set lno [gdb_get_line_number "sparc64-regs.exp: after first %fsr" $srcfile]
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gdb_test "break $srcfile:$lno" "Breakpoint \[0-9\] at .*" \
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"forward breakpoint to first %fsr test"
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gdb_test "continue" "Continuing.*"
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proc test_fsr {exp_value exp_text} {
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gdb_test "info register fsr" \
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"fsr $exp_value .*$exp_text.*" \
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"check %fsr register value equal to $exp_text"
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gdb_test "si" "stx .*" "single step to a next %fsr test (I.) after $exp_text"
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gdb_test "si" "ldx .*" "single step to a next %fsr test (II.) after $exp_text"
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gdb_test "si" "sllx .*" "single step to a next %fsr test (III.) after $exp_text"
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}
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test_fsr "0x1" "NXC"
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test_fsr "0x2" "DZC"
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test_fsr "0x4" "UFC"
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test_fsr "0x8" "OFC"
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test_fsr "0x10" "NVC"
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test_fsr "0x20" "NXA"
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test_fsr "0x40" "DZA"
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test_fsr "0x80" "UFA"
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test_fsr "0x100" "OFA"
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test_fsr "0x200" "NVA"
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test_fsr "0x800000" "NXM"
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test_fsr "0x1000000" "DZM"
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test_fsr "0x2000000" "UFM"
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test_fsr "0x4000000" "OFM"
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test_fsr "0x8000000" "NVM"
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##########################################
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Loading…
Reference in New Issue