[PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operands. (parse_operands): Handle new operands. (do_mve_vcmul): New encoding function. (do_vcmla): Change to support MVE variants. (do_vcadd): Change to support MVE variants. (insns): Change existing to support MVE variants and add new. * testsuite/gas/arm/mve-vcadd-bad-1.d: New test. * testsuite/gas/arm/mve-vcadd-bad-1.l: New test. * testsuite/gas/arm/mve-vcadd-bad-1.s: New test. * testsuite/gas/arm/mve-vcadd-bad-2.d: New test. * testsuite/gas/arm/mve-vcadd-bad-2.l: New test. * testsuite/gas/arm/mve-vcadd-bad-2.s: New test. * testsuite/gas/arm/mve-vcmla-bad-1.d: New test. * testsuite/gas/arm/mve-vcmla-bad-1.l: New test. * testsuite/gas/arm/mve-vcmla-bad-1.s: New test. * testsuite/gas/arm/mve-vcmla-bad-2.d: New test. * testsuite/gas/arm/mve-vcmla-bad-2.l: New test. * testsuite/gas/arm/mve-vcmla-bad-2.s: New test. * testsuite/gas/arm/mve-vcmul-bad-1.d: New test. * testsuite/gas/arm/mve-vcmul-bad-1.l: New test. * testsuite/gas/arm/mve-vcmul-bad-1.s: New test. * testsuite/gas/arm/mve-vcmul-bad-2.d: New test. * testsuite/gas/arm/mve-vcmul-bad-2.l: New test. * testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
This commit is contained in:
Andre Vieira
parent
f601a00c4c
commit
5d281bf033
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@ -1,3 +1,30 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): New operands.
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(parse_operands): Handle new operands.
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(do_mve_vcmul): New encoding function.
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(do_vcmla): Change to support MVE variants.
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(do_vcadd): Change to support MVE variants.
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(insns): Change existing to support MVE variants and add new.
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* testsuite/gas/arm/mve-vcadd-bad-1.d: New test.
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* testsuite/gas/arm/mve-vcadd-bad-1.l: New test.
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* testsuite/gas/arm/mve-vcadd-bad-1.s: New test.
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* testsuite/gas/arm/mve-vcadd-bad-2.d: New test.
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* testsuite/gas/arm/mve-vcadd-bad-2.l: New test.
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* testsuite/gas/arm/mve-vcadd-bad-2.s: New test.
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* testsuite/gas/arm/mve-vcmla-bad-1.d: New test.
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* testsuite/gas/arm/mve-vcmla-bad-1.l: New test.
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* testsuite/gas/arm/mve-vcmla-bad-1.s: New test.
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* testsuite/gas/arm/mve-vcmla-bad-2.d: New test.
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* testsuite/gas/arm/mve-vcmla-bad-2.l: New test.
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* testsuite/gas/arm/mve-vcmla-bad-2.s: New test.
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* testsuite/gas/arm/mve-vcmul-bad-1.d: New test.
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* testsuite/gas/arm/mve-vcmul-bad-1.l: New test.
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* testsuite/gas/arm/mve-vcmul-bad-1.s: New test.
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* testsuite/gas/arm/mve-vcmul-bad-2.d: New test.
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* testsuite/gas/arm/mve-vcmul-bad-2.l: New test.
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* testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): New operands.
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@ -6951,6 +6951,7 @@ enum operand_parse_code
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OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
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*/
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OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
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OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
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OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
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OP_VMOV, /* Neon VMOV operands. */
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OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
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@ -7346,6 +7347,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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}
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break;
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case OP_RNDQMQ_RNSC:
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po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
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break;
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try_rndq_rnsc:
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case OP_RNDQ_RNSC:
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{
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po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
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@ -15574,6 +15579,38 @@ do_mve_vcmp (void)
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return;
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}
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static void
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do_mve_vcmul (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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unsigned rot = inst.relocs[0].exp.X_add_number;
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constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
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_("immediate out of range"));
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if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
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|| inst.operands[0].reg == inst.operands[2].reg))
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as_tsktsk (BAD_MVE_SRCDEST);
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inst.instruction |= (et.size == 32) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= (rot > 90) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 7;
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inst.instruction |= HI1 (inst.operands[2].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[2].reg);
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inst.instruction |= (rot == 90 || rot == 270);
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inst.is_neon = 1;
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}
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static void
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do_vfp_nsyn_cmp (void)
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{
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@ -19677,16 +19714,23 @@ neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
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static void
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do_vcmla (void)
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
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_(BAD_FPU));
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
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&& (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
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|| !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
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constraint (inst.relocs[0].exp.X_op != O_constant,
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_("expression too complex"));
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unsigned rot = inst.relocs[0].exp.X_add_number;
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constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
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_("immediate out of range"));
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rot /= 90;
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if (check_simd_pred_availability (1, NEON_CHECK_ARCH8 | NEON_CHECK_CC))
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return;
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if (inst.operands[2].isscalar)
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{
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
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first_error (_("invalid instruction shape"));
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enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
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unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
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N_KEY | N_F16 | N_F32).size;
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@ -19705,9 +19749,19 @@ do_vcmla (void)
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}
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else
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{
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enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
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enum neon_shape rs;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
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rs = neon_select_shape (NS_QQQI, NS_NULL);
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else
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rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
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unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
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N_KEY | N_F16 | N_F32).size;
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if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
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&& (inst.operands[0].reg == inst.operands[1].reg
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|| inst.operands[0].reg == inst.operands[2].reg))
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as_tsktsk (BAD_MVE_SRCDEST);
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neon_three_same (neon_quad (rs), 0, -1);
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inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
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inst.instruction |= 0xfc200800;
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@ -19719,20 +19773,60 @@ do_vcmla (void)
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static void
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do_vcadd (void)
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
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_(BAD_FPU));
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
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&& (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
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|| !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
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constraint (inst.relocs[0].exp.X_op != O_constant,
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_("expression too complex"));
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unsigned rot = inst.relocs[0].exp.X_add_number;
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constraint (rot != 90 && rot != 270, _("immediate out of range"));
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enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
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unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
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N_KEY | N_F16 | N_F32).size;
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neon_three_same (neon_quad (rs), 0, -1);
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inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
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inst.instruction |= 0xfc800800;
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inst.instruction |= (rot == 270) << 24;
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inst.instruction |= (size == 32) << 20;
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enum neon_shape rs;
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struct neon_type_el et;
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if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
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{
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rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
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et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
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}
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else
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{
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rs = neon_select_shape (NS_QQQI, NS_NULL);
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et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
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| N_I16 | N_I32);
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if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
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as_tsktsk (_("Warning: 32-bit element size and same first and third "
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"operand makes instruction UNPREDICTABLE"));
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}
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if (et.type == NT_invtype)
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return;
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if (check_simd_pred_availability (et.type == NT_float, NEON_CHECK_ARCH8
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return;
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if (et.type == NT_float)
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{
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neon_three_same (neon_quad (rs), 0, -1);
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inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
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inst.instruction |= 0xfc800800;
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inst.instruction |= (rot == 270) << 24;
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inst.instruction |= (et.size == 32) << 20;
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}
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else
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
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inst.instruction = 0xfe000f00;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= neon_logbits (et.size) << 20;
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inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= (rot == 270) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 7;
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inst.instruction |= HI1 (inst.operands[2].reg) << 5;
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inst.instruction |= LOW4 (inst.operands[2].reg);
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inst.is_neon = 1;
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}
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}
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/* Dot Product instructions encoding support. */
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@ -22719,8 +22813,6 @@ static const struct asm_opcode insns[] =
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8_3
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NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
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NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla),
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NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_neon_ext_dotprod
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@ -24087,6 +24179,10 @@ static const struct asm_opcode insns[] =
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mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
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mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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#undef ARM_VARIANT
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#define ARM_VARIANT & fpu_vfp_ext_v1
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#undef THUMB_VARIANT
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@ -24141,6 +24237,13 @@ static const struct asm_opcode insns[] =
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mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
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mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
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mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_v8_3
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v6t2_v8m
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MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
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MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
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};
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#undef ARM_VARIANT
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#undef THUMB_VARIANT
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@ -0,0 +1,5 @@
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#name: bad MVE VCADD instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vcadd-bad-1.l
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.*: +file format .*arm.*
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@ -0,0 +1,17 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: selected FPU does not support instruction -- `vcadd.f16 q0,q1,q2,#90'
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[^:]*:11: Error: bad type in SIMD instruction -- `vcadd.64 q0,q1,q2,#90'
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[^:]*:12: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#180'
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[^:]*:13: Error: immediate out of range -- `vcadd.i32 q0,q1,q2,#0'
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[^:]*:14: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
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[^:]*:18: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
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[^:]*:20: Error: syntax error -- `vcaddeq.i16 q0,q1,q2,#90'
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[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcaddt.i16 q0,q1,q2,#90'
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[^:]*:23: Error: instruction missing MVE vector predication code -- `vcadd.i16 q0,q1,q2,#90'
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@ -0,0 +1,23 @@
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.macro cond
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vcadd.i16 q0, q1, q2, #90
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.endr
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.endm
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.syntax unified
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.thumb
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vcadd.f16 q0, q1, q2, #90
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vcadd.64 q0, q1, q2, #90
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vcadd.i32 q0, q1, q2, #180
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vcadd.i32 q0, q1, q2, #0
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vcadd.i32 q0, q1, q0, #90
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cond
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it eq
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vcaddeq.i16 q0, q1, q2, #90
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vcaddeq.i16 q0, q1, q2, #90
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vpst
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vcaddeq.i16 q0, q1, q2, #90
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vcaddt.i16 q0, q1, q2, #90
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vpst
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vcadd.i16 q0, q1, q2, #90
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@ -0,0 +1,5 @@
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#name: bad MVE FP VCADD instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vcadd-bad-2.l
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.*: +file format .*arm.*
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@ -0,0 +1,17 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vcadd.f64 q0,q1,q2,#90'
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[^:]*:11: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#180'
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[^:]*:12: Error: immediate out of range -- `vcadd.f32 q0,q1,q2,#0'
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[^:]*:13: Warning: 32-bit element size and same first and third operand makes instruction UNPREDICTABLE
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
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[^:]*:17: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
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[^:]*:19: Error: syntax error -- `vcaddeq.f16 q0,q1,q2,#90'
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[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vcaddt.f16 q0,q1,q2,#90'
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[^:]*:22: Error: instruction missing MVE vector predication code -- `vcadd.f16 q0,q1,q2,#90'
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@ -0,0 +1,22 @@
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.macro cond
|
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.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vcadd.f32 q0, q1, q2, #90
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vcadd.f64 q0, q1, q2, #90
|
||||
vcadd.f32 q0, q1, q2, #180
|
||||
vcadd.f32 q0, q1, q2, #0
|
||||
vcadd.f32 q0, q1, q0, #90
|
||||
cond
|
||||
it eq
|
||||
vcaddeq.f16 q0, q1, q2, #90
|
||||
vcaddeq.f16 q0, q1, q2, #90
|
||||
vpst
|
||||
vcaddeq.f16 q0, q1, q2, #90
|
||||
vcaddt.f16 q0, q1, q2, #90
|
||||
vpst
|
||||
vcadd.f16 q0, q1, q2, #90
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VCMLA instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vcmla-bad-1.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:3: Error: selected FPU does not support instruction -- `vcmla.f16 q0,q1,q2,#0'
|
||||
[^:]*:4: Error: selected FPU does not support instruction -- `vcmla.f32 q0,q1,q2,#0'
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
.syntax unified
|
||||
.thumb
|
||||
vcmla.f16 q0, q1, q2, #0
|
||||
vcmla.f32 q0, q1, q2, #0
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE FP VCMLA instructions
|
||||
#as: -march=armv8.1-m.main+mve.fp
|
||||
#error_output: mve-vcmla-bad-2.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: immediate out of range -- `vcmla.f16 q0,q1,q2,#20'
|
||||
[^:]*:11: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
|
||||
[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vcmla.f64 q0,q1,q2,#0'
|
||||
[^:]*:14: Error: bad type in SIMD instruction -- `vcmla.i16 q0,q1,q2,#0'
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
|
||||
[^:]*:18: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
|
||||
[^:]*:20: Error: syntax error -- `vcmlaeq.f16 q0,q1,q2,#0'
|
||||
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcmlat.f16 q0,q1,q2,#0'
|
||||
[^:]*:23: Error: instruction missing MVE vector predication code -- `vcmla.f16 q0,q1,q2,#0'
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
.macro cond
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vcmla.f32 q0, q1, q2, #0
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vcmla.f16 q0, q1, q2, #20
|
||||
vcmla.f32 q0, q0, q1, #0
|
||||
vcmla.f32 q0, q1, q0, #0
|
||||
vcmla.f64 q0, q1, q2, #0
|
||||
vcmla.i16 q0, q1, q2, #0
|
||||
cond
|
||||
it eq
|
||||
vcmlaeq.f16 q0, q1, q2, #0
|
||||
vcmlaeq.f16 q0, q1, q2, #0
|
||||
vpst
|
||||
vcmlaeq.f16 q0, q1, q2, #0
|
||||
vcmlat.f16 q0, q1, q2, #0
|
||||
vpst
|
||||
vcmla.f16 q0, q1, q2, #0
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VCMUL instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vcmul-bad-1.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:3: Error: selected processor does not support `vcmul.f16 q0,q1,q2,#0' in Thumb mode
|
||||
[^:]*:4: Error: selected processor does not support `vcmul.f32 q0,q1,q2,#0' in Thumb mode
|
||||
[^:]*:5: Error: selected processor does not support `vcmul.i16 q0,q1,q2,#0' in Thumb mode
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
.syntax unified
|
||||
.thumb
|
||||
vcmul.f16 q0, q1, q2, #0
|
||||
vcmul.f32 q0, q1, q2, #0
|
||||
vcmul.i16 q0, q1, q2, #0
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE FP VCMUL instructions
|
||||
#as: -march=armv8.1-m.main+mve.fp
|
||||
#error_output: mve-vcmul-bad-2.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vcmul.i16 q0,q1,q2,#0'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vcmul.f64 q0,q1,q2,#0'
|
||||
[^:]*:12: Error: immediate out of range -- `vcmul.f32 q0,q1,q2,#20'
|
||||
[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
|
||||
[^:]*:14: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:17: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
|
||||
[^:]*:18: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
|
||||
[^:]*:20: Error: syntax error -- `vcmuleq.f32 q0,q1,q2,#0'
|
||||
[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vcmult.f32 q0,q1,q2,#0'
|
||||
[^:]*:23: Error: instruction missing MVE vector predication code -- `vcmul.f32 q0,q1,q2,#0'
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
.macro cond
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
vcmul.f32 q0, q1, q2, #0
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.thumb
|
||||
vcmul.i16 q0, q1, q2, #0
|
||||
vcmul.f64 q0, q1, q2, #0
|
||||
vcmul.f32 q0, q1, q2, #20
|
||||
vcmul.f32 q0, q1, q0, #0
|
||||
vcmul.f32 q0, q0, q1, #0
|
||||
cond
|
||||
it eq
|
||||
vcmuleq.f32 q0, q1, q2, #0
|
||||
vcmuleq.f32 q0, q1, q2, #0
|
||||
vpst
|
||||
vcmuleq.f32 q0, q1, q2, #0
|
||||
vcmult.f32 q0, q1, q2, #0
|
||||
vpst
|
||||
vcmul.f32 q0, q1, q2, #0
|
||||
Loading…
Reference in New Issue