Fix ARI warnings in aarch64-tdep.c
This patch fixes some ARI warnings: $ bash ./gdb/contrib/ari/gdb_ari.sh -Wall -Werror -Wari gdb/aarch64-tdep.c gdb/aarch64-tdep.c:3009: code: Do not use &&, or || at the end of a line gdb/aarch64-tdep.c:3010: code: Do not use &&, or || at the end of a line gdb/aarch64-tdep.c:3413: code: Do not use &&, or || at the end of a line gdb/aarch64-tdep.c:3460: code: Do not use &&, or || at the end of a line This patch moves && from the end of line to the start of the line. gdb: 2015-05-27 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_record_branch_except_sys): Split lines before operator &&. (aarch64_record_load_store): Likewise.
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@ -1,3 +1,9 @@
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2015-05-27 Yao Qi <yao.qi@linaro.org>
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* aarch64-tdep.c (aarch64_record_branch_except_sys): Split lines
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before operator &&.
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(aarch64_record_load_store): Likewise.
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2015-05-26 Doug Evans <dje@google.com>
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2015-05-26 Doug Evans <dje@google.com>
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PR c++/18141, c++/18417.
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PR c++/18141, c++/18417.
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@ -3006,9 +3006,9 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
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/* Exception generation instructions. */
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/* Exception generation instructions. */
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if (insn_bits24_27 == 0x04)
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if (insn_bits24_27 == 0x04)
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{
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{
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if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) &&
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if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
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!bits (aarch64_insn_r->aarch64_insn, 21, 23) &&
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&& !bits (aarch64_insn_r->aarch64_insn, 21, 23)
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bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
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&& bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
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{
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{
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ULONGEST svc_number;
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ULONGEST svc_number;
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@ -3410,8 +3410,8 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
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}
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}
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}
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}
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/* Load/store register (register offset) instructions. */
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/* Load/store register (register offset) instructions. */
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else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
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else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
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insn_bits10_11 == 0x02 && insn_bit21)
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&& insn_bits10_11 == 0x02 && insn_bit21)
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{
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{
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if (record_debug)
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if (record_debug)
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{
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{
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@ -3457,8 +3457,8 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
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}
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}
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}
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}
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/* Load/store register (immediate and unprivileged) instructions. */
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/* Load/store register (immediate and unprivileged) instructions. */
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else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
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else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
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!insn_bit21)
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&& !insn_bit21)
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{
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{
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if (record_debug)
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if (record_debug)
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{
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{
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