2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Added .xop and .cvt16. (build_vex_prefix): Handle xop08. (md_assemble): Don't special case the constant 3 for insns using MODRM. (build_modrm_byte): Handle vex2sources. (md_show_usage): Add xop and cvt16. * doc/c-i386.texi: Document fma4, xop, and cvt16. gas/testsuite/ * gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode. Run x86-64-xop and x86-64-cvt16 in 64-bit mode. * gas/i386/lwp.d: Update name of the testcase. * gas/i386/x86-64-xop.d: New. * gas/i386/x86-64-xop.s: New. * gas/i386/xop.d: New. * gas/i386/xop.s: New. * gas/i386/cvt16.d: New. * gas/i386/cvt16.s: New. opcodes/ * i386-dis.c (OP_Vex_2src_1): New. (OP_Vex_2src_2): New. (Vex_2src_1): New. (Vex_2src_2): New. (XOP_08): Added. (VEX_LEN_XOP_08_A0): Added. (VEX_LEN_XOP_08_A1): Added. (VEX_LEN_XOP_09_80): Added. (VEX_LEN_XOP_09_81): Added. (xop_table): Added an entry for XOP_08. Handle xop instructions. (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. (get_valid_dis386): Handle XOP_08. (OP_Vex_2src): New. * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS. (cpu_flags): Add CpuXOP and CpuCVT16. (opcode_modifiers): Add XOP08, Vex2Sources. * i386-opc.h (CpuXOP): Added. (CpuCVT16): Added. (i386_cpu_flags): Add cpuxop and cpucvt16. (XOP08): Added. (Vex2Sources): Added. (i386_opcode_modifier): Add xop08, vex2sources. * i386-opc.tbl: Add entries for XOP and CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
This commit is contained in:
Sebastian Pop
parent
bef57ef2c6
commit
5dd85c9970
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@ -1,3 +1,13 @@
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2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
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Quentin Neill <quentin.neill@amd.com>
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* config/tc-i386.c (cpu_arch): Added .xop and .cvt16.
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(build_vex_prefix): Handle xop08.
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(md_assemble): Don't special case the constant 3 for insns using MODRM.
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(build_modrm_byte): Handle vex2sources.
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(md_show_usage): Add xop and cvt16.
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* doc/c-i386.texi: Document fma4, xop, and cvt16.
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2009-11-17 Paul Brook <paul@codesourcery.com>
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Daniel Jacobowitz <dan@codesourcery.com>
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@ -642,6 +642,10 @@ static const arch_entry cpu_arch[] =
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CPU_FMA_FLAGS },
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{ ".fma4", PROCESSOR_UNKNOWN,
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CPU_FMA4_FLAGS },
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{ ".xop", PROCESSOR_UNKNOWN,
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CPU_XOP_FLAGS },
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{ ".cvt16", PROCESSOR_UNKNOWN,
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CPU_CVT16_FLAGS },
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{ ".lwp", PROCESSOR_UNKNOWN,
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CPU_LWP_FLAGS },
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{ ".movbe", PROCESSOR_UNKNOWN,
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@ -2748,6 +2752,11 @@ build_vex_prefix (const insn_template *t)
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m = 0x2;
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else if (i.tm.opcode_modifier.vex0f3a)
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m = 0x3;
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else if (i.tm.opcode_modifier.xop08)
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{
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m = 0x8;
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i.vex.bytes[0] = 0x8f;
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}
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else if (i.tm.opcode_modifier.xop09)
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{
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m = 0x9;
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@ -2997,8 +3006,12 @@ md_assemble (char *line)
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if (i.tm.opcode_modifier.vex)
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build_vex_prefix (t);
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/* Handle conversion of 'int $3' --> special int3 insn. */
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if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
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/* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
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instructions may define INT_OPCODE as well, so avoid this corner
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case for those instructions that use MODRM. */
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if (i.tm.base_opcode == INT_OPCODE
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&& i.op[0].imms->X_add_number == 3
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&& !i.tm.opcode_modifier.modrm)
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{
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i.tm.base_opcode = INT3_OPCODE;
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i.imm_operands = 0;
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@ -4908,11 +4921,12 @@ build_modrm_byte (void)
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{
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const seg_entry *default_seg = 0;
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unsigned int source, dest;
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int vex_3_sources;
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int vex_3_sources, vex_2_sources;
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/* The first operand of instructions with VEX prefix and 3 sources
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must be VEX_Imm4. */
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vex_3_sources = i.tm.opcode_modifier.vex3sources;
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vex_2_sources = i.tm.opcode_modifier.vex2sources;
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if (vex_3_sources)
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{
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unsigned int nds, reg;
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@ -5296,7 +5310,41 @@ build_modrm_byte (void)
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else
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mem = ~0;
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if (i.tm.opcode_modifier.vexlwp)
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if (vex_2_sources)
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{
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if (operand_type_check (i.types[0], imm))
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i.vex.register_specifier = NULL;
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else
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{
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/* VEX.vvvv encodes one of the sources when the first
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operand is not an immediate. */
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if (i.tm.opcode_modifier.vexw0)
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i.vex.register_specifier = i.op[0].regs;
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else
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i.vex.register_specifier = i.op[1].regs;
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}
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/* Destination is a XMM register encoded in the ModRM.reg
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and VEX.R bit. */
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i.rm.reg = i.op[2].regs->reg_num;
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if ((i.op[2].regs->reg_flags & RegRex) != 0)
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i.rex |= REX_R;
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/* ModRM.rm and VEX.B encodes the other source. */
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if (!i.mem_operands)
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{
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i.rm.mode = 3;
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if (i.tm.opcode_modifier.vexw0)
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i.rm.regmem = i.op[1].regs->reg_num;
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else
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i.rm.regmem = i.op[0].regs->reg_num;
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if ((i.op[1].regs->reg_flags & RegRex) != 0)
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i.rex |= REX_B;
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}
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}
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else if (i.tm.opcode_modifier.vexlwp)
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{
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i.vex.register_specifier = i.op[2].regs;
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if (!i.mem_operands)
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@ -8079,7 +8127,7 @@ md_show_usage (stream)
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ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
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vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
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clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
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svme, abm, padlock, fma4, lwp\n"));
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svme, abm, padlock, fma4, xop, cvt16, lwp\n"));
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fprintf (stream, _("\
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-mtune=CPU optimize for CPU, CPU is one of:\n\
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i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
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@ -142,6 +142,9 @@ accept various extension mnemonics. For example,
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@code{ept},
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@code{clflush},
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@code{lwp},
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@code{fma4},
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@code{xop},
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@code{cvt16},
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@code{syscall},
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@code{rdtscp},
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@code{3dnow},
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@ -922,7 +925,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.ept} @tab @samp{.clflush}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cvt16}
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@item @samp{.padlock}
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@end multitable
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@ -1,3 +1,16 @@
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2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
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Quentin Neill <quentin.neill@amd.com>
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* gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode.
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Run x86-64-xop and x86-64-cvt16 in 64-bit mode.
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* gas/i386/lwp.d: Update name of the testcase.
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* gas/i386/x86-64-xop.d: New.
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* gas/i386/x86-64-xop.s: New.
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* gas/i386/xop.d: New.
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* gas/i386/xop.s: New.
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* gas/i386/cvt16.d: New.
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* gas/i386/cvt16.s: New.
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2009-11-17 Paul Brook <paul@codesourcery.com>
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Daniel Jacobowitz <dan@codesourcery.com>
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@ -20,7 +33,7 @@
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* gas/arm/arm7t.d: Likewise.
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* gas/arm/inst.d: Likewise.
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* gas/arm/xscale.d: Likewise.
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2009-11-17 Nick Clifton <nickc@redhat.com>
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* gas/rx/macros.inc (creg): Remove cpen.
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@ -0,0 +1,73 @@
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#objdump: -dw
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#name: i386 CVT16
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 8f e8 78 a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm7,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 3b 00[ ]+vcvtph2ps \$0x0,\(%ebx\),%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 e8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 c5 ff[ ]+vcvtph2ps \$0xff,%xmm5,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 ed 00[ ]+vcvtph2ps \$0x0,%xmm5,%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 00 03[ ]+vcvtph2ps \$0x3,\(%eax\),%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 03 ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 38 00[ ]+vcvtph2ps \$0x0,\(%eax\),%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm7,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a0 ed ff[ ]+vcvtph2ps \$0xff,%xmm5,%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 2b ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%xmm5
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[ ]*[a-f0-9]+: 8f e8 78 a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a0 38 03[ ]+vcvtph2ps \$0x3,\(%eax\),%xmm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm7,%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 3b 00[ ]+vcvtph2ps \$0x0,\(%ebx\),%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 e8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 c5 ff[ ]+vcvtph2ps \$0xff,%xmm5,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm7,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 ed 00[ ]+vcvtph2ps \$0x0,%xmm5,%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 00 03[ ]+vcvtph2ps \$0x3,\(%eax\),%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 03 ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 38 00[ ]+vcvtph2ps \$0x0,\(%eax\),%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm7,%ymm7
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[ ]*[a-f0-9]+: 8f e8 7c a0 ed ff[ ]+vcvtph2ps \$0xff,%xmm5,%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 2b ff[ ]+vcvtph2ps \$0xff,\(%ebx\),%ymm5
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[ ]*[a-f0-9]+: 8f e8 7c a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm7,%ymm0
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[ ]*[a-f0-9]+: 8f e8 7c a0 38 03[ ]+vcvtph2ps \$0x3,\(%eax\),%ymm7
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[ ]*[a-f0-9]+: 8f e8 78 a1 2b 00[ ]+vcvtps2ph \$0x0,%xmm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 3e 00[ ]+vcvtps2ph \$0x0,%xmm7,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 00 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 ea ff[ ]+vcvtps2ph \$0xff,%xmm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 78 a1 c2 03[ ]+vcvtps2ph \$0x3,%xmm0,%xmm2
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[ ]*[a-f0-9]+: 8f e8 78 a1 ea 03[ ]+vcvtps2ph \$0x3,%xmm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 78 a1 c7 00[ ]+vcvtps2ph \$0x0,%xmm0,%xmm7
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[ ]*[a-f0-9]+: 8f e8 78 a1 06 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 f8 ff[ ]+vcvtps2ph \$0xff,%xmm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 78 a1 3b 00[ ]+vcvtps2ph \$0x0,%xmm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 2b ff[ ]+vcvtps2ph \$0xff,%xmm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 00 ff[ ]+vcvtps2ph \$0xff,%xmm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 38 ff[ ]+vcvtps2ph \$0xff,%xmm7,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 3b 03[ ]+vcvtps2ph \$0x3,%xmm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 28 03[ ]+vcvtps2ph \$0x3,%xmm5,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 78 a1 ef ff[ ]+vcvtps2ph \$0xff,%xmm5,%xmm7
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[ ]*[a-f0-9]+: 8f e8 7c a1 2b 00[ ]+vcvtps2ph \$0x0,%ymm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 3e 00[ ]+vcvtps2ph \$0x0,%ymm7,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 00 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 ea ff[ ]+vcvtps2ph \$0xff,%ymm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 7c a1 c2 03[ ]+vcvtps2ph \$0x3,%ymm0,%xmm2
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[ ]*[a-f0-9]+: 8f e8 7c a1 ea 03[ ]+vcvtps2ph \$0x3,%ymm5,%xmm2
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[ ]*[a-f0-9]+: 8f e8 7c a1 c7 00[ ]+vcvtps2ph \$0x0,%ymm0,%xmm7
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[ ]*[a-f0-9]+: 8f e8 7c a1 06 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%esi\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 f8 ff[ ]+vcvtps2ph \$0xff,%ymm7,%xmm0
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[ ]*[a-f0-9]+: 8f e8 7c a1 3b 00[ ]+vcvtps2ph \$0x0,%ymm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 2b ff[ ]+vcvtps2ph \$0xff,%ymm5,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 00 ff[ ]+vcvtps2ph \$0xff,%ymm0,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 38 ff[ ]+vcvtps2ph \$0xff,%ymm7,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 3b 03[ ]+vcvtps2ph \$0x3,%ymm7,\(%ebx\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 28 03[ ]+vcvtps2ph \$0x3,%ymm5,\(%eax\)
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[ ]*[a-f0-9]+: 8f e8 7c a1 ef ff[ ]+vcvtps2ph \$0xff,%ymm5,%xmm7
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#pass
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@ -0,0 +1,74 @@
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# Check CVT16 instructions (maxcombos=16, maxops=3, archbits=32, seed=1)
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.allow_index_reg
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.text
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_start:
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# Tests for op VCVTPH2PS imm8, xmm2/mem64, xmm1 (at&t syntax)
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VCVTPH2PS $0x0,%xmm7,%xmm7
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VCVTPH2PS $0x0,(%ebx),%xmm7
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VCVTPH2PS $0x0,%xmm0,%xmm5
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VCVTPH2PS $0xFF,%xmm5,%xmm0
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VCVTPH2PS $0x3,%xmm0,%xmm0
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VCVTPH2PS $0x3,%xmm7,%xmm0
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VCVTPH2PS $0x0,%xmm5,%xmm5
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VCVTPH2PS $0x0,%xmm0,%xmm7
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VCVTPH2PS $0x3,(%eax),%xmm0
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VCVTPH2PS $0xFF,(%ebx),%xmm0
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VCVTPH2PS $0x0,(%eax),%xmm7
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VCVTPH2PS $0xFF,%xmm7,%xmm7
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VCVTPH2PS $0xFF,%xmm5,%xmm5
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VCVTPH2PS $0xFF,(%ebx),%xmm5
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VCVTPH2PS $0xFF,%xmm7,%xmm0
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VCVTPH2PS $0x3,(%eax),%xmm7
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# Tests for op VCVTPH2PS imm8, xmm2/mem128, ymm1 (at&t syntax)
|
||||
VCVTPH2PS $0x0,%xmm7,%ymm7
|
||||
VCVTPH2PS $0x0,(%ebx),%ymm7
|
||||
VCVTPH2PS $0x0,%xmm0,%ymm5
|
||||
VCVTPH2PS $0xFF,%xmm5,%ymm0
|
||||
VCVTPH2PS $0x3,%xmm0,%ymm0
|
||||
VCVTPH2PS $0x3,%xmm7,%ymm0
|
||||
VCVTPH2PS $0x0,%xmm5,%ymm5
|
||||
VCVTPH2PS $0x0,%xmm0,%ymm7
|
||||
VCVTPH2PS $0x3,(%eax),%ymm0
|
||||
VCVTPH2PS $0xFF,(%ebx),%ymm0
|
||||
VCVTPH2PS $0x0,(%eax),%ymm7
|
||||
VCVTPH2PS $0xFF,%xmm7,%ymm7
|
||||
VCVTPH2PS $0xFF,%xmm5,%ymm5
|
||||
VCVTPH2PS $0xFF,(%ebx),%ymm5
|
||||
VCVTPH2PS $0xFF,%xmm7,%ymm0
|
||||
VCVTPH2PS $0x3,(%eax),%ymm7
|
||||
# Tests for op VCVTPS2PH imm8, xmm2, xmm1/mem64 (at&t syntax)
|
||||
VCVTPS2PH $0x0,%xmm5,(%ebx)
|
||||
VCVTPS2PH $0x0,%xmm7,(%esi)
|
||||
VCVTPS2PH $0x0,%xmm0,(%eax)
|
||||
VCVTPS2PH $0xFF,%xmm5,%xmm2
|
||||
VCVTPS2PH $0x3,%xmm0,%xmm2
|
||||
VCVTPS2PH $0x3,%xmm5,%xmm2
|
||||
VCVTPS2PH $0x0,%xmm0,%xmm7
|
||||
VCVTPS2PH $0x0,%xmm0,(%esi)
|
||||
VCVTPS2PH $0xFF,%xmm7,%xmm0
|
||||
VCVTPS2PH $0x0,%xmm7,(%ebx)
|
||||
VCVTPS2PH $0xFF,%xmm5,(%ebx)
|
||||
VCVTPS2PH $0xFF,%xmm0,(%eax)
|
||||
VCVTPS2PH $0xFF,%xmm7,(%eax)
|
||||
VCVTPS2PH $0x3,%xmm7,(%ebx)
|
||||
VCVTPS2PH $0x3,%xmm5,(%eax)
|
||||
VCVTPS2PH $0xFF,%xmm5,%xmm7
|
||||
# Tests for op VCVTPS2PH imm8, ymm2, xmm1/mem128 (at&t syntax)
|
||||
VCVTPS2PH $0x0,%ymm5,(%ebx)
|
||||
VCVTPS2PH $0x0,%ymm7,(%esi)
|
||||
VCVTPS2PH $0x0,%ymm0,(%eax)
|
||||
VCVTPS2PH $0xFF,%ymm5,%xmm2
|
||||
VCVTPS2PH $0x3,%ymm0,%xmm2
|
||||
VCVTPS2PH $0x3,%ymm5,%xmm2
|
||||
VCVTPS2PH $0x0,%ymm0,%xmm7
|
||||
VCVTPS2PH $0x0,%ymm0,(%esi)
|
||||
VCVTPS2PH $0xFF,%ymm7,%xmm0
|
||||
VCVTPS2PH $0x0,%ymm7,(%ebx)
|
||||
VCVTPS2PH $0xFF,%ymm5,(%ebx)
|
||||
VCVTPS2PH $0xFF,%ymm0,(%eax)
|
||||
VCVTPS2PH $0xFF,%ymm7,(%eax)
|
||||
VCVTPS2PH $0x3,%ymm7,(%ebx)
|
||||
VCVTPS2PH $0x3,%ymm5,(%eax)
|
||||
VCVTPS2PH $0xFF,%ymm5,%xmm7
|
||||
|
|
@ -162,6 +162,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "fma-intel"
|
||||
run_dump_test "fma4"
|
||||
run_dump_test "lwp"
|
||||
run_dump_test "xop"
|
||||
run_dump_test "cvt16"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
# so we only run them for ELF and COFF targets.
|
||||
|
|
@ -336,6 +338,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-fma-intel"
|
||||
run_dump_test "x86-64-fma4"
|
||||
run_dump_test "x86-64-lwp"
|
||||
run_dump_test "x86-64-xop"
|
||||
run_dump_test "x86-64-cvt16"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 LWP
|
||||
#name: i386 LWP
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 CVT16
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm15,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 3e 00[ ]+vcvtph2ps \$0x0,\(%rsi\),%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 d8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm11
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm15,%xmm0
|
||||
[ ]*[a-f0-9]+: 8f e8 78 a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%xmm0
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm15,%xmm0
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a0 db 00[ ]+vcvtph2ps \$0x0,%xmm11,%xmm11
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f e8 78 a0 01 03[ ]+vcvtph2ps \$0x3,\(%rcx\),%xmm0
|
||||
[ ]*[a-f0-9]+: 8f e8 78 a0 06 ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%xmm0
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 3f 00[ ]+vcvtph2ps \$0x0,\(%rdi\),%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm15,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a0 db ff[ ]+vcvtph2ps \$0xff,%xmm11,%xmm11
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 1e ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%xmm11
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a0 3f 03[ ]+vcvtph2ps \$0x3,\(%rdi\),%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a0 df 03[ ]+vcvtph2ps \$0x3,%xmm15,%xmm11
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 ff 00[ ]+vcvtph2ps \$0x0,%xmm15,%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 3e 00[ ]+vcvtph2ps \$0x0,\(%rsi\),%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 d8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a0 c7 ff[ ]+vcvtph2ps \$0xff,%xmm15,%ymm0
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a0 c0 03[ ]+vcvtph2ps \$0x3,%xmm0,%ymm0
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a0 c7 03[ ]+vcvtph2ps \$0x3,%xmm15,%ymm0
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 db 00[ ]+vcvtph2ps \$0x0,%xmm11,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 f8 00[ ]+vcvtph2ps \$0x0,%xmm0,%ymm15
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a0 01 03[ ]+vcvtph2ps \$0x3,\(%rcx\),%ymm0
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a0 06 ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%ymm0
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 3f 00[ ]+vcvtph2ps \$0x0,\(%rdi\),%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 ff ff[ ]+vcvtph2ps \$0xff,%xmm15,%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 db ff[ ]+vcvtph2ps \$0xff,%xmm11,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 1e ff[ ]+vcvtph2ps \$0xff,\(%rsi\),%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a0 3f 03[ ]+vcvtph2ps \$0x3,\(%rdi\),%ymm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a0 df 03[ ]+vcvtph2ps \$0x3,%xmm15,%ymm11
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 18 00[ ]+vcvtps2ph \$0x0,%xmm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 3f 00[ ]+vcvtps2ph \$0x0,%xmm15,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a1 04 24 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 df ff[ ]+vcvtps2ph \$0xff,%xmm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a1 c7 03[ ]+vcvtps2ph \$0x3,%xmm0,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 df 03[ ]+vcvtps2ph \$0x3,%xmm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f e8 78 a1 c4 00[ ]+vcvtps2ph \$0x0,%xmm0,%xmm4
|
||||
[ ]*[a-f0-9]+: 8f e8 78 a1 07 00[ ]+vcvtps2ph \$0x0,%xmm0,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 f8 ff[ ]+vcvtps2ph \$0xff,%xmm15,%xmm0
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 38 00[ ]+vcvtps2ph \$0x0,%xmm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 18 ff[ ]+vcvtps2ph \$0xff,%xmm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f c8 78 a1 04 24 ff[ ]+vcvtps2ph \$0xff,%xmm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 3c 24 ff[ ]+vcvtps2ph \$0xff,%xmm15,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 38 03[ ]+vcvtps2ph \$0x3,%xmm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 48 78 a1 1c 24 03[ ]+vcvtps2ph \$0x3,%xmm11,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 78 a1 dc ff[ ]+vcvtps2ph \$0xff,%xmm11,%xmm4
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 18 00[ ]+vcvtps2ph \$0x0,%ymm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 3f 00[ ]+vcvtps2ph \$0x0,%ymm15,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a1 04 24 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 df ff[ ]+vcvtps2ph \$0xff,%ymm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a1 c7 03[ ]+vcvtps2ph \$0x3,%ymm0,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 df 03[ ]+vcvtps2ph \$0x3,%ymm11,%xmm15
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a1 c4 00[ ]+vcvtps2ph \$0x0,%ymm0,%xmm4
|
||||
[ ]*[a-f0-9]+: 8f e8 7c a1 07 00[ ]+vcvtps2ph \$0x0,%ymm0,\(%rdi\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 f8 ff[ ]+vcvtps2ph \$0xff,%ymm15,%xmm0
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 38 00[ ]+vcvtps2ph \$0x0,%ymm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 18 ff[ ]+vcvtps2ph \$0xff,%ymm11,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f c8 7c a1 04 24 ff[ ]+vcvtps2ph \$0xff,%ymm0,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 3c 24 ff[ ]+vcvtps2ph \$0xff,%ymm15,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 38 03[ ]+vcvtps2ph \$0x3,%ymm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 8f 48 7c a1 1c 24 03[ ]+vcvtps2ph \$0x3,%ymm11,\(%r12\)
|
||||
[ ]*[a-f0-9]+: 8f 68 7c a1 dc ff[ ]+vcvtps2ph \$0xff,%ymm11,%xmm4
|
||||
#pass
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
# Check CVT16 instructions (maxcombos=16, maxops=3, archbits=64, seed=1)
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
# Tests for op VCVTPH2PS imm8, xmm2/mem64, xmm1 (at&t syntax)
|
||||
VCVTPH2PS $0x0,%xmm15,%xmm15
|
||||
VCVTPH2PS $0x0,(%rsi),%xmm15
|
||||
VCVTPH2PS $0x0,%xmm0,%xmm11
|
||||
VCVTPH2PS $0xFF,%xmm15,%xmm0
|
||||
VCVTPH2PS $0x3,%xmm0,%xmm0
|
||||
VCVTPH2PS $0x3,%xmm15,%xmm0
|
||||
VCVTPH2PS $0x0,%xmm11,%xmm11
|
||||
VCVTPH2PS $0x0,%xmm0,%xmm15
|
||||
VCVTPH2PS $0x3,(%rcx),%xmm0
|
||||
VCVTPH2PS $0xFF,(%rsi),%xmm0
|
||||
VCVTPH2PS $0x0,(%rdi),%xmm15
|
||||
VCVTPH2PS $0xFF,%xmm15,%xmm15
|
||||
VCVTPH2PS $0xFF,%xmm11,%xmm11
|
||||
VCVTPH2PS $0xFF,(%rsi),%xmm11
|
||||
VCVTPH2PS $0x3,(%rdi),%xmm15
|
||||
VCVTPH2PS $0x3,%xmm15,%xmm11
|
||||
# Tests for op VCVTPH2PS imm8, xmm2/mem128, ymm1 (at&t syntax)
|
||||
VCVTPH2PS $0x0,%xmm15,%ymm15
|
||||
VCVTPH2PS $0x0,(%rsi),%ymm15
|
||||
VCVTPH2PS $0x0,%xmm0,%ymm11
|
||||
VCVTPH2PS $0xFF,%xmm15,%ymm0
|
||||
VCVTPH2PS $0x3,%xmm0,%ymm0
|
||||
VCVTPH2PS $0x3,%xmm15,%ymm0
|
||||
VCVTPH2PS $0x0,%xmm11,%ymm11
|
||||
VCVTPH2PS $0x0,%xmm0,%ymm15
|
||||
VCVTPH2PS $0x3,(%rcx),%ymm0
|
||||
VCVTPH2PS $0xFF,(%rsi),%ymm0
|
||||
VCVTPH2PS $0x0,(%rdi),%ymm15
|
||||
VCVTPH2PS $0xFF,%xmm15,%ymm15
|
||||
VCVTPH2PS $0xFF,%xmm11,%ymm11
|
||||
VCVTPH2PS $0xFF,(%rsi),%ymm11
|
||||
VCVTPH2PS $0x3,(%rdi),%ymm15
|
||||
VCVTPH2PS $0x3,%xmm15,%ymm11
|
||||
# Tests for op VCVTPS2PH imm8, xmm2, xmm1/mem64 (at&t syntax)
|
||||
VCVTPS2PH $0x0,%xmm11,(%rax)
|
||||
VCVTPS2PH $0x0,%xmm15,(%rdi)
|
||||
VCVTPS2PH $0x0,%xmm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%xmm11,%xmm15
|
||||
VCVTPS2PH $0x3,%xmm0,%xmm15
|
||||
VCVTPS2PH $0x3,%xmm11,%xmm15
|
||||
VCVTPS2PH $0x0,%xmm0,%xmm4
|
||||
VCVTPS2PH $0x0,%xmm0,(%rdi)
|
||||
VCVTPS2PH $0xFF,%xmm15,%xmm0
|
||||
VCVTPS2PH $0x0,%xmm15,(%rax)
|
||||
VCVTPS2PH $0xFF,%xmm11,(%rax)
|
||||
VCVTPS2PH $0xFF,%xmm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%xmm15,(%r12)
|
||||
VCVTPS2PH $0x3,%xmm15,(%rax)
|
||||
VCVTPS2PH $0x3,%xmm11,(%r12)
|
||||
VCVTPS2PH $0xFF,%xmm11,%xmm4
|
||||
# Tests for op VCVTPS2PH imm8, ymm2, xmm1/mem128 (at&t syntax)
|
||||
VCVTPS2PH $0x0,%ymm11,(%rax)
|
||||
VCVTPS2PH $0x0,%ymm15,(%rdi)
|
||||
VCVTPS2PH $0x0,%ymm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%ymm11,%xmm15
|
||||
VCVTPS2PH $0x3,%ymm0,%xmm15
|
||||
VCVTPS2PH $0x3,%ymm11,%xmm15
|
||||
VCVTPS2PH $0x0,%ymm0,%xmm4
|
||||
VCVTPS2PH $0x0,%ymm0,(%rdi)
|
||||
VCVTPS2PH $0xFF,%ymm15,%xmm0
|
||||
VCVTPS2PH $0x0,%ymm15,(%rax)
|
||||
VCVTPS2PH $0xFF,%ymm11,(%rax)
|
||||
VCVTPS2PH $0xFF,%ymm0,(%r12)
|
||||
VCVTPS2PH $0xFF,%ymm15,(%r12)
|
||||
VCVTPS2PH $0x3,%ymm15,(%rax)
|
||||
VCVTPS2PH $0x3,%ymm11,(%r12)
|
||||
VCVTPS2PH $0xFF,%ymm11,%xmm4
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,3 +1,33 @@
|
|||
2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
|
||||
Quentin Neill <quentin.neill@amd.com>
|
||||
|
||||
* i386-dis.c (OP_Vex_2src_1): New.
|
||||
(OP_Vex_2src_2): New.
|
||||
(Vex_2src_1): New.
|
||||
(Vex_2src_2): New.
|
||||
(XOP_08): Added.
|
||||
(VEX_LEN_XOP_08_A0): Added.
|
||||
(VEX_LEN_XOP_08_A1): Added.
|
||||
(VEX_LEN_XOP_09_80): Added.
|
||||
(VEX_LEN_XOP_09_81): Added.
|
||||
(xop_table): Added an entry for XOP_08. Handle xop instructions.
|
||||
(vex_len_table): Added entries for VEX_LEN_XOP_08_A0,
|
||||
VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81.
|
||||
(get_valid_dis386): Handle XOP_08.
|
||||
(OP_Vex_2src): New.
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS.
|
||||
(cpu_flags): Add CpuXOP and CpuCVT16.
|
||||
(opcode_modifiers): Add XOP08, Vex2Sources.
|
||||
* i386-opc.h (CpuXOP): Added.
|
||||
(CpuCVT16): Added.
|
||||
(i386_cpu_flags): Add cpuxop and cpucvt16.
|
||||
(XOP08): Added.
|
||||
(Vex2Sources): Added.
|
||||
(i386_opcode_modifier): Add xop08, vex2sources.
|
||||
* i386-opc.tbl: Add entries for XOP and CVT16 instructions.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Regenerated.
|
||||
|
||||
2009-11-17 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
PR binutils/10924
|
||||
|
|
|
|||
|
|
@ -113,6 +113,8 @@ static void CRC32_Fixup (int, int);
|
|||
static void OP_LWPCB_E (int, int);
|
||||
static void OP_LWP_E (int, int);
|
||||
static void OP_LWP_I (int, int);
|
||||
static void OP_Vex_2src_1 (int, int);
|
||||
static void OP_Vex_2src_2 (int, int);
|
||||
|
||||
static void MOVBE_Fixup (int, int);
|
||||
|
||||
|
|
@ -356,6 +358,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define OPSUF { OP_3DNowSuffix, 0 }
|
||||
#define CMP { CMP_Fixup, 0 }
|
||||
#define XMM0 { XMM_Fixup, 0 }
|
||||
#define Vex_2src_1 { OP_Vex_2src_1, 0 }
|
||||
#define Vex_2src_2 { OP_Vex_2src_2, 0 }
|
||||
|
||||
#define Vex { OP_VEX, vex_mode }
|
||||
#define Vex128 { OP_VEX, vex128_mode }
|
||||
|
|
@ -1073,7 +1077,8 @@ enum
|
|||
|
||||
enum
|
||||
{
|
||||
XOP_09 = 0,
|
||||
XOP_08 = 0,
|
||||
XOP_09,
|
||||
XOP_0A
|
||||
};
|
||||
|
||||
|
|
@ -1287,7 +1292,11 @@ enum
|
|||
VEX_LEN_3A7B_P_2,
|
||||
VEX_LEN_3A7E_P_2,
|
||||
VEX_LEN_3A7F_P_2,
|
||||
VEX_LEN_3ADF_P_2
|
||||
VEX_LEN_3ADF_P_2,
|
||||
VEX_LEN_XOP_08_A0,
|
||||
VEX_LEN_XOP_08_A1,
|
||||
VEX_LEN_XOP_09_80,
|
||||
VEX_LEN_XOP_09_81
|
||||
};
|
||||
|
||||
typedef void (*op_rtn) (int bytemode, int sizeflag);
|
||||
|
|
@ -6381,6 +6390,297 @@ static const struct dis386 three_byte_table[][256] = {
|
|||
};
|
||||
|
||||
static const struct dis386 xop_table[][256] = {
|
||||
/* XOP_08 */
|
||||
{
|
||||
/* 00 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 08 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 10 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 18 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 20 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 28 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 30 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 38 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 40 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 48 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 50 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 58 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 60 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 68 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 70 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 78 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 80 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
/* 88 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
/* 90 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
/* 98 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
/* a0 */
|
||||
{ VEX_LEN_TABLE (VEX_LEN_XOP_08_A0) },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_XOP_08_A1) },
|
||||
{ "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
/* a8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* b0 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
|
||||
{ "(bad)", { XX } },
|
||||
/* b8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* c0 */
|
||||
{ "vprotb", { XM, Vex_2src_1, Ib } },
|
||||
{ "vprotw", { XM, Vex_2src_1, Ib } },
|
||||
{ "vprotd", { XM, Vex_2src_1, Ib } },
|
||||
{ "vprotq", { XM, Vex_2src_1, Ib } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* c8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpcomb", { XM, Vex128, EXx, Ib } },
|
||||
{ "vpcomw", { XM, Vex128, EXx, Ib } },
|
||||
{ "vpcomd", { XM, Vex128, EXx, Ib } },
|
||||
{ "vpcomq", { XM, Vex128, EXx, Ib } },
|
||||
/* d0 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* d8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* e0 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* e8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpcomub", { XM, Vex128, EXx, Ib } },
|
||||
{ "vpcomuw", { XM, Vex128, EXx, Ib } },
|
||||
{ "vpcomud", { XM, Vex128, EXx, Ib } },
|
||||
{ "vpcomuq", { XM, Vex128, EXx, Ib } },
|
||||
/* f0 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* f8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
/* XOP_09 */
|
||||
{
|
||||
/* 00 */
|
||||
|
|
@ -6528,10 +6828,10 @@ static const struct dis386 xop_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 80 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
|
||||
{ "vfrczss", { XM, EXd } },
|
||||
{ "vfrczsd", { XM, EXq } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -6546,19 +6846,19 @@ static const struct dis386 xop_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* 90 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
/* 98 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -6601,45 +6901,45 @@ static const struct dis386 xop_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
/* c0 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "vphaddbw", { XM, EXxmm } },
|
||||
{ "vphaddbd", { XM, EXxmm } },
|
||||
{ "vphaddbq", { XM, EXxmm } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vphaddwd", { XM, EXxmm } },
|
||||
{ "vphaddwq", { XM, EXxmm } },
|
||||
/* c8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vphadddq", { XM, EXxmm } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* d0 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "vphaddubw", { XM, EXxmm } },
|
||||
{ "vphaddubd", { XM, EXxmm } },
|
||||
{ "vphaddubq", { XM, EXxmm } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vphadduwd", { XM, EXxmm } },
|
||||
{ "vphadduwq", { XM, EXxmm } },
|
||||
/* d8 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vphaddudq", { XM, EXxmm } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
/* e0 */
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "vphsubbw", { XM, EXxmm } },
|
||||
{ "vphsubwd", { XM, EXxmm } },
|
||||
{ "vphsubdq", { XM, EXxmm } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
{ "(bad)", { XX } },
|
||||
|
|
@ -9053,6 +9353,26 @@ static const struct dis386 vex_len_table[][2] = {
|
|||
{ "vaeskeygenassist", { XM, EXx, Ib } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
/* VEX_LEN_XOP_08_A0 */
|
||||
{
|
||||
{ "vcvtph2ps", { XM, EXq, Ib } },
|
||||
{ "vcvtph2ps", { XM, EXxmm, Ib } },
|
||||
},
|
||||
/* VEX_LEN_XOP_08_A1 */
|
||||
{
|
||||
{ "vcvtps2ph", { EXq, XM, Ib } },
|
||||
{ "vcvtps2ph", { EXxmm, XM, Ib } },
|
||||
},
|
||||
/* VEX_LEN_XOP_09_80 */
|
||||
{
|
||||
{ "vfrczps", { XM, EXxmm } },
|
||||
{ "vfrczps", { XM, EXymmq } },
|
||||
},
|
||||
/* VEX_LEN_XOP_09_81 */
|
||||
{
|
||||
{ "vfrczpd", { XM, EXxmm } },
|
||||
{ "vfrczpd", { XM, EXymmq } },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dis386 mod_table[][2] = {
|
||||
|
|
@ -10015,6 +10335,9 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
|
|||
{
|
||||
default:
|
||||
BadOp ();
|
||||
case 0x8:
|
||||
vex_table_index = XOP_08;
|
||||
break;
|
||||
case 0x9:
|
||||
vex_table_index = XOP_09;
|
||||
break;
|
||||
|
|
@ -13482,6 +13805,58 @@ OP_EX_VexReg (int bytemode, int sizeflag, int reg)
|
|||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
|
||||
static void
|
||||
OP_Vex_2src (int bytemode, int sizeflag)
|
||||
{
|
||||
if (modrm.mod == 3)
|
||||
{
|
||||
USED_REX (REX_B);
|
||||
sprintf (scratchbuf, "%%xmm%d", rex & REX_B ? modrm.rm + 8 : modrm.rm);
|
||||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (intel_syntax
|
||||
&& (bytemode == v_mode || bytemode == v_swap_mode))
|
||||
{
|
||||
bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
}
|
||||
OP_E (bytemode, sizeflag);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
OP_Vex_2src_1 (int bytemode, int sizeflag)
|
||||
{
|
||||
if (modrm.mod == 3)
|
||||
{
|
||||
/* Skip mod/rm byte. */
|
||||
MODRM_CHECK;
|
||||
codep++;
|
||||
}
|
||||
|
||||
if (vex.w)
|
||||
{
|
||||
sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
|
||||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
else
|
||||
OP_Vex_2src (bytemode, sizeflag);
|
||||
}
|
||||
|
||||
static void
|
||||
OP_Vex_2src_2 (int bytemode, int sizeflag)
|
||||
{
|
||||
if (vex.w)
|
||||
OP_Vex_2src (bytemode, sizeflag);
|
||||
else
|
||||
{
|
||||
sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
|
||||
oappend (scratchbuf + intel_syntax);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
OP_EX_VexW (int bytemode, int sizeflag)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -128,6 +128,10 @@ static initializer cpu_flag_init[] =
|
|||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" },
|
||||
{ "CPU_FMA4_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" },
|
||||
{ "CPU_XOP_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP|CpuCVT16" },
|
||||
{ "CPU_CVT16_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP|CpuCVT16" },
|
||||
{ "CPU_LWP_FLAGS",
|
||||
"CpuLWP" },
|
||||
{ "CPU_MOVBE_FLAGS",
|
||||
|
|
@ -298,6 +302,8 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuPCLMUL),
|
||||
BITFIELD (CpuFMA),
|
||||
BITFIELD (CpuFMA4),
|
||||
BITFIELD (CpuXOP),
|
||||
BITFIELD (CpuCVT16),
|
||||
BITFIELD (CpuLWP),
|
||||
BITFIELD (CpuLM),
|
||||
BITFIELD (CpuMovbe),
|
||||
|
|
@ -359,9 +365,11 @@ static bitfield opcode_modifiers[] =
|
|||
BITFIELD (Vex0F),
|
||||
BITFIELD (Vex0F38),
|
||||
BITFIELD (Vex0F3A),
|
||||
BITFIELD (XOP08),
|
||||
BITFIELD (XOP09),
|
||||
BITFIELD (XOP0A),
|
||||
BITFIELD (Vex3Sources),
|
||||
BITFIELD (Vex2Sources),
|
||||
BITFIELD (VexImmExt),
|
||||
BITFIELD (SSE2AVX),
|
||||
BITFIELD (NoAVX),
|
||||
|
|
|
|||
|
|
@ -22,282 +22,292 @@
|
|||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 1, 1 } }
|
||||
1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CVT16_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0 } }
|
||||
0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 1, 1 } }
|
||||
1, 1, 0, 1, 1 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -102,6 +102,10 @@ enum
|
|||
CpuFMA,
|
||||
/* FMA4 support required */
|
||||
CpuFMA4,
|
||||
/* XOP support required */
|
||||
CpuXOP,
|
||||
/* CVT16 support required */
|
||||
CpuCVT16,
|
||||
/* LWP support required */
|
||||
CpuLWP,
|
||||
/* MOVBE Instuction support required */
|
||||
|
|
@ -170,6 +174,8 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpupclmul:1;
|
||||
unsigned int cpufma:1;
|
||||
unsigned int cpufma4:1;
|
||||
unsigned int cpuxop:1;
|
||||
unsigned int cpucvt16:1;
|
||||
unsigned int cpulwp:1;
|
||||
unsigned int cpumovbe:1;
|
||||
unsigned int cpuept:1;
|
||||
|
|
@ -291,11 +297,15 @@ enum
|
|||
Vex0F38,
|
||||
/* insn has VEX 0x0F3A opcode prefix. */
|
||||
Vex0F3A,
|
||||
/* insn has XOP 0x08 opcode prefix. */
|
||||
XOP08,
|
||||
/* insn has XOP 0x09 opcode prefix. */
|
||||
XOP09,
|
||||
/* insn has XOP 0x0A opcode prefix. */
|
||||
XOP0A,
|
||||
/* insn has VEX prefix with 3 soures. */
|
||||
/* insn has VEX prefix with 2 sources. */
|
||||
Vex2Sources,
|
||||
/* insn has VEX prefix with 3 sources. */
|
||||
Vex3Sources,
|
||||
/* instruction has VEX 8 bit imm */
|
||||
VexImmExt,
|
||||
|
|
@ -364,8 +374,10 @@ typedef struct i386_opcode_modifier
|
|||
unsigned int vex0f:1;
|
||||
unsigned int vex0f38:1;
|
||||
unsigned int vex0f3a:1;
|
||||
unsigned int xop08:1;
|
||||
unsigned int xop09:1;
|
||||
unsigned int xop0a:1;
|
||||
unsigned int vex2sources:1;
|
||||
unsigned int vex3sources:1;
|
||||
unsigned int veximmext:1;
|
||||
unsigned int sse2avx:1;
|
||||
|
|
|
|||
|
|
@ -2548,6 +2548,91 @@ vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sourc
|
|||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM }
|
||||
vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
||||
// CVT16 instructions
|
||||
|
||||
vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vcvtph2ps, 3, 0xa0, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
|
||||
vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex }
|
||||
vcvtps2ph, 3, 0xa1, None, 1, CpuCVT16, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, RegYMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex }
|
||||
|
||||
// XOP instructions
|
||||
|
||||
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
|
||||
vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM }
|
||||
vfrczsd, 2, 0x83, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vfrczss, 2, 0x82, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { RegYMM, Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM }
|
||||
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM, RegXMM }
|
||||
vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM, RegYMM }
|
||||
vpcomb, 4, 0xcc, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomd, 4, 0xce, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomq, 4, 0xcf, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomub, 4, 0xec, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomud, 4, 0xee, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomuq, 4, 0xef, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomuw, 4, 0xed, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpcomw, 4, 0xcd, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vphaddbd, 2, 0xc2, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddbq, 2, 0xc3, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddbw, 2, 0xc1, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphadddq, 2, 0xcb, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddubd, 2, 0xd2, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddubq, 2, 0xd3, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddubw, 2, 0xd1, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddudq, 2, 0xdb, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphadduwd, 2, 0xd6, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphadduwq, 2, 0xd7, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddwd, 2, 0xc6, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphaddwq, 2, 0xc7, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphsubbw, 2, 0xe1, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphsubdq, 2, 0xe3, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vphsubwd, 2, 0xe2, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpmacsdd, 4, 0x9e, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacsdqh, 4, 0x9f, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacsdql, 4, 0x97, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacssdd, 4, 0x8e, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacssdqh, 4, 0x8f, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacssdql, 4, 0x87, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacsswd, 4, 0x86, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacssww, 4, 0x85, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacswd, 4, 0x96, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmacsww, 4, 0x95, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmadcsswd, 4, 0xa6, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmadcswd, 4, 0xb6, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM, RegXMM }
|
||||
vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vprotb, 3, 0xc0, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vprotd, 3, 0xc2, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vprotq, 3, 0xc3, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vprotw, 3, 0xc1, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
// LWP instructions
|
||||
|
||||
llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg16 }
|
||||
|
|
|
|||
10573
opcodes/i386-tbl.h
10573
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue