[PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum it_instruction_type): Rename to... (enum pred_instruction_type): ... this. Include VPT types. (it_insn_type): Rename to ... (pred_insn_type): .. this. (arm_it): Change comment. (enum arm_reg_type): Add new value. (reg_expected_msgs): New entry. (asm_opcode): Add mayBeVecPred member. (BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT, MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS. (arm_vcond_hsh): New table for vector condition codes. (now_it): Rename to ... (now_pred): ... this. (now_it_compatible): Rename to ... (now_pred_compatible): ... this. (in_it_block): Rename to ... (in_pred_block): ... this. (handle_it_state): Rename to ... (handle_pred_state): ... this. And change it to accept VPT blocks. (set_it_insn_type): Rename to ... (set_pred_insn_type): ... this. (set_it_insn_type_nonvoid): Rename to ... (set_pred_insn_type_nonvoid): ... this. (set_it_insn_type_last): Rename to ... (set_pred_insn_type_last): ... this. (record_feature_use): Moved. (mark_feature_used): Likewise. (parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ. (emit_insn): Use renamed functions and variables. (enum operand_parse_code): Add new operands. (parse_operands): Handle new operands. (do_scalar_fp16_v82_encode): Change predication detection. (do_it): Use renamed functions and variables. (do_t_add_sub): Likewise. (do_t_arit3): Likewise. (do_t_arit3c): Likewise. (do_t_blx): Likewise. (do_t_branch): Likewise. (do_t_bkpt_hlt1): Likewise. (do_t_branch23): Likewise. (do_t_bx): Likewise. (do_t_bxj): Likewise. (do_t_cond): Likewise. (do_t_csdb): Likewise. (do_t_cps): Likewise. (do_t_cpsi): Likewise. (do_t_cbz): Likewise. (do_t_it): Likewise. (do_mve_vpt): New function to handle VPT blocks. (encode_thumb2_multi): Use renamed functions and variables. (do_t_ldst): Use renamed functions and variables. (do_t_mov_cmp): Likewise. (do_t_mvn_tst): Likewise. (do_t_mul): Likewise. (do_t_nop): Likewise. (do_t_neg): Likewise. (do_t_rsb): Likewise. (do_t_setend): Likewise. (do_t_shift): Likewise. (do_t_smc): Likewise. (do_t_tb): Likewise. (do_t_udf): Likewise. (do_t_loloop): Likewise. (do_neon_cvt_1): Likewise. (do_vfp_nsyn_cvt_fpv8): Likewise. (do_vsel): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (do_crypto_2op_1): Likewise. (do_crypto_3op_1): Likewise. (do_crc32_1): Likewise. (it_fsm_pre_encode): Likewise. (it_fsm_post_encode): Likewise. (force_automatic_it_block_close): Likewise. (check_it_blocks_finished): Likewise. (check_pred_blocks_finished): Likewise. (arm_cleanup): Likewise. (now_it_add_mask): Rename to ... (now_pred_add_mask): ... this. And use new variables and functions. (NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl. (N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs. (neon_check_type): Generalize error message. (mve_encode_qqr): New MVE generic encoding function. (neon_dyadic_misc): Change to accept MVE variants. (do_neon_dyadic_if_su): Likewise. (do_neon_addsub_if_i): Likewise. (do_neon_dyadic_long): Likewise. (vfp_or_neon_is_neon): Add extra checks. (check_simd_pred_availability): Helper function to check SIMD instruction availability with respect to predication. (enum opcode_tag): New suffix value. (opcode_lookup): Change to handle VPT blocks. (new_automatic_it_block): Rename to ... (close_automatic_it_block): ...this. (TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU, toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF, NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for new field. (mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs. (insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVE variants. Add entries for vscclrm, and vpst. (md_begin): Add arm_vcond_hsh initialization. * config/tc-arm.h (enum it_state): Rename to... (enum pred_state): ...this. (struct current_it): Rename to... (struct current_pred): ...this. (enum pred_type): New enum. (struct arm_segment_info_type): Use current_pred. * testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message. * testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message. * testsuite/gas/arm/dotprod-illegal.l: Update error message. * testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test. * testsuite/gas/arm/mve-vpst-bad.d: New test. * testsuite/gas/arm/mve-vpst-bad.l: New test. * testsuite/gas/arm/mve-vpst-bad.s: New test. * testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.
This commit is contained in:
Andre Vieira
parent
a7ad558c37
commit
5ee9134313
124
gas/ChangeLog
124
gas/ChangeLog
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@ -1,3 +1,127 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum it_instruction_type): Rename to...
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(enum pred_instruction_type): ... this. Include VPT types.
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(it_insn_type): Rename to ...
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(pred_insn_type): .. this.
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(arm_it): Change comment.
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(enum arm_reg_type): Add new value.
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(reg_expected_msgs): New entry.
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(asm_opcode): Add mayBeVecPred member.
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(BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT,
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MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS.
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(arm_vcond_hsh): New table for vector condition codes.
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(now_it): Rename to ...
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(now_pred): ... this.
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(now_it_compatible): Rename to ...
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(now_pred_compatible): ... this.
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(in_it_block): Rename to ...
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(in_pred_block): ... this.
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(handle_it_state): Rename to ...
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(handle_pred_state): ... this. And change it to accept VPT blocks.
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(set_it_insn_type): Rename to ...
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(set_pred_insn_type): ... this.
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(set_it_insn_type_nonvoid): Rename to ...
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(set_pred_insn_type_nonvoid): ... this.
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(set_it_insn_type_last): Rename to ...
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(set_pred_insn_type_last): ... this.
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(record_feature_use): Moved.
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(mark_feature_used): Likewise.
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(parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ.
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(emit_insn): Use renamed functions and variables.
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(enum operand_parse_code): Add new operands.
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(parse_operands): Handle new operands.
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(do_scalar_fp16_v82_encode): Change predication detection.
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(do_it): Use renamed functions and variables.
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(do_t_add_sub): Likewise.
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(do_t_arit3): Likewise.
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(do_t_arit3c): Likewise.
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(do_t_blx): Likewise.
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(do_t_branch): Likewise.
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(do_t_bkpt_hlt1): Likewise.
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(do_t_branch23): Likewise.
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(do_t_bx): Likewise.
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(do_t_bxj): Likewise.
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(do_t_cond): Likewise.
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(do_t_csdb): Likewise.
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(do_t_cps): Likewise.
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(do_t_cpsi): Likewise.
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(do_t_cbz): Likewise.
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(do_t_it): Likewise.
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(do_mve_vpt): New function to handle VPT blocks.
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(encode_thumb2_multi): Use renamed functions and variables.
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(do_t_ldst): Use renamed functions and variables.
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(do_t_mov_cmp): Likewise.
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(do_t_mvn_tst): Likewise.
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(do_t_mul): Likewise.
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(do_t_nop): Likewise.
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(do_t_neg): Likewise.
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(do_t_rsb): Likewise.
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(do_t_setend): Likewise.
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(do_t_shift): Likewise.
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(do_t_smc): Likewise.
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(do_t_tb): Likewise.
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(do_t_udf): Likewise.
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(do_t_loloop): Likewise.
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(do_neon_cvt_1): Likewise.
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(do_vfp_nsyn_cvt_fpv8): Likewise.
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(do_vsel): Likewise.
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(do_vmaxnm): Likewise.
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(do_vrint_1): Likewise.
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(do_crypto_2op_1): Likewise.
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(do_crypto_3op_1): Likewise.
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(do_crc32_1): Likewise.
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(it_fsm_pre_encode): Likewise.
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(it_fsm_post_encode): Likewise.
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(force_automatic_it_block_close): Likewise.
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(check_it_blocks_finished): Likewise.
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(check_pred_blocks_finished): Likewise.
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(arm_cleanup): Likewise.
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(now_it_add_mask): Rename to ...
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(now_pred_add_mask): ... this. And use new variables and functions.
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(NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl.
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(N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs.
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(neon_check_type): Generalize error message.
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(mve_encode_qqr): New MVE generic encoding function.
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(neon_dyadic_misc): Change to accept MVE variants.
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(do_neon_dyadic_if_su): Likewise.
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(do_neon_addsub_if_i): Likewise.
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(do_neon_dyadic_long): Likewise.
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(vfp_or_neon_is_neon): Add extra checks.
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(check_simd_pred_availability): Helper function to check SIMD
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instruction availability with respect to predication.
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(enum opcode_tag): New suffix value.
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(opcode_lookup): Change to handle VPT blocks.
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(new_automatic_it_block): Rename to ...
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(close_automatic_it_block): ...this.
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(TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU,
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toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF,
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NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for new
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field.
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(mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs.
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(insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVE
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variants. Add entries for vscclrm, and vpst.
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(md_begin): Add arm_vcond_hsh initialization.
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* config/tc-arm.h (enum it_state): Rename to...
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(enum pred_state): ...this.
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(struct current_it): Rename to...
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(struct current_pred): ...this.
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(enum pred_type): New enum.
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(struct arm_segment_info_type): Use current_pred.
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* testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message.
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* testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message.
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* testsuite/gas/arm/dotprod-illegal.l: Update error message.
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* testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test.
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* testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test.
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* testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test.
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* testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test.
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* testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test.
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* testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test.
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* testsuite/gas/arm/mve-vpst-bad.d: New test.
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* testsuite/gas/arm/mve-vpst-bad.l: New test.
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* testsuite/gas/arm/mve-vpst-bad.s: New test.
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* testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
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1225
gas/config/tc-arm.c
1225
gas/config/tc-arm.c
File diff suppressed because it is too large
Load Diff
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@ -254,21 +254,25 @@ arm_min (int am_p1, int am_p2)
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/* Registers are generally saved at negative offsets to the CFA. */
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#define DWARF2_CIE_DATA_ALIGNMENT (-4)
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/* State variables for IT block handling. */
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enum it_state
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/* State variables for predication block handling. */
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enum pred_state
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{
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OUTSIDE_IT_BLOCK, MANUAL_IT_BLOCK, AUTOMATIC_IT_BLOCK
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OUTSIDE_PRED_BLOCK, MANUAL_PRED_BLOCK, AUTOMATIC_PRED_BLOCK
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};
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struct current_it
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enum pred_type {
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SCALAR_PRED, VECTOR_PRED
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};
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struct current_pred
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{
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int mask;
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enum it_state state;
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enum pred_state state;
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int cc;
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int block_length;
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char *insn;
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int state_handled;
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int warn_deprecated;
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int insn_cond;
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enum pred_type type;
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};
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#ifdef OBJ_ELF
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@ -303,7 +307,7 @@ struct arm_segment_info_type
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emitted only once per section, to save unnecessary bloat. */
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unsigned int marked_pr_dependency;
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struct current_it current_it;
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struct current_pred current_pred;
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};
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/* We want .cfi_* pseudo-ops for generating unwind info. */
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@ -3,5 +3,5 @@
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[^:]+:4: Error: VFP single precision register expected -- `vjcvt\.s32\.f64 r0,d1'
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[^:]+:5: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f64 s0,s1'
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[^:]+:6: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f32 s0,s1'
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[^:]+:7: Error: bad type in Neon instruction -- `vjcvt\.s32\.f32 s0,d1'
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[^:]+:8: Error: bad type in Neon instruction -- `vjcvt\.f32\.f64 s0,d1'
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[^:]+:7: Error: bad type in SIMD instruction -- `vjcvt\.s32\.f32 s0,d1'
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[^:]+:8: Error: bad type in SIMD instruction -- `vjcvt\.f32\.f64 s0,d1'
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@ -3,15 +3,15 @@
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[^:]+:7: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
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[^:]+:8: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
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[^:]+:9: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
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[^:]+:10: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
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[^:]+:11: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
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[^:]+:10: Error: bad type in SIMD instruction -- `vcadd\.f64 d0,d1,d2,#90'
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[^:]+:11: Error: bad type in SIMD instruction -- `vcadd\.f64 q0,q1,q2,#90'
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[^:]+:13: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
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[^:]+:14: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
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[^:]+:15: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
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[^:]+:16: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
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[^:]+:17: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
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[^:]+:18: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
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[^:]+:19: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
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[^:]+:18: Error: bad type in SIMD instruction -- `vcmla\.f64 d0,d1,d2,#90'
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[^:]+:19: Error: bad type in SIMD instruction -- `vcmla\.f64 q0,q1,q2,#90'
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[^:]+:21: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
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[^:]+:22: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
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[^:]+:23: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
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@ -22,15 +22,15 @@
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[^:]+:32: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
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[^:]+:33: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
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[^:]+:34: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
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[^:]+:35: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
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[^:]+:36: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
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[^:]+:35: Error: bad type in SIMD instruction -- `vcadd\.f64 d0,d1,d2,#90'
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[^:]+:36: Error: bad type in SIMD instruction -- `vcadd\.f64 q0,q1,q2,#90'
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[^:]+:38: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
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[^:]+:39: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
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[^:]+:40: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
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[^:]+:41: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
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[^:]+:42: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
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[^:]+:43: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
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[^:]+:44: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
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[^:]+:43: Error: bad type in SIMD instruction -- `vcmla\.f64 d0,d1,d2,#90'
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[^:]+:44: Error: bad type in SIMD instruction -- `vcmla\.f64 q0,q1,q2,#90'
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[^:]+:46: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
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[^:]+:47: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
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[^:]+:48: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
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@ -1,9 +1,9 @@
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[^:]*: Assembler messages:
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[^:]*:4: Error: bad type in Neon instruction -- `vudot.s8 d0,d2,d5'
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[^:]*:6: Error: bad type in Neon instruction -- `vudot.u16 d0,d2,d5'
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[^:]*:7: Error: bad type in Neon instruction -- `vsdot.s16 d1,d12,d18'
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[^:]*:9: Error: bad type in Neon instruction -- `vudot.u32 d2,d22,d1'
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[^:]*:10: Error: bad type in Neon instruction -- `vsdot.s32 d3,d30,d9'
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[^:]*:4: Error: bad type in SIMD instruction -- `vudot.s8 d0,d2,d5'
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[^:]*:6: Error: bad type in SIMD instruction -- `vudot.u16 d0,d2,d5'
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[^:]*:7: Error: bad type in SIMD instruction -- `vsdot.s16 d1,d12,d18'
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[^:]*:9: Error: bad type in SIMD instruction -- `vudot.u32 d2,d22,d1'
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[^:]*:10: Error: bad type in SIMD instruction -- `vsdot.s32 d3,d30,d9'
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[^:]*:12: Error: scalar out of range for multiply instruction -- `vudot.u8 d31,d2,d16\[0\]'
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[^:]*:13: Error: scalar out of range for multiply instruction -- `vsdot.s8 q13,q14,d22\[1\]'
|
||||
[^:]*:15: Error: scalar out of range for multiply instruction -- `vudot.u8 d1,d8,d15\[2\]'
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
#name: bad MVE VADD, VSUB and VABD instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vaddsubabd-bad-1.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vadd.p8 q0,q1,q2'
|
||||
[^:]*:12: Error: selected FPU does not support instruction -- `vadd.f16 q0,q1,q2'
|
||||
[^:]*:13: Error: selected FPU does not support instruction -- `vadd.f32 q0,q1,q2'
|
||||
[^:]*:14: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,q2'
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,q2'
|
||||
[^:]*:17: Error: selected FPU does not support instruction -- `vsub.f16 q0,q1,q2'
|
||||
[^:]*:18: Error: selected FPU does not support instruction -- `vsub.f32 q0,q1,q2'
|
||||
[^:]*:19: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,q2'
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Error: bad type in SIMD instruction -- `vadd.p8 q0,q1,r2'
|
||||
[^:]*:22: Error: selected FPU does not support instruction -- `vadd.f16 q0,q1,r2'
|
||||
[^:]*:23: Error: selected FPU does not support instruction -- `vadd.f32 q0,q1,r2'
|
||||
[^:]*:24: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,r2'
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:26: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,r2'
|
||||
[^:]*:27: Error: selected FPU does not support instruction -- `vsub.f16 q0,q1,r2'
|
||||
[^:]*:28: Error: selected FPU does not support instruction -- `vsub.f32 q0,q1,r2'
|
||||
[^:]*:29: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,r2'
|
||||
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:31: Error: bad type in SIMD instruction -- `vabd.p8 q0,q1,q2'
|
||||
[^:]*:32: Error: selected FPU does not support instruction -- `vabd.f16 q0,q1,q2'
|
||||
[^:]*:33: Error: selected FPU does not support instruction -- `vabd.f32 q0,q1,q2'
|
||||
[^:]*:34: Error: bad type in SIMD instruction -- `vabd.i64 q0,q1,q2'
|
||||
[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:36: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:37: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:38: Warning: instruction is UNPREDICTABLE with PC operand
|
||||
[^:]*:39: Warning: instruction is UNPREDICTABLE with PC operand
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
.macro cond op, lastreg, size
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\size q0, q1, \lastreg
|
||||
.endr
|
||||
.endm
|
||||
|
||||
.syntax unified
|
||||
.text
|
||||
.thumb
|
||||
vadd.p8 q0, q1, q2
|
||||
vadd.f16 q0, q1, q2
|
||||
vadd.f32 q0, q1, q2
|
||||
vadd.i64 q0, q1, q2
|
||||
cond vadd, q2, .i32
|
||||
vsub.p8 q0, q1, q2
|
||||
vsub.f16 q0, q1, q2
|
||||
vsub.f32 q0, q1, q2
|
||||
vsub.i64 q0, q1, q2
|
||||
cond vsub, q2, .i32
|
||||
vadd.p8 q0, q1, r2
|
||||
vadd.f16 q0, q1, r2
|
||||
vadd.f32 q0, q1, r2
|
||||
vadd.i64 q0, q1, r2
|
||||
cond vadd, r2, .i32
|
||||
vsub.p8 q0, q1, r2
|
||||
vsub.f16 q0, q1, r2
|
||||
vsub.f32 q0, q1, r2
|
||||
vsub.i64 q0, q1, r2
|
||||
cond vsub, r2, .i32
|
||||
vabd.p8 q0, q1, q2
|
||||
vabd.f16 q0, q1, q2
|
||||
vabd.f32 q0, q1, q2
|
||||
vabd.i64 q0, q1, q2
|
||||
cond vabd, q2, .s32
|
||||
vadd.i32 q0, q1, sp
|
||||
vsub.i32 q0, q1, sp
|
||||
vadd.i32 q0, q1, pc
|
||||
vsub.i32 q0, q1, pc
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#name: bad MVE FP VADD, VSUB and VABD instructions
|
||||
#as: -march=armv8.1-m.main+mve.fp
|
||||
#error_output: mve-vaddsubabd-bad-2.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:13: Error: bad type in SIMD instruction -- `vadd.p8 q0,q1,q2'
|
||||
[^:]*:14: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,q2'
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:16: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,q2'
|
||||
[^:]*:17: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,q2'
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:19: Error: bad type in SIMD instruction -- `vadd.p8 q0,q1,r2'
|
||||
[^:]*:20: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,r2'
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:22: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,r2'
|
||||
[^:]*:23: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,r2'
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:25: Error: bad type in SIMD instruction -- `vabd.p8 q0,q1,q2'
|
||||
[^:]*:26: Error: bad type in SIMD instruction -- `vabd.i64 q0,q1,q2'
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:28: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:29: Warning: instruction is UNPREDICTABLE with SP operand
|
||||
[^:]*:30: Warning: instruction is UNPREDICTABLE with PC operand
|
||||
[^:]*:31: Warning: instruction is UNPREDICTABLE with PC operand
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
.macro cond op, lastreg
|
||||
.irp cond, eq, ne, gt, ge, lt, le
|
||||
it \cond
|
||||
\op\().f32 q0, q1, \lastreg
|
||||
.endr
|
||||
.endm
|
||||
|
||||
|
||||
|
||||
.syntax unified
|
||||
.text
|
||||
.thumb
|
||||
vadd.p8 q0, q1, q2
|
||||
vadd.i64 q0, q1, q2
|
||||
cond vadd, q2
|
||||
vsub.p8 q0, q1, q2
|
||||
vsub.i64 q0, q1, q2
|
||||
cond vsub, q2
|
||||
vadd.p8 q0, q1, r2
|
||||
vadd.i64 q0, q1, r2
|
||||
cond vadd, r2
|
||||
vsub.p8 q0, q1, r2
|
||||
vsub.i64 q0, q1, r2
|
||||
cond vsub, r2
|
||||
vabd.p8 q0, q1, q2
|
||||
vabd.i64 q0, q1, q2
|
||||
cond vabd, q2
|
||||
vadd.i32 q0, q1, sp
|
||||
vsub.i32 q0, q1, sp
|
||||
vadd.i32 q0, q1, pc
|
||||
vsub.i32 q0, q1, pc
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#name: bad VPST instructions
|
||||
#as: -march=armv8.1-m.main+mve
|
||||
#error_output: mve-vpst-bad.l
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:6: Error: syntax error -- `vpsteq'
|
||||
[^:]*:9: Error: vector predicated instruction should be in VPT/VPST block -- `vaddt.i32 q0,q1,q2'
|
||||
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:15: Error: syntax error -- `vaddeq.i32 q0,q1,q2'
|
||||
[^:]*:21: Error: instruction missing MVE vector predication code -- `vadd.i32 q0,q1,q2'
|
||||
[^:]*:23: Error: syntax error -- `vaddeq.i32 q0,q1,q2'
|
||||
[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vaddt.i32 q0,q1,q2'
|
||||
[^:]*:33: Error: bad instruction `addt r0,r0,r1'
|
||||
[^:]*:37: Error: instruction not allowed in IT block -- `add r0,r0,r1'
|
||||
[^:]*:40: Error: thumb conditional instruction should be in IT block -- `addeq r0,r0,r1'
|
||||
[^:]*:43: Error: bad instruction `addt r0,r0,r1'
|
||||
[^:]*:47: Warning: instruction is UNPREDICTABLE in a VPT block
|
||||
[^:]*:49: Error: thumb conditional instruction should be in IT block -- `addeq r0,r0,r1'
|
||||
[^:]*:51: Error: bad instruction `addt r0,r0,r1'
|
||||
[^:]*:55: Warning: instruction is UNPREDICTABLE in an IT block
|
||||
[^:]*:62: Error: incorrect condition in VPT/VPST block -- `vaddt.i32 q0,q1,q2'
|
||||
[^:]*:65: Error: syntax error -- `vaddeq.i32 q0,q1,q2'
|
||||
[^:]*:68: Warning: .* finished with an open VPT/VPST block.
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
.syntax unified
|
||||
.text
|
||||
.thumb
|
||||
@ Case 1
|
||||
it eq
|
||||
vpsteq
|
||||
@ Case 2
|
||||
it eq
|
||||
vaddt.i32 q0, q1, q2
|
||||
@ Case 3
|
||||
it eq
|
||||
vadd.i32 q0, q1, q2
|
||||
@ Case 4
|
||||
vpst
|
||||
vaddeq.i32 q0, q1, q2
|
||||
@ Case 5
|
||||
vpst
|
||||
vaddt.i32 q0, q1, q2
|
||||
@ Case 6
|
||||
vpst
|
||||
vadd.i32 q0, q1, q2
|
||||
@ Case 7
|
||||
vaddeq.i32 q0, q1, q2
|
||||
@ Case 8
|
||||
vaddt.i32 q0, q1, q2
|
||||
@ Case 9
|
||||
vadd.i32 q0, q1, q2
|
||||
@ Case 10
|
||||
it eq
|
||||
addeq r0, r0, r1
|
||||
@ Case 11
|
||||
it eq
|
||||
addt r0, r0, r1
|
||||
addeq r0, r0, r1
|
||||
@ Case 12
|
||||
it eq
|
||||
add r0, r0, r1
|
||||
@ Case 13
|
||||
vpst
|
||||
addeq r0, r0, r1
|
||||
@ Case 14
|
||||
vpst
|
||||
addt r0, r0, r1
|
||||
vaddt.i32 q0, q0, q1
|
||||
@ Case 15
|
||||
vpst
|
||||
add r0, r0, r1
|
||||
@ Case 16
|
||||
addeq r0, r0, r1
|
||||
@ Case 17
|
||||
addt r0, r0, r1
|
||||
@ Case 18
|
||||
add r0, r0, r1
|
||||
it le
|
||||
vpstete
|
||||
vaddt.i32 q0, q1, q2
|
||||
vadde.i32 q0, q1, q2
|
||||
vaddt.i32 q0, q1, q2
|
||||
vadde.i32 q0, q1, q2
|
||||
vpste
|
||||
vaddt.i32 q0, q1, q2
|
||||
vaddt.i32 q0, q1, q2
|
||||
vpste
|
||||
vaddt.i32 q0, q1, q2
|
||||
vaddeq.i32 q0, q1, q2
|
||||
vpstet
|
||||
vaddt.i32 q0, q1, q2
|
||||
vadde.i32 q0, q1, q2
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:2: Error: bad type in Neon instruction -- `vld1\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:3: Error: bad type in Neon instruction -- `vld1\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:4: Error: bad type in Neon instruction -- `vld2\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:5: Error: bad type in Neon instruction -- `vld2\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:2: Error: bad type in SIMD instruction -- `vld1\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:3: Error: bad type in SIMD instruction -- `vld1\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:4: Error: bad type in SIMD instruction -- `vld2\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:5: Error: bad type in SIMD instruction -- `vld2\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:6: Error: bad element type for instruction -- `vld2\.64 {d0-d1},\[r0\]'
|
||||
[^:]*:7: Error: bad type in Neon instruction -- `vld3\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:8: Error: bad type in Neon instruction -- `vld3\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:7: Error: bad type in SIMD instruction -- `vld3\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:8: Error: bad type in SIMD instruction -- `vld3\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:9: Error: bad element type for instruction -- `vld3\.64 {d0-d2},\[r0\]'
|
||||
[^:]*:10: Error: bad type in Neon instruction -- `vld4\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:11: Error: bad type in Neon instruction -- `vld4\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:10: Error: bad type in SIMD instruction -- `vld4\.64 {d0\[1\]},\[r0\]'
|
||||
[^:]*:11: Error: bad type in SIMD instruction -- `vld4\.64 {d0\[\]},\[r0\]'
|
||||
[^:]*:12: Error: bad element type for instruction -- `vld4\.64 {d0-d3},\[r0\]'
|
||||
|
|
|
|||
Loading…
Reference in New Issue