* config/tc-m32r.c (assemble_two_insns): Always call fill_insn.
PR 19068
This commit is contained in:
Doug Evans
parent
b11485dae8
commit
5f02ae577f
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@ -1,3 +1,9 @@
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start-sanitize-cygnus
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Fri Feb 5 19:25:50 1999 Doug Evans <devans@canuck.cygnus.com>
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* config/tc-m32r.c (assemble_two_insns): Always call fill_insn.
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end-sanitize-cygnus
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1999-02-05 Nick Clifton <nickc@cygnus.com>
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* config/tc-arm.h: Tidy OBJ_ELF and OBJ_COFF definitions.
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@ -90,7 +90,7 @@ static const char * m32r_cpu_desc;
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shouldn't assume or require it to). */
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static int warn_unmatched_high = 0;
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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/* Non-zero if -m32rx has been specified, in which case support for the
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extended M32RX instruction set should be enabled. */
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static int enable_m32rx = 0;
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@ -105,7 +105,7 @@ static int warn_explicit_parallel_conflicts = 1;
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/* Non-zero if insns can be made parallel. */
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static int optimize;
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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/* stuff for .scomm symbols. */
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static segT sbss_section;
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@ -142,7 +142,7 @@ struct m32r_hi_fixup
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static struct m32r_hi_fixup * m32r_hi_fixup_list;
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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static void
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allow_m32rx (on)
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int on;
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@ -153,18 +153,18 @@ allow_m32rx (on)
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bfd_set_arch_mach (stdoutput, TARGET_ARCH,
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enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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#define M32R_SHORTOPTS ""
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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#undef M32R_SHORTOPTS
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#define M32R_SHORTOPTS "O"
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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const char * md_shortopts = M32R_SHORTOPTS;
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struct option md_longopts[] =
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{
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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#define OPTION_M32RX (OPTION_MD_BASE)
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{"m32rx", no_argument, NULL, OPTION_M32RX},
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#define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
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@ -175,7 +175,7 @@ struct option md_longopts[] =
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{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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#define OPTION_SPECIAL (OPTION_MD_BASE + 3)
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{"hidden", no_argument, NULL, OPTION_SPECIAL},
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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/* Sigh. I guess all warnings must now have both variants. */
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#define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
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@ -203,7 +203,7 @@ md_parse_option (c, arg)
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{
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switch (c)
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{
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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case 'O':
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optimize = 1;
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break;
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@ -232,7 +232,7 @@ md_parse_option (c, arg)
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return 0;
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}
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break;
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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case OPTION_WARN_UNMATCHED:
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warn_unmatched_high = 1;
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@ -263,7 +263,7 @@ md_show_usage (stream)
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{
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fprintf (stream, _(" M32R specific command line options:\n"));
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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fprintf (stream, _("\
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-m32rx support the extended m32rx instruction set\n"));
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fprintf (stream, _("\
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@ -281,7 +281,7 @@ md_show_usage (stream)
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-Wp synonym for -warn-explicit-parallel-conflicts\n"));
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fprintf (stream, _("\
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-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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fprintf (stream, _("\
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-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
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@ -316,11 +316,11 @@ const pseudo_typeS md_pseudo_table[] =
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{ "fillinsn", fill_insn, 0 },
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{ "scomm", m32r_scomm, 0 },
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{ "debugsym", debug_sym, 0 },
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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/* Not documented as so far there is no need for them.... */
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{ "m32r", allow_m32rx, 0 },
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{ "m32rx", allow_m32rx, 1 },
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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{ NULL, NULL, 0 }
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};
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@ -556,12 +556,12 @@ md_begin ()
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scom_symbol.name = ".scommon";
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scom_symbol.section = & scom_section;
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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allow_m32rx (enable_m32rx);
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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}
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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#define OPERAND_IS_COND_BIT(operand, indices, index) \
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(CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
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@ -747,12 +747,13 @@ assemble_two_insns (str, str2, parallel_p)
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* str2 = 0; /* Seperate the two instructions. */
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/* If there was a previous 16 bit insn, then fill the following 16 bit slot,
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so that the parallel instruction will start on a 32 bit boundary.
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/* Make sure the two insns begin on a 32 bit boundary.
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This is also done for the serial case (foo -> bar), relaxing doesn't
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affect insns written like this. */
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if (prev_insn.insn)
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fill_insn (0);
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affect insns written like this.
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Note that we must always do this as we can't assume anything about
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whether we're currently on a 32 bit boundary or not. Relaxing may
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change this. */
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fill_insn (0);
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first.debug_sym_link = debug_sym_link;
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debug_sym_link = (sym_linkS *)0;
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@ -970,7 +971,7 @@ assemble_two_insns (str, str2, parallel_p)
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prev_subseg = now_subseg;
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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void
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@ -984,7 +985,7 @@ md_assemble (str)
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/* Initialize GAS's cgen interface for a new instruction. */
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gas_cgen_init_parse ();
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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/* Look for a parallel instruction seperator. */
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if ((str2 = strstr (str, "||")) != NULL)
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{
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@ -998,7 +999,7 @@ md_assemble (str)
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assemble_two_insns (str, str2, 0);
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return;
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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insn.debug_sym_link = debug_sym_link;
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debug_sym_link = (sym_linkS *)0;
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@ -1012,7 +1013,7 @@ md_assemble (str)
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return;
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}
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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if (! enable_special
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&& CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL))
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{
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@ -1027,7 +1028,7 @@ md_assemble (str)
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as_bad (_("instruction '%s' is for the M32RX only"), str);
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return;
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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if (CGEN_INSN_BITSIZE (insn.insn) == 32)
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{
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@ -1049,15 +1050,15 @@ md_assemble (str)
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else
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{
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int on_32bit_boundary_p;
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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int swap = false;
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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if (CGEN_INSN_BITSIZE (insn.insn) != 16)
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abort();
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insn.orig_insn = insn.insn;
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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/* If the previous insn was relaxable, then it may be expanded
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to fill the current 16 bit slot. Emit a NOP here to occupy
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this slot, so that we can start at optimizing at a 32 bit
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@ -1076,13 +1077,13 @@ md_assemble (str)
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if (insn.insn == NULL)
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as_fatal (_("internal error: lookup/get operands failed"));
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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/* Compute whether we're on a 32 bit boundary or not.
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prev_insn.insn is NULL when we're on a 32 bit boundary. */
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on_32bit_boundary_p = prev_insn.insn == NULL;
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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/* Look to see if this instruction can be combined with the
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previous instruction to make one, parallel, 32 bit instruction.
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If the previous instruction (potentially) changed the flow of
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@ -1106,7 +1107,7 @@ md_assemble (str)
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else if (can_make_parallel (& insn, & prev_insn) == NULL)
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swap = true;
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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expand_debug_syms (insn.debug_sym_link, 1);
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@ -1127,7 +1128,7 @@ md_assemble (str)
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insn.fixups[i] = fi.fixups[i];
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}
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/* start-sanitize-m32rx */
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/* start-sanitize-cygnus */
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if (swap)
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{
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int i,tmp;
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@ -1155,7 +1156,7 @@ md_assemble (str)
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for (i = 0; i < insn.num_fixups; ++i)
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insn.fixups[i]->fx_where -= 2;
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}
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/* end-sanitize-m32rx */
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/* end-sanitize-cygnus */
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/* Keep track of whether we've seen a pair of 16 bit insns.
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prev_insn.insn is NULL when we're on a 32 bit boundary. */
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