* gas/arm/addthumb2err.s: New test file.
* gas/arm/addthumb2err.d: Test control file. * gas/arm/addthumb2err.l: Expected error messages. * config/tc-arm.c (do_t_add_sub): Only allow LSL shifts of less than 4 in Thumb mode.
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@ -1,3 +1,8 @@
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2011-06-30 Paul Carroll <pcarroll@codesourcery.com>
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* config/tc-arm.c (do_t_add_sub): Only allow LSL shifts of less
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than 4 in Thumb mode.
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2011-06-30 Nick Clifton <nickc@redhat.com>
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2011-06-30 Nick Clifton <nickc@redhat.com>
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PR gas/12848
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PR gas/12848
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@ -9474,6 +9474,9 @@ do_t_add_sub (void)
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}
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}
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else
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else
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{
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{
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unsigned int value = inst.reloc.exp.X_add_number;
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unsigned int shift = inst.operands[2].shift_kind;
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Rn = inst.operands[2].reg;
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Rn = inst.operands[2].reg;
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/* See if we can do this with a 16-bit instruction. */
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/* See if we can do this with a 16-bit instruction. */
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if (!inst.operands[2].shifted && inst.size_req != 4)
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if (!inst.operands[2].shifted && inst.size_req != 4)
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@ -9524,6 +9527,10 @@ do_t_add_sub (void)
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inst.instruction = THUMB_OP32 (inst.instruction);
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inst.instruction = THUMB_OP32 (inst.instruction);
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inst.instruction |= Rd << 8;
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inst.instruction |= Rd << 8;
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inst.instruction |= Rs << 16;
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inst.instruction |= Rs << 16;
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constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
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_("shift value over 3 not allowed in thumb mode"));
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constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
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_("only LSL shift allowed in thumb mode"));
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encode_thumb32_shifted_operand (2);
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encode_thumb32_shifted_operand (2);
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}
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}
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}
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}
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@ -1,3 +1,9 @@
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2011-06-30 Paul Carroll <pcarroll@codesourcery.com>
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* gas/arm/addthumb2err.s: New test file.
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* gas/arm/addthumb2err.d: Test control file.
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* gas/arm/addthumb2err.l: Expected error messages.
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2011-06-30 Nick Clifton <nickc@redhat.com>
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2011-06-30 Nick Clifton <nickc@redhat.com>
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PR gas/12931
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PR gas/12931
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#name: bad Thumb2 Add{S} and Sub{S} instructions
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#as: -march=armv7-a
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#error-output: addthumb2err.l
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# Test some Thumb2 instructions:
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.*: +file format .*arm.*
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[^:]*: Assembler messages:
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[^:]*:9: Error: shift value over 3 not allowed in thumb mode -- `add sp,sp,r0,LSL#4'
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[^:]*:10: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,LSR#3'
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[^:]*:11: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ASR#3'
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[^:]*:12: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ROR#3'
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[^:]*:13: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,RRX'
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[^:]*:14: Error: shift value over 3 not allowed in thumb mode -- `adds sp,sp,r0,LSL#4'
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[^:]*:15: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,LSR#3'
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[^:]*:16: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ASR#3'
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[^:]*:17: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ROR#3'
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[^:]*:18: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,RRX'
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[^:]*:19: Error: shift value over 3 not allowed in thumb mode -- `sub sp,sp,r0,LSL#4'
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[^:]*:20: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,LSR#3'
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[^:]*:21: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ASR#3'
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[^:]*:22: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ROR#3'
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[^:]*:23: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,RRX'
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[^:]*:24: Error: shift value over 3 not allowed in thumb mode -- `subs sp,sp,r0,LSL#4'
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[^:]*:25: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,LSR#3'
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[^:]*:26: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ASR#3'
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[^:]*:27: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ROR#3'
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[^:]*:28: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,RRX'
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.syntax unified
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.text
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.align 2
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.thumb
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# Test of invalid operands for ADD{S} and SUB{S} instructions
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# in Thumb2 mode. The instruction form being testing
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# involves having the first 2 operands be SP.
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add sp, sp, r0, LSL #4
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add sp, sp, r0, LSR #3
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add sp, sp, r0, ASR #3
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add sp, sp, r0, ROR #3
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add sp, sp, r0, RRX
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adds sp, sp, r0, LSL #4
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adds sp, sp, r0, LSR #3
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adds sp, sp, r0, ASR #3
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adds sp, sp, r0, ROR #3
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adds sp, sp, r0, RRX
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sub sp, sp, r0, LSL #4
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sub sp, sp, r0, LSR #3
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sub sp, sp, r0, ASR #3
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sub sp, sp, r0, ROR #3
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sub sp, sp, r0, RRX
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subs sp, sp, r0, LSL #4
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subs sp, sp, r0, LSR #3
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subs sp, sp, r0, ASR #3
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subs sp, sp, r0, ROR #3
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subs sp, sp, r0, RRX
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