OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

2003-04-13 Michael Snyder <msnyder@redhat.com>

Browse Source 
* configure.in: Add testsuite to extra_subdirs.
	* configure: Regenerate.

2003-04-13  Michael Snyder  <msnyder@redhat.com>

	* sim/h8300: New directory.  Tests for Hitachi h8/300 family.
This commit is contained in:
Michael Snyder 2003-04-13 16:44:57 +00:00
parent ef6e7e1393
commit 5fe8b0dfe1
55 changed files with 31460 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
sim/configure vendored
View File

@ -1426,7 +1426,10 @@ case "${target}" in
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
# OBSOLETE fr30-*-*) sim_target=fr30 ;;
h8300*-*-*) sim_target=h8300 ;;
h8300*-*-*)
sim_target=h8300
extra_subdirs="${extra_subdirs} testsuite"
;;
h8500-*-*) sim_target=h8500 ;;
i960-*-*) sim_target=i960 ;;
m32r-*-*) sim_target=m32r ;;

5
sim/configure.in
View File

@ -65,7 +65,10 @@ case "${target}" in
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
# OBSOLETE fr30-*-*) sim_target=fr30 ;;
h8300*-*-*) sim_target=h8300 ;;
h8300*-*-*)
sim_target=h8300
extra_subdirs="${extra_subdirs} testsuite"
;;
h8500-*-*) sim_target=h8500 ;;
i960-*-*) sim_target=i960 ;;
m32r-*-*) sim_target=m32r ;;

200
sim/testsuite/sim/h8300/ChangeLog Normal file
View File

@ -0,0 +1,200 @@
2003-04-11 Michael Snyder <msnyder@redhat.com>
* mac.s: New file. Test multiply-accumulator insns.
* allinsn.exp: Add mac tests.
2003-04-10 Michael Snyder <msnyder@redhat.com>
* brabc.s: New file. Test for bra/bc and bra/bs.
* allinsn.exp: Add bra/bc test.
* testsuite.inc: New macro memcmp.
* bfld.s: Un-comment insns, assembler works now.
* bfld.s: Add tests for bfst insn.
* bfld.s: New file. Test for bfld insn.
* allinsn.exp: Add bfld test.
2003-04-09 Michael Snyder <msnyder@redhat.com>
* movmd.s: New file. Test for movmd insn.
* allinsn.exp: Add movmd test.
* movsd.s: Un-comment movsd instructions (assembler works now).
* movsd.s: New file. Test for movsd insn.
* allinsn.exp: Add movsd test.
* add.b.s: Add tests for ABS8 mode.
2003-04-08 Michael Snyder <msnyder@redhat.com>
* bset.s: New file, test bset and bclr.
* allinsn.exp: Add bset test.
* and.b.s: Add test for andc ccr.
* or.b.s: Add test for orc ccr.
* xor.b.s: Add test for xorc ccr.
2003-04-07 Michael Snyder <msnyder@redhat.com>
* testutils.inc (_write_and_exit): Rewrite for new syscall lib.
(pass, fail): Use new syscall abi.
2003-04-04 Michael Snyder <msnyder@redhat.com>
* rotl.s: Add INDEXB, INDEXW, INDEXL tests.
* rotl.s, rotr.s, rotxl.s, rotxr.s: New files.
* allinsn.exp: Add rot insn tests.
2003-04-03 Michael Snyder <msnyder@redhat.com>
* shift.s: Remove. Replace with
* shal.s, shar.s, shll.s, shlr.s: New files.
* allinsn.exp: Invoke new test files.
* ext.w.s, ext.l.s: New files, tests for exts and extu.
2003-04-02 Michael Snyder <msnyder@redhat.com>
* bra.s: New file, test for branch insns.
* allinsn.exp: Add bra.s.
* adds.s: Add ccr flags checking.
2003-04-01 Michael Snyder <msnyder@redhat.com>
* shift.s: Add lots of tests.
* mov.b.s: Add word and long tests.
* neg.s: New file, test neg instructions.
* allinsn.exp: Add neg test.
2003-03-31 Michael Snyder <msnyder@redhat.com>
* addx.s: Add word and long tests.
2003-03-28 Michael Snyder <msnyder@redhat.com>
* mov.w.s: Add a bunch more tests for new addressing modes.
* add.l.s: Comment fixes.
* not.s: Add tests for word and long operations.
* not.s: Fill out remaining tests for byte operation.
* add.l.s: Fix up .if directives for h8h, h8s.
* mov.l.s: Simplify results checking.
* add.l.s: Add several dozen new tests for new addressing modes.
2003-03-25 Michael Snyder <msnyder@redhat.com>
* mov.l.s: A sampling of tests for esoteric addressing modes.
* mov.l.s: Finish tests for immediate and register direct modes.
* mov.l.s: Simplify, add more tests.
* mov.l.s: Add more new tests.
2003-03-13 Michael Snyder <msnyder@redhat.com>
* not.s: New test.
* allinsn.exp: Add not.s test.
* add.b.s, add.w.s, addx.s and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s:
Un-comment assembler instructions: assembler should handle 'em all.
2003-03-04 Michael Snyder <msnyder@redhat.com>
* add.b.s: Add DISP16, DISP32, ABS16, ABS32.
* sub.b.s: Add POSTINC, POSTDEC, RDIND.
* or.b.s, xor.b.s: Add RDPOSTINC, RDPREINC, RDPREDEC.
2003-03-03 Michael Snyder <msnyder@redhat.com>
* add.b.s, addx.s, and.b.s, cmp.b.s: Add RDPOSTINC,
RDPREINC, RDPREDEC.
* add.b.s, addx.s, and.b.s, cmp.b.s, or.b.s, xor.b.s: Add RDPOSTDEC.
2003-02-28 Michael Snyder <msnyder@redhat.com>
* add.b.s, and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s:
Add tests for RDIND. Also add RDPOSTDEC to cmp.b.s.
* allinsn.exp: All tests run for all machine flavors.
2003-02-27 Michael Snyder <msnyder@redhat.com>
* add.l.s, adds.s, addx.s, and.l.s, cmp.l.s, cmp.w.s, jmp.s,
or.l.s, or.w.s, sub.l.s, sub.w.s, xor.l.s, xor.w.s):
Substitute actual assembler instructions for data words!
* addx.s: Add tests for RDIND and RDPOSTDEC.
* shifts.s: New file.
* allinsn.exp: Add shifts.s.
* testutils.inc: Add assembler directive ".h8300sx".
* add.w.s, add.l.s, ...: Add linker directive "-m h8300sxelf".
2003-02-25 Michael Snyder <msnyder@redhat.com>
* adds.s, addw.s: New files.
* testutils.inc (set_ccr, set_carry_flag, test_carry_clear,
test_carry_set, test_ovf_clear, test_ovf_set, test_zero_clear,
test_zero_set, test_neg_clear, test_neg_set): New macros.
2003-02-24 Michael Snyder <msnyder@redhat.com>
* stc.c: Extend tests to all h8300s opcodes.
* ldc.s: New file.
* stc.s: New file.
* allinsn.exp: Add stc test.
* and.l.s: 'and.l imm:16 clears upper half of dest. reg.
* testutils.inc: Add kludge for h8sx.
(set_gr_a5a5, set_grs_a5a5, test_gr_a5a5, test_grs_a5a5,
set_ccr_zero): New macros.
2003-02-18 Michael Snyder <msnyder@redhat.com>
* daa.s: New file.
* das.s: New file.
* dec.s: New file.
* inc.s: New file.
* or.b.s: New file.
* or.w.s: New file.
* or.l.s: New file.
* xor.b.s: New file.
* xor.w.s: New file.
* xor.l.s: New file.
* and.l.s: Fix expected result.
* allinsn.exp: Add new tests.
2003-02-12 Michael Snyder <msnyder@redhat.com>
* and.b.s: New file.
* and.w.s: New file.
* and.l.s: New file.
* cmp.b.s: New file.
* cmp.w.s: New file.
* cmp.l.s: New file.
* jmp.s: New file.
* add.w.s: Add test for 3-bit immediate operand.
* add.l.s: Add test for 3-bit and 16-bit immediate operands.
* mov.b.s (dst_addr16, dst_addr32): Delete.
* nop.s: Simplify using testutils.inc macros.
* sub.w.s: Add test for 3-bit immediate operand.
* sub.l.s: Add test for 3-bit and 16-bit immediate operands.
2003-02-07 Michael Snyder <msnyder@redhat.com>
* mov.b.s: Add tests for more addressing modes.
(src_addr16, src_addr32, dst_addr16, dst_addr32): Delete.
* mov.b.s: Add prospective tests for h8sx modes.
* mov.w.s: New file (test for 'mov.w').
* mov.l.s: New file (test for 'mov.l').
* sub.b.s: New file (test for 'sub.b').
* sub.w.s: New file (test for 'sub.w').
* sub.l.s: New file (test for 'sub.l').
* allinsn.exp: Turn new tests on.
2003-02-06 Michael Snyder <msnyder@redhat.com>
* allinsn.exp: New file.
* testutils.inc: New file.
* nop.s: New file (test for 'nop' insn).
* add.b.s: New file (test for 'add.b').
* add.w.s: New file (test for 'add.w').
* add.l.s: New file (test for 'add.l').
* mov.b.s: New file (test for 'mov.b');
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
change-log-default-name: "ChangeLog"
End:

778
sim/testsuite/sim/h8300/add.b.s Normal file
View File

@ -0,0 +1,778 @@
# Hitachi H8 testcase 'add.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.b #xx:8, rd ; 8 rd xxxxxxxx
# add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx
# add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx
# add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx
# add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx
# add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx
# add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx
# add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx
# add.b rs, rd ; 0 8 rs rd
# add.b reg8, @erd ; 7 d rd ???? 0 8 rs ????
# add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs
# add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs
# add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs
# add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs
# add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16
# add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32
# add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ????
# add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ????
# add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ????
#
# Coming soon:
# add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx
# add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0
post_byte: .byte 0
start
add_b_imm8_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.b #xx:8,Rd
add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
add_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@eRd
mov #byte_dest, er0
add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #5, r0l
beq .L1
fail
.L1:
add_b_imm8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@eRd+
mov #byte_dest, er0
add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #10, r0l
beq .L2
fail
.L2:
add_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@eRd-
mov #byte_dest, er0
add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #15, r0l
beq .L3
fail
.L3:
add_b_imm8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@+eRd
mov #pre_byte, er0
add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #20, r0l
beq .L4
fail
.L4:
add_b_imm8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@-eRd
mov #post_byte, er0
add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #25, r0l
beq .L5
fail
.L5:
add_b_imm8_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@(dd:16, eRd)
mov #post_byte, er0
add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest.
;;; .word 0x0174
;;; .word 0x6e08
;;; .word 0xffff
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #30, r0l
beq .L6
fail
.L6:
add_b_imm8_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@(dd:32, eRd)
mov #pre_byte, er0
add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest.
;;; .word 0x7804
;;; .word 0x6a28
;;; .word 0x0000
;;; .word 0x0001
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #35, r0l
beq .L7
fail
.L7:
add_b_imm8_abs8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:8
;; NOTE: for abs8, we will use the SBR register as a base,
;; since otherwise we would have to make sure that the destination
;; was in the zero page.
;;
mov #byte_dest-100, er0
ldc er0, sbr
add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest
;;; .word 0x7f64
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #40, r0l
beq .L8
fail
.L8:
add_b_imm8_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@aa:16
add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #45, r0l
beq .L9
fail
.L9:
add_b_imm8_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b #xx:8,@aa:32
add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x8005
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #50, r0l
beq .L10
fail
.L10:
.endif
add_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.b Rs,Rd
mov.b #5, r0h
add.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x05aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
add_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@eRd ; Add to register indirect
mov #byte_dest, er0
mov #5, r1l
add.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x0890
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #55, r0l
beq .L11
fail
.L11:
add_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@eRd+ ; Add to register post-increment
mov #byte_dest, er0
mov #5, r1l
add.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #60, r0l
beq .L12
fail
.L12:
add_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@eRd- ; Add to register post-decrement
mov #byte_dest, er0
mov #5, r1l
add.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #65, r0l
beq .L13
fail
.L13:
add_b_reg8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@+eRd ; Add to register pre-increment
mov #pre_byte, er0
mov #5, r1l
add.b r1l, @+er0 ; reg8 src, reg pre-incr dest
;;; .word 0x0179
;;; .word 0x9019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #70, r0l
beq .L14
fail
.L14:
add_b_reg8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@-eRd ; Add to register pre-decrement
mov #post_byte, er0
mov #5, r1l
add.b r1l, @-er0 ; reg8 src, reg pre-decr dest
;;; .word 0x0179
;;; .word 0xb019
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #75, r0l
beq .L15
fail
.L15:
add_b_reg8_disp16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement
mov #pre_byte, er0
mov #5, r1l
add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest
;;; .word 0x0179
;;; .word 0xc019
;;; .word 0x0001
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #80, r0l
beq .L16
fail
.L16:
add_b_reg8_disp32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement
mov #post_byte, er0
mov #5, r1l
add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest
;;; .word 0x0179
;;; .word 0xd819
;;; .word 0xffff
;;; .word 0xffff
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #85, r0l
beq .L17
fail
.L17:
add_b_reg8_abs8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:8
;; NOTE: for abs8, we will use the SBR register as a base,
;; since otherwise we would have to make sure that the destination
;; was in the zero page.
;;
mov #byte_dest-100, er0
ldc er0, sbr
mov #5, r1l
add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest
;;; .word 0x7f64
;;; .word 0x0890
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #90, r0l
beq .L18
fail
.L18:
add_b_reg8_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:16
mov #5, r0l
add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest
;;; .word 0x6a18
;;; .word byte_dest
;;; .word 0x0880
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #95, r0l
beq .L19
fail
.L19:
add_b_reg8_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; add.b reg8,@aa:32
mov #5, r0l
add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest
;;; .word 0x6a38
;;; .long byte_dest
;;; .word 0x0880
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #100, r0l
beq .L20
fail
.L20:
.endif
pass
exit 0

1865
sim/testsuite/sim/h8300/add.l.s Normal file
View File

File diff suppressed because it is too large Load Diff

87
sim/testsuite/sim/h8300/add.w.s Normal file
View File

@ -0,0 +1,87 @@
# Hitachi H8 testcase 'add.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# add.w xx:3, rd ; 0 a 0xxx rd (sx only)
# add.w xx:16, rd ; 7 9 1 rd imm16
# add.w rs, rd ; 0 9 rs rd
#
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
add_w_imm3:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.w #xx:3,Rd ; Immediate 3-bit operand
add.w #7, r0 ; FIXME will not assemble yet
; .word 0x0a70 ; Fake it until assembler will take it.
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7
test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
add_w_imm16:
;; add.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.w #xx:16,Rd
add.w #0x111, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
add_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.w Rs,Rd
mov.w #0x111, r1
add.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
test_h_gr16 0x0111 r1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
test_h_gr32 0xa5a50111 er1
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

74
sim/testsuite/sim/h8300/adds.s Normal file
View File

@ -0,0 +1,74 @@
# Hitachi H8 testcase 'adds'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# adds #1, erd ; 0 b 0 xerd
# adds #2, erd ; 0 b 8 xerd
# adds #4, erd ; 0 b 9 xerd
#
start
.if (sim_cpu) ; 32 bit only
adds_1:
set_grs_a5a5
set_ccr_zero
adds #1, er0
test_cc_clear ; adds should not affect any condition codes
test_h_gr32 0xa5a5a5a6 er0 ; result of adds #1
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
adds_2:
set_grs_a5a5
set_ccr_zero
adds #2, er0
test_cc_clear ; adds should not affect any condition codes
test_h_gr32 0xa5a5a5a7 er0 ; result of adds #2
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
adds_4:
set_grs_a5a5
set_ccr_zero
adds #4, er0
test_cc_clear ; adds should not affect any condition codes
test_h_gr32 0xa5a5a5a9 er0 ; result of adds #4
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
.endif
exit 0

993
sim/testsuite/sim/h8300/addx.s Normal file
View File

@ -0,0 +1,993 @@
# Hitachi H8 testcase 'addx'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# addx.b #xx:8, rd8 ; 9 rd8 xxxxxxxx
# addx.b #xx:8, @erd ; 7 d erd ???? 9 ???? xxxxxxxx
# addx.b #xx:8, @erd- ; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx
# addx.b rs8, rd8 ; 0 e rs8 rd8
# addx.b rs8, @erd ; 7 d erd ???? 0 e rs8 ????
# addx.b rs8, @erd- ; 0 1 7 6 6 c erd 1??? 0 e rs8 ????
# addx.b @ers, rd8 ; 7 c ers ???? 0 e ???? rd8
# addx.b @ers-, rd8 ; 0 1 7 6 6 c ers 00?? 0 e ???? rd8
# addx.b @ers, @erd ; 0 1 7 4 6 8 ers d 0 erd 1 ????
# addx.b @ers-, @erd- ; 0 1 7 6 6 c ers d a erd 1 ????
#
# coming soon:
# word ops
# long ops
.data
byte_src: .byte 0x5
byte_dest: .byte 0
.align 2
word_src: .word 0x505
word_dest: .word 0
.align 4
long_src: .long 0x50505
long_dest: .long 0
start
addx_b_imm8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,Rd ; Addx with carry initially zero.
addx.b #5, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_imm8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,Rd ; Addx with carry initially one.
set_carry_flag 1
addx.b #5, r0l ; Immediate 8-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xa5ab r0 ; add result: a5 + 5 + 1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5ab er0 ; add result: a5 + 5 + 1
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
addx_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,@eRd ; Addx to register indirect
mov #byte_dest, er0
addx.b #5, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #5, @byte_dest
beq .Lb1
fail
.Lb1:
addx_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b #xx:8,@eRd- ; Addx to register post-decrement
mov #byte_dest, er0
addx.b #5, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #10, @byte_dest
beq .Lb2
fail
.Lb2:
.endif
addx_b_reg8_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b Rs,Rd ; addx with carry initially zero
mov.b #5, r0h
addx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x05aa r0 ; add result: a5 + 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b Rs,Rd ; addx with carry initially one
mov.b #5, r0h
set_carry_flag 1
addx.b r0h, r0l ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0x05ab r0 ; add result: a5 + 5 + 1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505ab er0 ; add result: a5 + 5 + 1
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
addx_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b rs8,@eRd ; Addx to register indirect
mov #byte_dest, er0
mov.b #5, r1l
addx.b r1l, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #15, @byte_dest
beq .Lb3
fail
.Lb3:
addx_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b rs8,@eRd- ; Addx to register post-decrement
mov #byte_dest, er0
mov.b #5, r1l
addx.b r1l, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #20, @byte_dest
beq .Lb4
fail
.Lb4:
addx_b_rsind_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
mov #byte_src, er0
addx.b @er0, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src er0 ; er0 still contains address
test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_rspostdec_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs-,rd8 ; Addx to register post-decrement
mov #byte_src, er0
addx.b @er0-, r1l
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_src-1 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5aa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_b_rsind_rsind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs,rd8 ; Addx from reg indirect to reg
mov #byte_src, er0
mov #byte_dest, er1
addx.b @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_src er0 ; er0 still contains src address
test_h_gr32 byte_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #25, @byte_dest
beq .Lb5
fail
.Lb5:
addx_b_rspostdec_rspostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.b @eRs-,rd8 ; Addx to register post-decrement
mov #byte_src, er0
mov #byte_dest, er1
addx.b @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_src-1 er0 ; er0 contains src address minus one
test_h_gr32 byte_dest-1 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.b #30, @byte_dest
beq .Lb6
fail
.Lb6:
addx_w_imm16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,Rd ; Addx with carry initially zero.
addx.w #0x505, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xaaaa r0 ; add result: 0xa5a5 + 0x505
test_h_gr32 0xa5a5aaaa er0 ; add result: 0xa5a5 + 0x505
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_imm16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,Rd ; Addx with carry initially one.
set_carry_flag 1
addx.w #0x505, r0 ; Immediate 16-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr16 0xaaab r0 ; add result: 0xa5a5 + 0x505 + 1
test_h_gr32 0xa5a5aaab er0 ; add result: 0xa5a5 + 0x505 + 1
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_imm16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,@eRd ; Addx to register indirect
mov #word_dest, er0
addx.w #0x505, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x505, @word_dest
beq .Lw1
fail
.Lw1:
addx_w_imm16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w #xx:16,@eRd- ; Addx to register post-decrement
mov #word_dest, er0
addx.w #0x505, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0xa0a, @word_dest
beq .Lw2
fail
.Lw2:
addx_w_reg16_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w Rs,Rd ; addx with carry initially zero
mov.w #0x505, e0
addx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0505aaaa er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w Rs,Rd ; addx with carry initially one
mov.w #0x505, e0
set_carry_flag 1
addx.w e0, r0 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x0505aaab er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_reg16_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w rs8,@eRd ; Addx to register indirect
mov #word_dest, er0
mov.w #0x505, r1
addx.w r1, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest er0 ; er0 still contains address
test_h_gr32 0xa5a50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0xf0f, @word_dest
beq .Lw3
fail
.Lw3:
addx_w_reg16_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w rs8,@eRd- ; Addx to register post-decrement
mov #word_dest, er0
mov.w #0x505, r1
addx.w r1, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_dest-2 er0 ; er0 contains address minus one
test_h_gr32 0xa5a50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1414, @word_dest
beq .Lw4
fail
.Lw4:
addx_w_rsind_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
mov #word_src, er0
addx.w @er0, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src er0 ; er0 still contains address
test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_rspostdec_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs-,rd8 ; Addx to register post-decrement
mov #word_src, er0
addx.w @er0-, r1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 word_src-2 er0 ; er0 contains address minus one
test_h_gr32 0xa5a5aaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_w_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs,rd8 ; Addx from reg indirect to reg
mov #word_src, er0
mov #word_dest, er1
addx.w @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_src er0 ; er0 still contains src address
test_h_gr32 word_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1919, @word_dest
beq .Lw5
fail
.Lw5:
addx_w_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.w @eRs-,rd8 ; Addx to register post-decrement
mov #word_src, er0
mov #word_dest, er1
addx.w @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 word_src-2 er0 ; er0 contains src address minus one
test_h_gr32 word_dest-2 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.w #0x1e1e, @word_dest
beq .Lw6
fail
.Lw6:
addx_l_imm32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,Rd ; Addx with carry initially zero.
addx.l #0x50505, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5aaaaaa er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_imm32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,Rd ; Addx with carry initially one.
set_carry_flag 1
addx.l #0x50505, er0 ; Immediate 32-bit operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0xa5aaaaab er0 ; add result:
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_imm32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,@eRd ; Addx to register indirect
mov #long_dest, er0
addx.l #0x50505, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x50505, @long_dest
beq .Ll1
fail
.Ll1:
addx_l_imm32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l #xx:32,@eRd- ; Addx to register post-decrement
mov #long_dest, er0
addx.l #0x50505, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0xa0a0a, @long_dest
beq .Ll2
fail
.Ll2:
addx_l_reg32_0:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l Rs,Rd ; addx with carry initially zero
mov.l #0x50505, er0
addx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50505 er0 ; add load
test_h_gr32 0xa5aaaaaa er1 ; add result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l Rs,Rd ; addx with carry initially one
mov.l #0x50505, er0
set_carry_flag 1
addx.l er0, er1 ; Register operand
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 0x50505 er0 ; add result:
test_h_gr32 0xa5aaaaab er1 ; add result:
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_reg32_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l rs8,@eRd ; Addx to register indirect
mov #long_dest, er0
mov.l #0x50505, er1
addx.l er1, @er0
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest er0 ; er0 still contains address
test_h_gr32 0x50505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0xf0f0f, @long_dest
beq .Ll3
fail
.Ll3:
addx_l_reg32_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l rs8,@eRd- ; Addx to register post-decrement
mov #long_dest, er0
mov.l #0x50505, er1
addx.l er1, @er0-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_dest-4 er0 ; er0 contains address minus one
test_h_gr32 0x50505 er1 ; er1 contains the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x141414, @long_dest
beq .Ll4
fail
.Ll4:
addx_l_rsind_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
mov #long_src, er0
addx.l @er0, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src er0 ; er0 still contains address
test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_rspostdec_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs-,rd8 ; Addx to register post-decrement
mov #long_src, er0
addx.l @er0-, er1
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 long_src-4 er0 ; er0 contains address minus one
test_h_gr32 0xa5aaaaaa er1 ; er1 contains the sum
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
addx_l_rsind_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs,rd8 ; Addx from reg indirect to reg
mov #long_src, er0
mov #long_dest, er1
addx.l @er0, @er1
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_src er0 ; er0 still contains src address
test_h_gr32 long_dest er1 ; er1 still contains dst address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x191919, @long_dest
beq .Ll5
fail
.Ll5:
addx_l_rspostdec_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; addx.l @eRs-,rd8 ; Addx to register post-decrement
mov #long_src, er0
mov #long_dest, er1
addx.l @er0-, @er1-
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 long_src-4 er0 ; er0 contains src address minus one
test_h_gr32 long_dest-4 er1 ; er1 contains dst address minus one
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the add to memory.
cmp.l #0x1e1e1e, @long_dest
beq .Ll6
fail
.Ll6:
.endif
pass
exit 0

55
sim/testsuite/sim/h8300/allinsn.exp Normal file
View File

@ -0,0 +1,55 @@
# Hitachi H8/300 (h, s, sx) simulator testsuite
set all "h8300 h8300h h8300s h8sx"
if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then {
run_sim_test add.b.s $all
run_sim_test add.w.s $all
run_sim_test add.l.s $all
run_sim_test adds.s $all
run_sim_test addx.s $all
run_sim_test and.b.s $all
run_sim_test and.w.s $all
run_sim_test and.l.s $all
run_sim_test bfld.s h8sx
run_sim_test bra.s $all
run_sim_test bset.s $all
run_sim_test cmp.b.s $all
run_sim_test cmp.w.s $all
run_sim_test cmp.l.s $all
run_sim_test daa.s $all
run_sim_test das.s $all
run_sim_test dec.s $all
run_sim_test ext.w.s $all
run_sim_test ext.l.s $all
run_sim_test inc.s $all
run_sim_test jmp.s $all
run_sim_test ldc.s $all
run_sim_test mac.s $all
run_sim_test mov.b.s $all
run_sim_test mov.w.s $all
run_sim_test mov.l.s $all
run_sim_test movmd.s h8sx
run_sim_test movsd.s h8sx
run_sim_test neg.s $all
run_sim_test nop.s $all
run_sim_test not.s $all
run_sim_test or.b.s $all
run_sim_test or.w.s $all
run_sim_test or.l.s $all
run_sim_test rotl.s $all
run_sim_test rotr.s $all
run_sim_test rotxl.s $all
run_sim_test rotxr.s $all
run_sim_test shal.s $all
run_sim_test shar.s $all
run_sim_test shll.s $all
run_sim_test shlr.s $all
run_sim_test stc.s $all
run_sim_test sub.b.s $all
run_sim_test sub.w.s $all
run_sim_test sub.l.s $all
run_sim_test xor.b.s $all
run_sim_test xor.w.s $all
run_sim_test xor.l.s $all
}

491
sim/testsuite/sim/h8300/and.b.s Normal file
View File

@ -0,0 +1,491 @@
# Hitachi H8 testcase 'and.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# and.b #xx:8, rd ; e rd xxxxxxxx
# and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx
# and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
# and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
# and.b rs, rd ; 1 6 rs rd
# and.b reg8, @erd ; 7 d rd ???? 1 6 rs ????
# and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs
# and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs
# and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs
# and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs
#
# andc #xx:8, ccr ; 0 6 xxxxxxxx
# andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
and_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.b #xx:8,Rd
and.b #0xaa, r0l ; Immediate 8-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a0 r0 ; and result: a5 & aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
and_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd
mov #byte_dest, er0
and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L1
fail
.L1:
and_b_imm8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd+
mov #byte_dest, er0
and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xe055
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L2
fail
.L2:
and_b_imm8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@eRd-
mov #byte_dest, er0
and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L3
fail
.L3:
and_b_imm8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@+eRd
mov #pre_byte, er0
and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xe055
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L4
fail
.L4:
and_b_imm8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b #xx:8,@-eRd
mov #post_byte, er0
and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xe0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L5
fail
.L5:
.endif
and_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.b Rs,Rd
mov.b #0xaa, r0h
and.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xaaa0 r0 ; and result: a5 & aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
and_b_reg8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd ; And to register indirect
mov #byte_dest, er0
mov #0x55, r1l
and.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1690
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L6
fail
.L6:
and_b_reg8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd+ ; And to register post-incr
mov #byte_dest, er0
mov #0xaa, r1l
and.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8069
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L7
fail
.L7:
and_b_reg8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@eRd- ; And to register post-decr
mov #byte_dest, er0
mov #0x55, r1l
and.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa069
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L8
fail
.L8:
and_b_reg8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@+eRd ; And to register post-incr
mov #pre_byte, er0
mov #0xaa, r1l
and.b r1l, @+er0 ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x9069
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L9
fail
.L9:
and_b_reg8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; and.b rs8,@-eRd ; And to register post-decr
mov #post_byte, er0
mov #0x55, r1l
and.b r1l, @-er0 ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xb069
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the and to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x05, r0l
beq .L10
fail
.L10:
andc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; andc #xx:8,ccr
set_ccr 0xff
test_neg_set
andc #0xf7, ccr ; Immediate 8-bit operand (neg flag)
test_neg_clear
test_zero_set
andc #0xfb, ccr ; Immediate 8-bit operand (zero flag)
test_zero_clear
test_ovf_set
andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_clear
test_carry_set
andc #0xfe, ccr ; Immediate 8-bit operand (carry flag)
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

77
sim/testsuite/sim/h8300/and.l.s Normal file
View File

@ -0,0 +1,77 @@
# Hitachi H8 testcase 'and.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
and_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l #xx:16,Rd
and.l #0xaaaa:16, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
and_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l #xx:32,Rd
and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
and_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.l Rs,Rd
mov.l #0xaaaaaaaa, er1
and.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa
test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

61
sim/testsuite/sim/h8300/and.w.s Normal file
View File

@ -0,0 +1,61 @@
# Hitachi H8 testcase 'and.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
and_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.w #xx:16,Rd
and.w #0xaaaa, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
and_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; and.w Rs,Rd
mov.w #0xaaaa, r1
and.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa
test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa
test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

286
sim/testsuite/sim/h8300/bfld.s Normal file
View File

@ -0,0 +1,286 @@
# Hitachi H8 testcase 'bfld', 'bfst'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src: .byte 0xa5
byte_dst: .byte 0
start
.if (sim_cpu == h8sx)
bfld_imm8_ind:
set_grs_a5a5
mov #byte_src, er2
;; bfld #xx:8, @ers, rd8
set_ccr_zero
bfld #1, @er2, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bfld #2, @er2, r1l
test_cc_clear
test_h_gr8 0 r1l
set_ccr_zero
bfld #7, @er2, r1l
test_cc_clear
test_h_gr8 5 r1l
set_ccr_zero
bfld #0x10, @er2, r1l
test_cc_clear
test_h_gr8 0 r1l
set_ccr_zero
bfld #0x20, @er2, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bfld #0xf0, @er2, r1l
test_cc_clear
test_h_gr8 0xa r1l
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 0xa5a5a50a er1
test_h_gr32 byte_src er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
bfld_imm8_abs16:
set_grs_a5a5
;; bfld #xx:8, @aa:16, rd8
set_ccr_zero
bfld #0x80, @byte_src:16, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bfld #0x40, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0 r1l
set_ccr_zero
bfld #0xe0, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0x5 r1l
set_ccr_zero
bfld #0x3c, @byte_src:16, r1l
test_cc_clear
test_h_gr8 9 r1l
set_ccr_zero
bfld #0xfe, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0x52 r1l
set_ccr_zero
bfld #0, @byte_src:16, r1l
test_cc_clear
test_h_gr8 0 r1l
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 0xa5a5a500 er1
test_h_gr32 0xa5a5a5a5 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
bfst_imm8_ind:
set_grs_a5a5
mov #byte_dst, er2
;; bfst rd8, #xx:8, @ers
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #1, @er2
;;; .word 0x7d20
;;; .word 0xf901
test_cc_clear
cmp.b #1, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #2, @er2
;;; .word 0x7d20
;;; .word 0xf902
test_cc_clear
cmp.b #2, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #7, @er2
;;; .word 0x7d20
;;; .word 0xf907
test_cc_clear
cmp.b #5, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x10, @er2
;;; .word 0x7d20
;;; .word 0xf910
test_cc_clear
cmp.b #0x10, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x20, @er2
;;; .word 0x7d20
;;; .word 0xf920
test_cc_clear
cmp.b #0x20, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0xf0, @er2
;;; .word 0x7d20
;;; .word 0xf9f0
test_cc_clear
cmp.b #0x50, @byte_dst
bne fail1:16
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 0xa5a5a5a5 er1
test_h_gr32 byte_dst er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
bfst_imm8_abs32:
set_grs_a5a5
;; bfst #xx:8, @aa:32, rd8
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x80, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf980
test_cc_clear
cmp.b #0x80, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x40, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf940
test_cc_clear
cmp.b #0x40, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0xe0, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf9e0
test_cc_clear
cmp.b #0xa0, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x3c, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf93c
test_cc_clear
cmp.b #0x14, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0xfe, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf9fe
test_cc_clear
cmp.b #0x4a, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf900
test_cc_clear
cmp.b #0x0, @byte_dst
bne fail1:16
mov.b #0, @byte_dst
set_ccr_zero
bfst r1l, #0x38, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf938
test_cc_clear
cmp.b #0x28, @byte_dst
bne fail1:16
;;
;; Now let's do one in which the bits in the destination
;; are appropriately combined with the bits in the source.
;;
mov.b #0xc3, @byte_dst
set_ccr_zero
bfst r1l, #0x3c, @byte_dst:32
;;; .word 0x6a38
;;; .long byte_dst
;;; .word 0xf93c
test_cc_clear
cmp.b #0xd7, @byte_dst
bne fail1:16
test_grs_a5a5
.endif
pass
exit 0
fail1: fail

165
sim/testsuite/sim/h8300/bra.s Normal file
View File

@ -0,0 +1,165 @@
# Hitachi H8 testcase 'bra'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx)
.data
.align 4
disp8: .long tgt_reg8
disp16: .long tgt_reg16
disp32: .long tgt_reg32
dslot: .byte 0
.text
.endif
bra_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; bra dd:8 ; 8-bit displacement
bra tgt_8:8
;;; .word 0x40xx ; where "xx" is tgt_8 - '.'.
fail
tgt_8:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; not available in h8/300 mode
bra_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; bra dd:16 ; 16-bit displacement
bra tgt_24:16 ; NOTE: hard-coded to avoid relaxing.
;;; .word 0x5800
;;; .word tgt_24 - .
fail
tgt_24:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx)
bra_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; bra rn.b ; 8-bit register indirect
sub.l #src8, @disp8
mov.l @disp8, er5
;;; bra er5.b
.word 0x5955
src8: fail
tgt_reg8:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
;;; test_h_gr32 tgt_reg8 er5
test_gr_a5a5 6
test_gr_a5a5 7
bra_reg16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; bra rn.w ; 16-bit register indirect
sub.l #src16, @disp16
mov.l @disp16, er5
;;; bra er5.w
.word 0x5956
src16: fail
tgt_reg16:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
;;; test_h_gr32 tgt_reg16 er5
test_gr_a5a5 6
test_gr_a5a5 7
bra_reg32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; bra ern ; 32-bit register indirect
sub.l #src32, @disp32
mov.l @disp32, er5
;;; bra er5.l
.word 0x5957
src32: fail
tgt_reg32:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
;;; test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
bra_s: set_grs_a5a5
set_ccr_zero
;;; bra/s tgt_post_delay
.word 0x4017
;; The following instruction is in the delay slot, and should execute.
mov.b #1, @dslot
;; After this, the next instructions should not execute.
fail
tgt_post_delay:
test_cc_clear
cmp.b #0, @dslot ; Should be non-zero if delay slot executed.
bne dslot_ok
fail
dslot_ok:
test_gr_a5a5 0 ; Make sure all general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

107
sim/testsuite/sim/h8300/brabc.s Normal file
View File

@ -0,0 +1,107 @@
# Hitachi H8 testcase 'bra/bc'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src: .byte 0xa5
start
.if (sim_cpu == h8sx)
brabc_ind_disp8:
set_grs_a5a5
mov #byte_src, er1
set_ccr_zero
;; bra/bc xx:3, @erd, disp8
bra/bc #1, @er1, .Lpass1:8
;;; .word 0x7c10
;;; .word 0x4110
fail
.Lpass1:
bra/bc #2, @er1, .Lfail1:8
;;; .word 0x7c10
;;; .word 0x4202
bra .Lpass2
.Lfail1:
fail
.Lpass2:
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 byte_src er1
test_h_gr32 0xa5a5a5a5 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
brabc_abs16_disp16:
set_grs_a5a5
set_ccr_zero
;; bra/bc xx:3, @aa:16, disp16
bra/bc #1, @byte_src:16, .Lpass3:16
fail
.Lpass3:
bra/bc #2, @byte_src:16, .Lfail2:16
bra .Lpass4
.Lfail2:
fail
.Lpass4:
test_cc_clear
test_grs_a5a5
brabs_ind_disp8:
set_grs_a5a5
mov #byte_src, er1
set_ccr_zero
;; bra/bs xx:3, @erd, disp8
bra/bs #2, @er1, .Lpass5:8
;;; .word 0x7c10
;;; .word 0x4a10
fail
.Lpass5:
bra/bs #1, @er1, .Lfail3:8
;;; .word 0x7c10
;;; .word 0x4902
bra .Lpass6
.Lfail3:
fail
.Lpass6:
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 byte_src er1
test_h_gr32 0xa5a5a5a5 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
brabs_abs32_disp16:
set_grs_a5a5
set_ccr_zero
;; bra/bs xx:3, @aa:32, disp16
bra/bs #2, @byte_src:32, .Lpass7:16
fail
.Lpass7:
bra/bs #1, @byte_src:32, .Lfail4:16
bra .Lpass8
.Lfail4:
fail
.Lpass8:
test_cc_clear
test_grs_a5a5
.endif
pass
exit 0

841
sim/testsuite/sim/h8300/bset.s Normal file
View File

@ -0,0 +1,841 @@
# Hitachi H8 testcase 'bset', 'bclr'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
#
# bset xx:3, rd8 ; 7 0 ?xxx rd8
# bclr xx:3, rd8 ; 7 2 ?xxx rd8
# bset xx:3, @erd ; 7 d 0rd ???? 7 0 ?xxx ????
# bclr xx:3, @erd ; 7 d 0rd ???? 7 2 ?xxx ????
# bset xx:3, @abs16 ; 6 a 1 1??? aa:16 7 0 ?xxx ????
# bclr xx:3, @abs16 ; 6 a 1 1??? aa:16 7 2 ?xxx ????
# bset reg8, rd8 ; 6 0 rs8 rd8
# bclr reg8, rd8 ; 6 2 rs8 rd8
# bset reg8, @erd ; 7 d 0rd ???? 6 0 rs8 ????
# bclr reg8, @erd ; 7 d 0rd ???? 6 2 rs8 ????
# bset reg8, @abs32 ; 6 a 3 1??? aa:32 6 0 rs8 ????
# bclr reg8, @abs32 ; 6 a 3 1??? aa:32 6 2 rs8 ????
#
# bset/eq xx:3, rd8
# bclr/eq xx:3, rd8
# bset/ne xx:3, rd8
# bclr/ne xx:3, rd8
.data
byte_dst: .byte 0
start
bset_imm3_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; bset xx:3, rd8
mov #0, r1l
set_ccr_zero
bset #0, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bset #1, r1l
test_cc_clear
test_h_gr8 3 r1l
set_ccr_zero
bset #2, r1l
test_cc_clear
test_h_gr8 7 r1l
set_ccr_zero
bset #3, r1l
test_cc_clear
test_h_gr8 15 r1l
set_ccr_zero
bset #4, r1l
test_cc_clear
test_h_gr8 31 r1l
set_ccr_zero
bset #5, r1l
test_cc_clear
test_h_gr8 63 r1l
set_ccr_zero
bset #6, r1l
test_cc_clear
test_h_gr8 127 r1l
set_ccr_zero
bset #7, r1l
test_cc_clear
test_h_gr8 255 r1l
.if (sim_cpu == h8300)
test_h_gr16 0xa5ff, r1
.else
test_h_gr32 0xa5a5a5ff er1
.endif
bclr_imm3_reg8:
set_ccr_zero
bclr #7, r1l
test_cc_clear
test_h_gr8 127 r1l
set_ccr_zero
bclr #6, r1l
test_cc_clear
test_h_gr8 63 r1l
set_ccr_zero
bclr #5, r1l
test_cc_clear
test_h_gr8 31 r1l
set_ccr_zero
bclr #4, r1l
test_cc_clear
test_h_gr8 15 r1l
set_ccr_zero
bclr #3, r1l
test_cc_clear
test_h_gr8 7 r1l
set_ccr_zero
bclr #2, r1l
test_cc_clear
test_h_gr8 3 r1l
set_ccr_zero
bclr #1, r1l
test_cc_clear
test_h_gr8 1 r1l
set_ccr_zero
bclr #0, r1l
test_cc_clear
test_h_gr8 0 r1l
test_gr_a5a5 0 ; Make sure other general regs not disturbed
.if (sim_cpu == h8300)
test_h_gr16 0xa500 r1
.else
test_h_gr32 0xa5a5a500 er1
.endif
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu)
bset_imm3_ind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; bset xx:3, @erd
mov #byte_dst, er1
set_ccr_zero
bset #0, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 1 r2l
set_ccr_zero
bset #1, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 3 r2l
set_ccr_zero
bset #2, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 7 r2l
set_ccr_zero
bset #3, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 15 r2l
set_ccr_zero
bset #4, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 31 r2l
set_ccr_zero
bset #5, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 63 r2l
set_ccr_zero
bset #6, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 127 r2l
set_ccr_zero
bset #7, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 255 r2l
.if (sim_cpu == h8300)
test_h_gr16 0xa5ff r2
.else
test_h_gr32 0xa5a5a5ff er2
.endif
bclr_imm3_ind:
set_ccr_zero
bclr #7, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 127 r2l
set_ccr_zero
bclr #6, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 63 r2l
set_ccr_zero
bclr #5, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 31 r2l
set_ccr_zero
bclr #4, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 15 r2l
set_ccr_zero
bclr #3, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 7 r2l
set_ccr_zero
bclr #2, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 3 r2l
set_ccr_zero
bclr #1, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 1 r2l
set_ccr_zero
bclr #0, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 0 r2l
test_gr_a5a5 0 ; Make sure other general regs not disturbed
.if (sim_cpu == h8300)
test_h_gr16 byte_dst r1
test_h_gr16 0xa500 r2
.else
test_h_gr32 byte_dst er1
test_h_gr32 0xa5a5a500 er2
.endif
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
bset_imm3_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; bset xx:3, @aa:16
set_ccr_zero
bset #0, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 1 r2l
set_ccr_zero
bset #1, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 3 r2l
set_ccr_zero
bset #2, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 7 r2l
set_ccr_zero
bset #3, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 15 r2l
set_ccr_zero
bset #4, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 31 r2l
set_ccr_zero
bset #5, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 63 r2l
set_ccr_zero
bset #6, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 127 r2l
set_ccr_zero
bset #7, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 255 r2l
.if (sim_cpu == h8300)
test_h_gr16 0xa5ff r2
.else
test_h_gr32 0xa5a5a5ff er2
.endif
bclr_imm3_abs16:
set_ccr_zero
bclr #7, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 127 r2l
set_ccr_zero
bclr #6, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 63 r2l
set_ccr_zero
bclr #5, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 31 r2l
set_ccr_zero
bclr #4, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 15 r2l
set_ccr_zero
bclr #3, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 7 r2l
set_ccr_zero
bclr #2, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 3 r2l
set_ccr_zero
bclr #1, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 1 r2l
set_ccr_zero
bclr #0, @byte_dst:16
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 0 r2l
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
.if (sim_cpu == h8300)
test_h_gr16 0xa500 r2
.else
test_h_gr32 0xa5a5a500 er2
.endif
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
bset_rs8_rd8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; bset rs8, rd8
mov #0, r1h
mov #0, r1l
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 1 r1l
mov #1, r1h
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 3 r1l
mov #2, r1h
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 7 r1l
mov #3, r1h
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 15 r1l
mov #4, r1h
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 31 r1l
mov #5, r1h
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 63 r1l
mov #6, r1h
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 127 r1l
mov #7, r1h
set_ccr_zero
bset r1h, r1l
test_cc_clear
test_h_gr8 255 r1l
.if (sim_cpu == h8300)
test_h_gr16 0x07ff, r1
.else
test_h_gr32 0xa5a507ff er1
.endif
bclr_rs8_rd8:
mov #7, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 127 r1l
mov #6, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 63 r1l
mov #5, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 31 r1l
mov #4, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 15 r1l
mov #3, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 7 r1l
mov #2, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 3 r1l
mov #1, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 1 r1l
mov #0, r1h
set_ccr_zero
bclr r1h, r1l
test_cc_clear
test_h_gr8 0 r1l
test_gr_a5a5 0 ; Make sure other general regs not disturbed
.if (sim_cpu == h8300)
test_h_gr16 0x0000 r1
.else
test_h_gr32 0xa5a50000 er1
.endif
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu)
bset_rs8_ind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; bset rs8, @erd
mov #byte_dst, er1
mov #0, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 1 r2l
mov #1, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 3 r2l
mov #2, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 7 r2l
mov #3, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 15 r2l
mov #4, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 31 r2l
mov #5, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 63 r2l
mov #6, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 127 r2l
mov #7, r2h
set_ccr_zero
bset r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 255 r2l
.if (sim_cpu == h8300)
test_h_gr16 0x07ff r2
.else
test_h_gr32 0xa5a507ff er2
.endif
bclr_rs8_ind:
mov #7, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 127 r2l
mov #6, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 63 r2l
mov #5, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 31 r2l
mov #4, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 15 r2l
mov #3, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 7 r2l
mov #2, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 3 r2l
mov #1, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 1 r2l
mov #0, r2h
set_ccr_zero
bclr r2h, @er1
test_cc_clear
mov @er1, r2l
test_h_gr8 0 r2l
test_gr_a5a5 0 ; Make sure other general regs not disturbed
.if (sim_cpu == h8300)
test_h_gr16 byte_dst r1
test_h_gr16 0x0000 r2
.else
test_h_gr32 byte_dst er1
test_h_gr32 0xa5a50000 er2
.endif
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
bset_rs8_abs32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; bset rs8, @aa:32
mov #0, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 1 r2l
mov #1, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 3 r2l
mov #2, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 7 r2l
mov #3, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 15 r2l
mov #4, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 31 r2l
mov #5, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 63 r2l
mov #6, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 127 r2l
mov #7, r2h
set_ccr_zero
bset r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 255 r2l
.if (sim_cpu == h8300)
test_h_gr16 0x07ff r2
.else
test_h_gr32 0xa5a507ff er2
.endif
bclr_rs8_abs32:
mov #7, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 127 r2l
mov #6, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 63 r2l
mov #5, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 31 r2l
mov #4, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 15 r2l
mov #3, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 7 r2l
mov #2, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 3 r2l
mov #1, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 1 r2l
mov #0, r2h
set_ccr_zero
bclr r2h, @byte_dst:32
test_cc_clear
mov @byte_dst, r2l
test_h_gr8 0 r2l
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
.if (sim_cpu == h8300)
test_h_gr16 0x0000 r2
.else
test_h_gr32 0xa5a50000 er2
.endif
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx)
bset_eq_imm3_abs16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; bset/eq xx:3, rd8
mov #0, @byte_dst
set_ccr_zero
bset/eq #0, @byte_dst:16 ; Zero is clear, should have no effect.
test_cc_clear
mov @byte_dst, r1l
test_h_gr8 0 r1l
set_ccr_zero
orc #4, ccr ; Set zero flag
bset/eq #0, @byte_dst:16 ; Zero is set: operation should succeed.
test_neg_clear
test_zero_set
test_ovf_clear
test_carry_clear
mov @byte_dst, r1l
test_h_gr8 1 r1l
bclr_eq_imm3_abs32:
mov #1, @byte_dst
set_ccr_zero
bclr/eq #0, @byte_dst:32 ; Zero is clear, should have no effect.
test_cc_clear
mov @byte_dst, r1l
test_h_gr8 1 r1l
set_ccr_zero
orc #4, ccr ; Set zero flag
bclr/eq #0, @byte_dst:32 ; Zero is set: operation should succeed.
test_neg_clear
test_zero_set
test_ovf_clear
test_carry_clear
mov @byte_dst, r1l
test_h_gr8 0 r1l
test_gr_a5a5 0 ; Make sure other general regs not disturbed
.if (sim_cpu == h8300)
test_h_gr16 0xa500 r1
.else
test_h_gr32 0xa5a5a500 er1
.endif
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

625
sim/testsuite/sim/h8300/cmp.b.s Normal file
View File

@ -0,0 +1,625 @@
# Hitachi H8 testcase 'cmp.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# cmp.b #xx:8, rd ; a rd xxxxxxxx
# cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
# cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
# cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
# cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
# cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
# cmp.b rs, rd ; 1 c rs rd
# cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ????
# cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs
# cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs
# cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs
# cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs
#
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
cmp_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.b #xx:8,Rd
cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest
beq .Leq1
fail
.Leq1: cmp.b #0xa6, r0l
blt .Llt1
fail
.Llt1: cmp.b #0xa4, r0l
bgt .Lgt1
fail
.Lgt1:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
cmp_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@eRd
mov #byte_dest, er0
cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xa0a5
beq .Leq2
fail
.Leq2: set_ccr_zero
cmp.b #0xa6, @er0
;;; .word 0x7d00
;;; .word 0xa0a6
blt .Llt2
fail
.Llt2: set_ccr_zero
cmp.b #0xa4, @er0
;;; .word 0x7d00
;;; .word 0xa0a4
bgt .Lgt2
fail
.Lgt2:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L2
fail
.L2:
cmp_b_imm8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@eRd+
mov #byte_dest, er0
cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq3
fail
.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa6, @er0+
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt3
fail
.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa4, @er0+
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt3
fail
.Lgt3:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L3
fail
.L3:
cmp_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@eRd-
mov #byte_dest, er0
cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq4
fail
.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa6, @er0-
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt4
fail
.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest, er0
set_ccr_zero
cmp.b #0xa4, @er0-
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt4
fail
.Lgt4:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L4
fail
.L4:
cmp_b_imm8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@+eRd
mov #pre_byte, er0
cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq5
fail
.Leq5: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte, er0
set_ccr_zero
cmp.b #0xa6, @+er0
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt5
fail
.Llt5: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte, er0
set_ccr_zero
cmp.b #0xa4, @+er0
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt5
fail
.Lgt5:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L5
fail
.L5:
cmp_b_imm8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b #xx:8,@-eRd
mov #post_byte, er0
cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xa0a5
beq .Leq6
fail
.Leq6: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte, er0
set_ccr_zero
cmp.b #0xa6, @-er0
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xa0a6
blt .Llt6
fail
.Llt6: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte, er0
set_ccr_zero
cmp.b #0xa4, @-er0
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xa0a4
bgt .Lgt6
fail
.Lgt6:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L6
fail
.L6:
.endif
cmp_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.b Rs,Rd
mov.b #0xa5, r0h
cmp.b r0h, r0l ; Reg8 src, reg8 dst
beq .Leq7
fail
.Leq7: mov.b #0xa6, r0h
cmp.b r0h, r0l
blt .Llt7
fail
.Llt7: mov.b #0xa4, r0h
cmp.b r0h, r0l
bgt .Lgt7
fail
.Lgt7:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa4a5 r0 ; r0l unchanged.
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
cmp_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b rs8,@eRd ; cmp reg8 to register indirect
mov #byte_dest, er0
mov #0xa5, r1l
cmp.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1c90
beq .Leq8
fail
.Leq8: set_ccr_zero
mov #0xa6, r1l
cmp.b r1l, @er0
;;; .word 0x7d00
;;; .word 0x1c90
blt .Llt8
fail
.Llt8: set_ccr_zero
mov #0xa4, r1l
cmp.b r1l, @er0
;;; .word 0x7d00
;;; .word 0x1c90
bgt .Lgt8
fail
.Lgt8:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (no change).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L8
fail
.L8:
cmp_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@eRd+
mov #byte_dest, er0
mov #0xa5, r1l
cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst
;;; .word 0x0179
;;; .word 0x8029
beq .Leq9
fail
.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @er0+
;;; .word 0x0179
;;; .word 0x8029
blt .Llt9
fail
.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one
mov #byte_dest er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @er0+
;;; .word 0x0179
;;; .word 0x8029
bgt .Lgt9
fail
.Lgt9:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L9
fail
.L9:
cmp_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@eRd-
mov #byte_dest, er0
mov #0xa5, r1l
cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst
;;; .word 0x0179
;;; .word 0xa029
beq .Leq10
fail
.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @er0-
;;; .word 0x0179
;;; .word 0xa029
blt .Llt10
fail
.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one
mov #byte_dest er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @er0-
;;; .word 0x0179
;;; .word 0xa029
bgt .Lgt10
fail
.Lgt10:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L10
fail
.L10:
cmp_b_reg8_rdpreinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@+eRd
mov #pre_byte, er0
mov #0xa5, r1l
cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst
;;; .word 0x0179
;;; .word 0x9029
beq .Leq11
fail
.Leq11: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @+er0
;;; .word 0x0179
;;; .word 0x9029
blt .Llt11
fail
.Llt11: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #pre_byte er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @+er0
;;; .word 0x0179
;;; .word 0x9029
bgt .Lgt11
fail
.Lgt11:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L11
fail
.L11:
cmp_b_reg8_rdpredec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; cmp.b reg8,@-eRd
mov #post_byte, er0
mov #0xa5, r1l
cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst
;;; .word 0x0179
;;; .word 0xb029
beq .Leq12
fail
.Leq12: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte er0
mov #0xa6, r1l
set_ccr_zero
cmp.b r1l, @-er0
;;; .word 0x0179
;;; .word 0xb029
blt .Llt12
fail
.Llt12: test_h_gr32 byte_dest er0 ; er0 contains destination address
mov #post_byte er0
mov #0xa4, r1l
set_ccr_zero
cmp.b r1l, @-er0
;;; .word 0x0179
;;; .word 0xb029
bgt .Lgt12
fail
.Lgt12:
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the cmp to memory (memory unchanged).
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L12
fail
.L12:
.endif
pass
exit 0

106
sim/testsuite/sim/h8300/cmp.l.s Normal file
View File

@ -0,0 +1,106 @@
# Hitachi H8 testcase 'cmp.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
cmp_l_imm3: ;
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.l #xx:3,eRd ; Immediate 3-bit operand
mov.l #5, er0
cmp.l #5, er0
beq eq3
fail
eq3:
cmp.l #6, er0
blt lt3
fail
lt3:
cmp.l #4, er0
bgt gt3
fail
gt3:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x00000005 er0 ; er0 unchanged
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
cmp_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.l #xx:8,Rd
cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand
beq eqi
fail
eqi: cmp.l #0xa5a5a5a6, er0
blt lti
fail
lti: cmp.l #0xa5a5a5a4, er0
bgt gti
fail
gti:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.l Rs,Rd
mov.l #0xa5a5a5a5, er1
cmp.l er1, er0 ; Register operand
beq eqr
fail
eqr: mov.l #0xa5a5a5a6, er1
cmp.l er1, er0
blt ltr
fail
ltr: mov.l #0xa5a5a5a4, er1
cmp.l er1, er0
bgt gtr
fail
gtr:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

110
sim/testsuite/sim/h8300/cmp.w.s Normal file
View File

@ -0,0 +1,110 @@
# Hitachi H8 testcase 'cmp.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
cmp_w_imm3: ;
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w #xx:3,Rd ; Immediate 3-bit operand
mov.w #5, r0
cmp.w #5, r0
beq eq3
fail
eq3:
cmp.w #6, r0
blt lt3
fail
lt3:
cmp.w #4, r0
bgt gt3
fail
gt3:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a50005 er0 ; er0 unchanged
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
cmp_w_imm16: ; cmp.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w #xx:8,Rd
cmp.w #0xa5a5, r0 ; Immediate 16-bit operand
beq eqi
fail
eqi: cmp.w #0xa5a6, r0
blt lti
fail
lti: cmp.w #0xa5a4, r0
bgt gti
fail
gti:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
cmp_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; cmp.w Rs,Rd
mov.w #0xa5a5, r1
cmp.w r1, r0 ; Register operand
beq eqr
fail
eqr: mov.w #0xa5a6, r1
cmp.w r1, r0
blt ltr
fail
ltr: mov.w #0xa5a4, r1
cmp.w r1, r0
bgt gtr
fail
gtr:
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a5 r0 ; r0 unchanged.
test_h_gr16 0xa5a4 r1 ; r1 unchanged.
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

36
sim/testsuite/sim/h8300/daa.s Normal file
View File

@ -0,0 +1,36 @@
# Hitachi H8 testcase 'daa'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
daa_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; daa Rd
daa r0l ; register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr8 5 r0l
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

36
sim/testsuite/sim/h8300/das.s Normal file
View File

@ -0,0 +1,36 @@
# Hitachi H8 testcase 'das'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
das_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; das Rd
das r0l ; register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

117
sim/testsuite/sim/h8300/dec.s Normal file
View File

@ -0,0 +1,117 @@
# Hitachi H8 testcase 'dec.b, dec.w, dec.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
dec_b:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.b Rd
dec.b r0h ; Decrement 8-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa4a5 r0 ; dec result: a4|a5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a4a5 er0 ; dec result: a5|a5|a4|a5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; non-zero means h8300h, s, or sx
dec_w_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.w #1, Rd
dec.w #1, r0 ; Decrement 16-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a4 r0 ; dec result: a5|a4
test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
dec_w_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.w #2, Rd
dec.w #2, r0 ; Decrement 16-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a3 r0 ; dec result: a5|a3
test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
dec_l_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.l #1, eRd
dec.l #1, er0 ; Decrement 32-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a4 er0 ; dec result: a5|a5|a5|a4
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
dec_l_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; dec.l #2, eRd
dec.l #2, er0 ; Decrement 32-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a3 er0 ; dec result: a5|a5|a5|a3
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

1146
sim/testsuite/sim/h8300/ext.l.s Normal file
View File

File diff suppressed because it is too large Load Diff

580
sim/testsuite/sim/h8300/ext.w.s Normal file
View File

@ -0,0 +1,580 @@
# Hitachi H8 testcase 'exts.w, extu.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
.align 2
pos: .word 0xff01
neg: .word 0x0080
.text
exts_w_reg16_p:
set_grs_a5a5
set_ccr_zero
;; exts.w rn16
mov.b #1, r0l
exts.w r0
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 0xa5a50001 er0 ; result of sign extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
exts_w_reg16_n:
set_grs_a5a5
set_ccr_zero
;; exts.w rn16
mov.b #0xff, r0l
exts.w r0
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 0xa5a5ffff er0 ; result of sign extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
extu_w_reg16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w rn16
mov.b #0xff, r0l
extu.w r0
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 0xa5a500ff er0 ; result of zero extend
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
exts_w_ind_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern
mov.l #pos, er1
exts.w @er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswindp
fail
.Lswindp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_ind_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern
mov.l #neg, er1
exts.w @er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswindn
fail
.Lswindn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_ind_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern
mov.l #neg, er1
extu.w @er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwindn
fail
.Luwindn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_postinc_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern+
mov.l #pos, er1
exts.w @er1+
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpostincp
fail
.Lswpostincp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_postinc_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern+
mov.l #neg, er1
exts.w @er1+
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg+2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpostincn
fail
.Lswpostincn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_postinc_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern+
mov.l #neg, er1
extu.w @er1+
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg+2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpostincn
fail
.Luwpostincn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_postdec_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern-
mov.l #pos, er1
exts.w @er1-
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpostdecp
fail
.Lswpostdecp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_postdec_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @ern-
mov.l #neg, er1
exts.w @er1-
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg-2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpostdecn
fail
.Lswpostdecn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_postdec_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @ern-
mov.l #neg, er1
extu.w @er1-
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-2 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpostdecn
fail
.Luwpostdecn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_preinc_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @+ern
mov.l #pos-2, er1
exts.w @+er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpreincp
fail
.Lswpreincp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_preinc_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @+ern
mov.l #neg-2, er1
exts.w @+er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpreincn
fail
.Lswpreincn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_preinc_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @+ern
mov.l #neg-2, er1
extu.w @+er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpreincn
fail
.Luwpreincn:
;; Note: leave the value as 0x0080, like it started out.
exts_w_predec_p:
set_grs_a5a5
set_ccr_zero
;; exts.w @-ern
mov.l #pos+2, er1
exts.w @-er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 pos er1 ; er1 still contains target address plus 2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0001, @pos
beq .Lswpredecp
fail
.Lswpredecp:
mov.w #0xff01, @pos ; Restore initial value
exts_w_predec_n:
set_grs_a5a5
set_ccr_zero
;; exts.w @-ern
mov.l #neg+2, er1
exts.w @-er1
;; Test ccr H=0 N=1 Z=0 V=0 C=0
test_neg_set
test_zero_clear
test_ovf_clear
test_carry_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0xff80, @neg
beq .Lswpredecn
fail
.Lswpredecn:
;; Note: leave the value as 0xff80, so that extu has work to do.
extu_w_predec_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @-ern
mov.l #neg+2, er1
extu.w @-er1
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwpredecn
fail
.Luwpredecn:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp2_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:2, ern)
mov.l #neg-1, er1
extu.w @(1:2, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-1 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp2n
fail
.Luwdisp2n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:16, ern)
mov.l #neg-44, er1
extu.w @(44:16, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg-44 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp16n
fail
.Luwdisp16n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_disp32_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @(dd:32, ern)
mov.l #neg+444, er1
extu.w @(-444:32, er1)
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_h_gr32 neg+444 er1 ; er1 still contains target address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwdisp32n
fail
.Luwdisp32n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_abs16_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @aa:16
extu.w @neg:16
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwabs16n
fail
.Luwabs16n:
;; Note: leave the value as 0x0080, like it started out.
extu_w_abs32_n:
set_grs_a5a5
set_ccr_zero
;; extu.w @aa:32
extu.w @neg:32
;; Test ccr H=0 N=0 Z=0 V=0 C=0
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
cmp.w #0x0080, @neg
beq .Luwabs32n
fail
.Luwabs32n:
;; Note: leave the value as 0x0080, like it started out.
.endif
pass
exit 0

117
sim/testsuite/sim/h8300/inc.s Normal file
View File

@ -0,0 +1,117 @@
# Hitachi H8 testcase 'inc, inc.w, inc.l'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
inc_b:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.b Rd
inc.b r0h ; Increment 8-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa6a5 r0 ; inc result: a6|a5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; non-zero means h8300h, s, or sx
inc_w_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.w #1, Rd
inc.w #1, r0 ; Increment 16-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a6 r0 ; inc result: a5|a6
test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_w_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.w #2, Rd
inc.w #2, r0 ; Increment 16-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a7 r0 ; inc result: a5|a7
test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_l_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.l #1, eRd
inc.l #1, er0 ; Increment 32-bit reg by one
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
inc_l_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; inc.l #2, eRd
inc.l #2, er0 ; Increment 32-bit reg by two
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

103
sim/testsuite/sim/h8300/jmp.s Normal file
View File

@ -0,0 +1,103 @@
# Hitachi H8 testcase 'jmp'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if 0 ; this one isn't right -- it's an indirect
jmp_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; jmp @aa:8 ; 8-bit displacement
jmp @@.Ltgt_8:8
fail
.Ltgt_8:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
jmp_24:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; jmp @aa:24 ; 24-bit address
jmp @.Ltgt_24:24
fail
.Ltgt_24:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx
jmp_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; jmp @ern ; register indirect
mov.l #.Ltgt_reg, er5
jmp @er5
fail
.Ltgt_reg:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_h_gr32 .Ltgt_reg er5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx)
jmp_32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; jmp @aa:32 ; 32-bit address
; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing
.word 0x5908
.long .Ltgt_32
fail
.Ltgt_32:
test_cc_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

375
sim/testsuite/sim/h8300/ldc.s Normal file
View File

@ -0,0 +1,375 @@
# Hitachi H8 testcase 'ldc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_pre:
.byte 0
byte_src:
.byte 0xff
byte_post:
.byte 0
start
ldc_imm8_ccr:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr ; set all ccr flags high, immediate operand
bcs .L1 ; carry flag set?
fail
.L1: bvs .L2 ; overflow flag set?
fail
.L2: beq .L3 ; zero flag set?
fail
.L3: bmi .L4 ; neg flag set?
fail
.L4:
ldc #0, ccr ; set all ccr flags low, immediate operand
bcc .L5 ; carry flag clear?
fail
.L5: bvc .L6 ; overflow flag clear?
fail
.L6: bne .L7 ; zero flag clear?
fail
.L7: bpl .L8 ; neg flag clear?
fail
.L8:
test_cc_clear
test_grs_a5a5
ldc_reg8_ccr:
set_grs_a5a5
set_ccr_zero
mov #0xff, r0h
ldc r0h, ccr ; set all ccr flags high, reg operand
bcs .L11 ; carry flag set?
fail
.L11: bvs .L12 ; overflow flag set?
fail
.L12: beq .L13 ; zero flag set?
fail
.L13: bmi .L14 ; neg flag set?
fail
.L14:
mov #0, r0h
ldc r0h, ccr ; set all ccr flags low, reg operand
bcc .L15 ; carry flag clear?
fail
.L15: bvc .L16 ; overflow flag clear?
fail
.L16: bne .L17 ; zero flag clear?
fail
.L17: bpl .L18 ; neg flag clear?
fail
.L18:
test_cc_clear
test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
ldc_imm8_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
ldc #0x87, exr ; set exr to 0x87
stc exr, r0l ; retrieve and check exr value
cmp.b #0x87, r0l
beq .L19
fail
.L19:
test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_reg8_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #0x87, r0h
ldc r0h, exr ; set exr to 0x87
stc exr, r0l ; retrieve and check exr value
cmp.b #0x87, r0l
beq .L21
fail
.L21:
test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs16_ccr:
set_grs_a5a5
set_ccr_zero
ldc @byte_src:16, ccr ; abs16 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs16_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
ldc @byte_src:16, exr ; abs16 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs32_ccr:
set_grs_a5a5
set_ccr_zero
ldc @byte_src:32, ccr ; abs32 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_abs32_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
ldc @byte_src:32, exr ; abs32 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp16_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_pre, er1
ldc @(1:16, er1), ccr ; disp16 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_pre, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp16_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_post, er1
ldc @(-1:16, er1), exr ; disp16 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_post, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp32_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_pre, er1
ldc @(1:32, er1), ccr ; disp32 src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_pre, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_disp32_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_post, er1
ldc @(-1:32, er1), exr ; disp16 src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_post, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_postinc_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_src, er1
ldc @er1+, ccr ; postinc src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_post, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_postinc_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_src, er1
ldc @er1+, exr ; postinc src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_post, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_ind_ccr:
set_grs_a5a5
set_ccr_zero
mov #byte_src, er1
ldc @er1, ccr ; postinc src
stc ccr, r0l ; copy into general reg
test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
test_h_gr32 byte_src, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_ind_exr:
set_grs_a5a5
set_ccr_zero
ldc #0, exr
mov #byte_src, er1
ldc @er1, exr ; postinc src
stc exr, r0l ; copy into general reg
test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
test_h_gr32 byte_src, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
ldc_reg_sbr:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
stc sbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
ldc_reg_vbr:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
stc vbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

263
sim/testsuite/sim/h8300/mac.s Normal file
View File

@ -0,0 +1,263 @@
# Hitachi H8 testcase 'mac'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
src1: .word 0
src2: .word 0
array: .word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
.word 0x7fff
start
.if (sim_cpu)
_clrmac:
set_grs_a5a5
set_ccr_zero
clrmac
test_cc_clear
test_grs_a5a5
;; Now see if the mac is actually clear...
stmac mach, er0
test_zero_set
test_neg_clear
test_ovf_clear
test_h_gr32 0 er0
stmac macl, er1
test_zero_set
test_neg_clear
test_ovf_clear
test_h_gr32 0 er1
ld_stmac:
set_grs_a5a5
sub.l er2, er2
set_ccr_zero
ldmac er1, macl
stmac macl, er2
test_ovf_clear
test_carry_clear
;; neg and zero are undefined
test_h_gr32 0xa5a5a5a5 er2
sub.l er2, er2
set_ccr_zero
ldmac er1, mach
stmac mach, er2
test_ovf_clear
test_carry_clear
;; neg and zero are undefined
test_h_gr32 0x0001a5 er2
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
mac_2x2:
set_grs_a5a5
mov.w #2, r1
mov.w r1, @src1
mov.w #2, r2
mov.w r2, @src2
mov #src1, er1
mov #src2, er2
set_ccr_zero
clrmac
mac @er1+, @er2+
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 src1+2 er1
test_h_gr32 src2+2 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
stmac macl, er0
test_zero_clear
test_neg_clear
test_ovf_clear
test_h_gr32 4 er0
stmac mach, er0
test_zero_clear
test_neg_clear
test_ovf_clear
test_h_gr32 0 er0
mac_same_reg_2x4:
;; Use same reg for src and dst. Should be incremented twice,
;; and fetch values from consecutive locations.
set_grs_a5a5
mov.w #2, r1
mov.w r1, @src1
mov.w #4, r2
mov.w r2, @src2
mov #src1, er1
set_ccr_zero
clrmac
mac @er1+, @er1+ ; same register for src and dst
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 src1+4 er1
test_h_gr32 0xa5a50004 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
stmac macl, er0
test_zero_clear
test_neg_clear
test_ovf_clear
test_h_gr32 8 er0
stmac mach, er0
test_zero_clear
test_neg_clear
test_ovf_clear
test_h_gr32 0 er0
mac_0x0:
set_grs_a5a5
mov.w #0, r1
mov.w r1, @src1
mov.w #0, r2
mov.w r2, @src2
mov #src1, er1
mov #src2, er2
set_ccr_zero
clrmac
mac @er1+, @er2+
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 src1+2 er1
test_h_gr32 src2+2 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
stmac macl, er0
test_zero_set ; zero flag is set
test_neg_clear
test_ovf_clear
test_h_gr32 0 er0 ; result is zero
stmac mach, er0
test_zero_set
test_neg_clear
test_ovf_clear
test_h_gr32 0 er0
mac_neg2x2:
set_grs_a5a5
mov.w #-2, r1
mov.w r1, @src1
mov.w #2, r2
mov.w r2, @src2
mov #src1, er1
mov #src2, er2
set_ccr_zero
clrmac
mac @er1+, @er2+
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 src1+2 er1
test_h_gr32 src2+2 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
stmac macl, er0
test_zero_clear
test_neg_set ; neg flag is set
test_ovf_clear
test_h_gr32 -4 er0 ; result is negative
stmac mach, er0
test_zero_clear
test_neg_set
test_ovf_clear
test_h_gr32 -1 er0 ; negative sign extend
mac_array:
;; Use same reg for src and dst, pointing to an array of shorts
set_grs_a5a5
mov #array, er1
set_ccr_zero
clrmac
mac @er1+, @er1+ ; same register for src and dst
mac @er1+, @er1+ ; repeat 8 times
mac @er1+, @er1+
mac @er1+, @er1+
mac @er1+, @er1+
mac @er1+, @er1+
mac @er1+, @er1+
mac @er1+, @er1+
test_cc_clear
test_h_gr32 0xa5a5a5a5 er0
test_h_gr32 array+32 er1
test_h_gr32 0xa5a5a5a5 er2
test_h_gr32 0xa5a5a5a5 er3
test_h_gr32 0xa5a5a5a5 er4
test_h_gr32 0xa5a5a5a5 er5
test_h_gr32 0xa5a5a5a5 er6
test_h_gr32 0xa5a5a5a5 er7
stmac macl, er0
test_zero_clear
test_neg_clear
test_ovf_clear
test_h_gr32 0xfff80008 er0
stmac mach, er0
test_zero_clear
test_neg_clear
test_ovf_clear
test_h_gr32 1 er0 ; result is greater than 32 bits
.endif
pass
exit 0

1495
sim/testsuite/sim/h8300/mov.b.s Normal file
View File

File diff suppressed because it is too large Load Diff

2160
sim/testsuite/sim/h8300/mov.l.s Normal file
View File

File diff suppressed because it is too large Load Diff

1857
sim/testsuite/sim/h8300/mov.w.s Normal file
View File

File diff suppressed because it is too large Load Diff

129
sim/testsuite/sim/h8300/movmd.s Normal file
View File

@ -0,0 +1,129 @@
# Hitachi H8 testcase 'movmd'
# mach(): h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_src:
.byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
byte_dst:
.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
.align 2
word_src:
.word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
word_dst:
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
.align 4
long_src:
.long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
long_dst:
.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
start
.if (sim_cpu == h8sx)
movmd_b:#
# Byte block transfer
#
set_grs_a5a5
mov #byte_src, er5
mov #byte_dst, er6
mov #10, r4
set_ccr_zero
;; movmd.b
movmd.b
;;; .word 0x7b94
test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 byte_src+10 er5
test_h_gr32 byte_dst+10 er6
test_gr_a5a5 7
#
# Now make sure exactly 10 bytes were transferred.
memcmp byte_src byte_dst 10
cmp.b #0, @byte_dst+10
beq .L0
fail
.L0:
movmd_w:#
# Word block transfer
#
set_grs_a5a5
mov #word_src, er5
mov #word_dst, er6
mov #10, r4
set_ccr_zero
;; movmd.w
movmd.w
;;; .word 0x7ba4
test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 word_src+20 er5
test_h_gr32 word_dst+20 er6
test_gr_a5a5 7
#
# Now make sure exactly 20 bytes were transferred.
memcmp word_src word_dst 20
cmp.w #0, @word_dst+20
beq .L1
fail
.L1:
movmd_l:#
# Long block transfer
#
set_grs_a5a5
mov #long_src, er5
mov #long_dst, er6
mov #10, r4
set_ccr_zero
;; movmd.b
movmd.l
;;; .word 0x7bb4
test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 long_src+40 er5
test_h_gr32 long_dst+40 er6
test_gr_a5a5 7
#
# Now make sure exactly 40 bytes were transferred.
memcmp long_src long_dst 40
cmp.l #0, @long_dst+40
beq .L2
fail
.L2:
.endif
pass
exit 0

100
sim/testsuite/sim/h8300/movsd.s Normal file
View File

@ -0,0 +1,100 @@
# Hitachi H8 testcase 'movsd'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
src: .byte 'h', 'e', 'l', 'l', 'o', 0
dst1: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
dst2: .byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
start
.if (sim_cpu == h8sx)
movsd_n:#
# In this test, the transfer will stop after n bytes.
#
set_grs_a5a5
mov #src, er5
mov #dst1, er6
mov #4, r4
set_ccr_zero
;; movsd.b disp:16
movsd.b fail1:16
;;; .word 0x7b84
;;; .word 0x02
bra pass1
fail1: fail
pass1: test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50000 er4
test_h_gr32 src+4 er5
test_h_gr32 dst1+4 er6
test_gr_a5a5 7
#
# Now make sure exactly 4 bytes were transferred.
cmp.b @src, @dst1
bne fail1:16
cmp.b @src+1, @dst1+1
bne fail1:16
cmp.b @src+2, @dst1+2
bne fail1:16
cmp.b @src+3, @dst1+3
bne fail1:16
cmp.b @src+4, @dst1+4
beq fail1:16
movsd_s:#
# In this test, the entire null-terminated string is transferred.
#
set_grs_a5a5
mov #src, er5
mov #dst2, er6
mov #8, r4
set_ccr_zero
;; movsd.b disp:16
movsd.b pass2:16
;;; .word 0x7b84
;;; .word 0x10
fail2: fail
pass2: test_cc_clear
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_h_gr32 0xa5a50002 er4
test_h_gr32 src+6 er5
test_h_gr32 dst2+6 er6
test_gr_a5a5 7
#
# Now make sure 5 bytes were transferred, and the 6th is zero.
cmp.b @src, @dst2
bne fail2:16
cmp.b @src+1, @dst2+1
bne fail2:16
cmp.b @src+2, @dst2+2
bne fail2:16
cmp.b @src+3, @dst2+3
bne fail2:16
cmp.b @src+4, @dst2+4
bne fail2:16
cmp.b #0, @dst2+5
bne fail2:16
.endif
pass
exit 0

1022
sim/testsuite/sim/h8300/neg.s Normal file
View File

File diff suppressed because it is too large Load Diff

26
sim/testsuite/sim/h8300/nop.s Normal file
View File

@ -0,0 +1,26 @@
# Hitachi H8 testcase 'nop'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
nop: set_grs_a5a5
set_ccr_zero
nop
test_cc_clear
test_grs_a5a5
pass
exit 0

1009
sim/testsuite/sim/h8300/not.s Normal file
View File

File diff suppressed because it is too large Load Diff

493
sim/testsuite/sim/h8300/or.b.s Normal file
View File

@ -0,0 +1,493 @@
# Hitachi H8 testcase 'or.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# or.b #xx:8, rd ; c rd xxxxxxxx
# or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx
# or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
# or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
# or.b rs, rd ; 1 4 rs rd
# or.b reg8, @erd ; 7 d rd ???? 1 4 rs ????
# or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs
# or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs
# or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs
# or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs
#
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
or_b_imm8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.b #xx:8,Rd
or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5af r0 ; or result: a5 | aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
or_b_imm8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd
mov #byte_dest, er0
or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L1
fail
.L1:
or_b_imm8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd+
mov #byte_dest, er0
or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xc055
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L2
fail
.L2:
or_b_imm8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@eRd-
mov #byte_dest, er0
or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L3
fail
.L3:
or_b_imm8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@+eRd
mov #pre_byte, er0
or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
;;; .word 0x0175
;;; .word 0x6c08
;;; .word 0xc055
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L4
fail
.L4:
or_b_imm8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b #xx:8,@-eRd
mov #post_byte, er0
or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
;;; .word 0x0177
;;; .word 0x6c08
;;; .word 0xc0aa
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 contains destination address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L5
fail
.L5:
.endif
or_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.b Rs,Rd
mov.b #0xaa, r0h
or.b r0h, r0l ; Reg8 src, reg8 dest
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xaaaf r0 ; or result: a5 | aa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
or_b_reg8_rdind:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd ; or reg8 to register indirect
mov #byte_dest, er0
mov #0xaa, r1l
or.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1490
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L6
fail
.L6:
or_b_reg8_rdpostinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment
mov #byte_dest, er0
mov #0x55, r1l
or.b r1l, @er0+ ; reg8 src, reg post-incr dest
;;; .word 0x0179
;;; .word 0x8049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L7
fail
.L7:
or_b_reg8_rdpostdec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement
mov #byte_dest, er0
mov #0xaa, r1l
or.b r1l, @er0- ; reg8 src, reg post-decr dest
;;; .word 0x0179
;;; .word 0xa049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L8
fail
.L8:
or_b_reg8_rdpreinc:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment
mov #pre_byte, er0
mov #0x55, r1l
or.b r1l, @+er0 ; reg8 src, reg pre-incr dest
;;; .word 0x0179
;;; .word 0x9049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xf5, r0l
beq .L9
fail
.L9:
or_b_reg8_rdpredec:
mov #byte_dest, er0
mov.b #0xa5, r1l
mov.b r1l, @er0
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement
mov #post_byte, er0
mov #0xaa, r1l
or.b r1l, @-er0 ; reg8 src, reg pre-decr dest
;;; .word 0x0179
;;; .word 0xb049
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 contains destination address
test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xaf, r0l
beq .L10
fail
.L10:
orc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; orc #xx:8,ccr
test_neg_clear
orc #0x8, ccr ; Immediate 8-bit operand (neg flag)
test_neg_set
test_zero_clear
orc #0x4, ccr ; Immediate 8-bit operand (zero flag)
test_zero_set
test_ovf_clear
orc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_set
test_carry_clear
orc #0x1, ccr ; Immediate 8-bit operand (carry flag)
test_carry_set
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

77
sim/testsuite/sim/h8300/or.l.s Normal file
View File

@ -0,0 +1,77 @@
# Hitachi H8 testcase 'or.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
or_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l #xx:16,Rd
or.l #0xaaaa, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
or_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l #xx:32,Rd
or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
or_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.l Rs,Rd
mov.l #0xaaaaaaaa, er1
or.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

61
sim/testsuite/sim/h8300/or.w.s Normal file
View File

@ -0,0 +1,61 @@
# Hitachi H8 testcase 'or.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
or_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.w #xx:16,Rd
or.w #0xaaaa, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
or_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; or.w Rs,Rd
mov.w #0xaaaa, r1
or.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

1212
sim/testsuite/sim/h8300/rotl.s Normal file
View File

File diff suppressed because it is too large Load Diff

1802
sim/testsuite/sim/h8300/rotr.s Normal file
View File

File diff suppressed because it is too large Load Diff

167
sim/testsuite/sim/h8300/rotxl.s Normal file
View File

@ -0,0 +1,167 @@
# Hitachi H8 testcase 'rotxl'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
rotxl_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.b r0l ; shift left arithmetic by one
;;; .word 0x1208
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
.if (sim_cpu)
test_h_gr32 0xa5a5a54a er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.b #2, r0l ; shift left arithmetic by two
;;; .word 0x1248
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa595 r0 ; 1010 0101 -> 1001 0101
.if (sim_cpu)
test_h_gr32 0xa5a5a595 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; Not available in h8300 mode
rotxl_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.w r0 ; shift left arithmetic by one
;;; .word 0x1210
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
test_h_gr32 0xa5a54b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.w #2, r0 ; shift left arithmetic by two
;;; .word 0x1250
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0x9695 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0101
test_h_gr32 0xa5a59695 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.l er0 ; shift left arithmetic by one
;;; .word 1030
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1010
test_h_gr32 0x4b4b4b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
rotxl_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
rotxl.l #2, er0 ; shift left arithmetic by two
;;; .word 0x1270
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0101
test_h_gr32 0x96969695 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

2002
sim/testsuite/sim/h8300/rotxr.s Normal file
View File

File diff suppressed because it is too large Load Diff

167
sim/testsuite/sim/h8300/shal.s Normal file
View File

@ -0,0 +1,167 @@
# Hitachi H8 testcase 'shal'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
shal_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shal.b r0l ; shift left arithmetic by one
;;; .word 0x1088
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
; test_ovf_clear ; FIXME
test_neg_clear
test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
.if (sim_cpu)
test_h_gr32 0xa5a5a54a er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shal_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shal.b #2, r0l ; shift left arithmetic by two
;;; .word 0x10c8
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
; test_ovf_clear ; FIXME
test_neg_set
test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
.if (sim_cpu)
test_h_gr32 0xa5a5a594 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu) ; Not available in h8300 mode
shal_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shal.w r0 ; shift left arithmetic by one
;;; .word 0x1090
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
; test_ovf_clear ; FIXME
test_neg_clear
test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
test_h_gr32 0xa5a54b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shal_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shal.w #2, r0 ; shift left arithmetic by two
;;; .word 0x10d0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
; test_ovf_clear ; FIXME
test_neg_set
test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
test_h_gr32 0xa5a59694 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shal_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shal.l er0 ; shift left arithmetic by one
;;; .word 10b0
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
; test_ovf_clear ; FIXME
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1010
test_h_gr32 0x4b4b4b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shal_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shal.l #2, er0 ; shift left arithmetic by two
;;; .word 0x10f0
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
; test_ovf_clear ; FIXME
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0100
test_h_gr32 0x96969694 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

2000
sim/testsuite/sim/h8300/shar.s Normal file
View File

File diff suppressed because it is too large Load Diff

308
sim/testsuite/sim/h8300/shll.s Normal file
View File

@ -0,0 +1,308 @@
# Hitachi H8 testcase 'shll'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.data
byte_dest: .byte 0xa5
.align 2
word_dest: .word 0xa5a5
.align 4
long_dest: .long 0xa5a5a5a5
.text
shll_b_reg8_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.b r0l ; shift left logical by one
;;; .word 0x1008
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
.if (sim_cpu)
test_h_gr32 0xa5a5a54a er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_b_reg8_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.b #2, r0l ; shift left logical by two
;;; .word 0x1048
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
.if (sim_cpu)
test_h_gr32 0xa5a5a594 er0
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shll_b_reg8_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.b #4, r0l ; shift left logical by four
;;; .word 0x10a8
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0xa550 r0 ; 1010 0101 -> 0101 0000
test_h_gr32 0xa5a5a550 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; Not available in h8300 mode
shll_w_reg16_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w r0 ; shift left logical by one
;;; .word 0x1010
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
test_h_gr32 0xa5a54b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_w_reg16_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w #2, r0 ; shift left logical by two
;;; .word 0x1050
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
test_h_gr32 0xa5a59694 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shll_w_reg16_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w #4, r0 ; shift left logical by four
;;; .word 0x1020
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
test_h_gr16 0x5a50 r0 ; 1010 0101 1010 0101 -> 0101 1010 0101 0000
test_h_gr32 0xa5a55a50 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_w_reg16_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.w #8, r0 ; shift left logical by eight
;;; .word 0x1060
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa500 r0 ; 1010 0101 1010 0101 -> 1010 0101 0000 0000
test_h_gr32 0xa5a5a500 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
shll_l_reg32_1:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l er0 ; shift left logical by one
;;; .word 1030
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0100 1011 0100 1011 0100 1011 0100 1010
test_h_gr32 0x4b4b4b4a er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_l_reg32_2:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #2, er0 ; shift left logical by two
;;; .word 0x1070
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1001 0110 1001 0110 1001 0110 1001 0100
test_h_gr32 0x96969694 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
shll_l_reg32_4:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #4, er0 ; shift left logical by four
;;; .word 0x1038
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_zero_clear
test_ovf_clear
test_neg_clear
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 0101 1010 0101 1010 0101 1010 0101 0000
test_h_gr32 0x5a5a5a50 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_l_reg32_8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #8, er0 ; shift left logical by eight
;;; .word 0x1078
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
test_h_gr16 0xa500 r0
; 1010 0101 1010 0101 1010 0101 1010 0101
; -> 1010 0101 1010 0101 1010 0101 0000 0000
test_h_gr32 0xa5a5a500 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
shll_l_reg32_16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
shll.l #16, er0 ; shift left logical by sixteen
;;; .word 0x10f8
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
test_zero_clear
test_ovf_clear
test_neg_set
; 1010 0101 1010 0101 1010 0101 1010 0101
;; -> 1010 0101 1010 0101 0000 0000 0000 0000
test_h_gr32 0xa5a50000 er0
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.endif
pass
exit 0

4018
sim/testsuite/sim/h8300/shlr.s Normal file
View File

File diff suppressed because it is too large Load Diff

389
sim/testsuite/sim/h8300/stc.s Normal file
View File

@ -0,0 +1,389 @@
# Hitachi H8 testcase 'stc'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
.data
byte_dest1:
.byte 0
byte_dest2:
.byte 0
byte_dest3:
.byte 0
byte_dest4:
.byte 0
byte_dest5:
.byte 0
byte_dest6:
.byte 0
byte_dest7:
.byte 0
byte_dest8:
.byte 0
byte_dest9:
.byte 0
byte_dest10:
.byte 0
byte_dest11:
.byte 0
byte_dest12:
.byte 0
start
stc_ccr_reg8:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr ; test value
stc ccr, r0h ; copy test value to r0h
test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
.if (sim_cpu) ; h/s/sx
test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
stc_exr_reg8:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr ; set exr to 0x87
stc exr, r0l ; retrieve and check exr value
cmp.b #0x87, r0l
beq .L21
fail
.L21:
test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_abs16:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr
stc ccr, @byte_dest1:16 ; abs16 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_abs16:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr
stc exr, @byte_dest2:16 ; abs16 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_abs32:
set_grs_a5a5
set_ccr_zero
ldc #0xff, ccr
stc ccr, @byte_dest3:32 ; abs32 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_abs32:
set_grs_a5a5
set_ccr_zero
ldc #0x87, exr
stc exr, @byte_dest4:32 ; abs32 dest
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_disp16:
set_grs_a5a5
set_ccr_zero
mov #byte_dest4, er1
ldc #0xff, ccr
stc ccr, @(1:16,er1) ; disp16 dest (5)
test_h_gr32 byte_dest4, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_disp16:
set_grs_a5a5
set_ccr_zero
mov #byte_dest7, er1
ldc #0x87, exr
stc exr, @(-1:16,er1) ; disp16 dest (6)
test_h_gr32 byte_dest7, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_disp32:
set_grs_a5a5
set_ccr_zero
mov #byte_dest6, er1
ldc #0xff, ccr
stc ccr, @(1:32,er1) ; disp32 dest (7)
test_h_gr32 byte_dest6, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_disp32:
set_grs_a5a5
set_ccr_zero
mov #byte_dest9, er1
ldc #0x87, exr
stc exr, @(-1:32,er1) ; disp16 dest (8)
test_h_gr32 byte_dest9, er1 ; er1 still contains address
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_predecr:
set_grs_a5a5
set_ccr_zero
mov #byte_dest10, er1
ldc #0xff, ccr
stc ccr, @-er1 ; predecr dest (9)
test_h_gr32 byte_dest9, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_predecr:
set_grs_a5a5
set_ccr_zero
mov #byte_dest11, er1
ldc #0x87, exr
stc exr, @-er1 ; predecr dest (10)
test_h_gr32 byte_dest10, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_ccr_ind:
set_grs_a5a5
set_ccr_zero
mov #byte_dest11, er1
ldc #0xff, ccr
stc ccr, @er1 ; postinc dest (11)
test_h_gr32 byte_dest11, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_exr_ind:
set_grs_a5a5
set_ccr_zero
mov #byte_dest12, er1
ldc #0x87, exr
stc exr, @er1, exr ; postinc dest (12)
test_h_gr32 byte_dest12, er1 ; er1 still contains address
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
stc_sbr_reg:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, sbr ; set sbr to 0xaaaaaaaa
stc sbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
stc_vbr_reg:
set_grs_a5a5
set_ccr_zero
mov #0xaaaaaaaa, er0
ldc er0, vbr ; set sbr to 0xaaaaaaaa
stc vbr, er1 ; retreive and check sbr value
test_h_gr32 0xaaaaaaaa er1
test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
check_results:
;; Now check results
mov @byte_dest1, r0h
cmp.b #0xff, r0h
beq .L1
fail
.L1: mov @byte_dest2, r0h
cmp.b #0x87, r0h
beq .L2
fail
.L2: mov @byte_dest3, r0h
cmp.b #0xff, r0h
beq .L3
fail
.L3: mov @byte_dest4, r0h
cmp.b #0x87, r0h
beq .L4
fail
.L4: mov @byte_dest5, r0h
cmp.b #0xff, r0h
beq .L5
fail
.L5: mov @byte_dest6, r0h
cmp.b #0x87, r0h
beq .L6
fail
.L6: mov @byte_dest7, r0h
cmp.b #0xff, r0h
beq .L7
fail
.L7: mov @byte_dest8, r0h
cmp.b #0x87, r0h
beq .L8
fail
.L8: mov @byte_dest9, r0h
cmp.b #0xff, r0h
beq .L9
fail
.L9: mov @byte_dest10, r0h
cmp.b #0x87, r0h
beq .L10
fail
.L10: mov @byte_dest11, r0h
cmp.b #0xff, r0h
beq .L11
fail
.L11: mov @byte_dest12, r0h
cmp.b #0x87, r0h
beq .L12
fail
.L12:
.endif
pass
exit 0

289
sim/testsuite/sim/h8300/sub.b.s Normal file
View File

@ -0,0 +1,289 @@
# Hitachi H8 testcase 'sub.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# sub.b #xx:8, rd ; <illegal>
# sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
# sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
# sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
# sub.b rs, rd ; 1 8 rs rd
# sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ????
# sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs
# sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs
#
# Coming soon:
# sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
# sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
# sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs
# sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
.if (0) ; Guess what? Sub.b immediate reg8 is illegal!
sub_b_imm8_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.b #xx:8,Rd
sub.b #5, r0l ; Immediate 8-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu == h8sx)
sub_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b #xx:8,@eRd
mov #byte_dest, er0
sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xa105
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa0, r0l
beq .L1
fail
.L1:
sub_b_imm8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b #xx:8,@eRd+
mov #byte_dest, er0
sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xa105
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte, er0 ; er0 still contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x9b, r0l
beq .L2
fail
.L2:
sub_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b #xx:8,@eRd-
mov #byte_dest, er0
sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xa105
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte, er0 ; er0 still contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x96, r0l
beq .L3
fail
.L3:
.endif
sub_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.b Rs,Rd
mov.b #5, r0h
sub.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x05a0 r0 ; sub result: a5 - 5
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
sub_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b rs8,@eRd ; Subx to register indirect
mov #byte_dest, er0
mov #5, r1l
sub.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1890
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x91, r0l
beq .L4
fail
.L4:
sub_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b rs8,@eRd+ ; Subx to register indirect
mov #byte_dest, er0
mov #5, r1l
sub.b r1l, @er0+ ; reg8 src, reg indirect dest
;;; .word 0x0179
;;; .word 0x8039
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte er0 ; er0 still contains address plus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x8c, r0l
beq .L5
fail
.L5:
sub_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; sub.b rs8,@eRd- ; Subx to register indirect
mov #byte_dest, er0
mov #5, r1l
sub.b r1l, @er0- ; reg8 src, reg indirect dest
;;; .word 0x0179
;;; .word 0xa039
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte er0 ; er0 still contains address minus one
test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the sub to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x87, r0l
beq .L6
fail
.L6:
.endif
pass
exit 0

91
sim/testsuite/sim/h8300/sub.l.s Normal file
View File

@ -0,0 +1,91 @@
# Hitachi H8 testcase 'sub.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ;
sub_l_imm3: ; 3-bit immediate mode only for h8sx
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:3,eRd ; Immediate 3-bit operand
sub.l #7:3, er0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
sub_l_imm16: ; sub immediate 16-bit value
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:16,eRd ; Immediate 16-bit operand
sub.l #0x1111:16, er0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111
test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
sub_l_imm32:
;; sub.l immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.l #xx:32,Rd
sub.l #0x11111111, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
sub.l.reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; add.l Rs,Rd
mov.l #0x11111111, er1
sub.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
test_h_gr32 0x11111111 er1
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

78
sim/testsuite/sim/h8300/sub.w.s Normal file
View File

@ -0,0 +1,78 @@
# Hitachi H8 testcase 'sub.w'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
sub_w_imm3: ; sub.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w #xx:3,Rd ; Immediate 3-bit operand
sub.w #7:3, r0
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7
test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
.if (sim_cpu) ; non-zero means h8300h, s, or sx
sub_w_imm16: ; sub.w immediate not available in h8300 mode.
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w #xx:16,Rd
sub.w #0x111, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
sub.w.reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; sub.w Rs,Rd
mov.w #0x111, r1
sub.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111
test_h_gr16 0x0111 r1
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111
test_h_gr32 0xa5a50111 er1
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

341
sim/testsuite/sim/h8300/testutils.inc Normal file
View File

@ -0,0 +1,341 @@
# Support macros for the Hitachi H8 assembly test cases.
; Set up a minimal machine state
.macro start
.equ h8300, 0
.equ h8300h, 1
.equ h8300s, 2
.equ h8sx, 3
.if (sim_cpu == h8300s)
.h8300s
.else
.if (sim_cpu == h8300h)
.h8300h
.else
.if (sim_cpu == h8sx)
.h8300sx
.endif
.endif
.endif
.text
.align 2
.global _start
_start:
jmp _main
.data
.align 2
.global pass_str
.global fail_str
.global ok_str
.global pass_loc
.global fail_loc
.global ok_loc
pass_str:
.ascii "pass\n"
fail_str:
.ascii "fail\n"
ok_str:
.ascii "ok\n"
pass_loc16:
.word pass_str
pass_loc32:
.long pass_str
fail_loc16:
.word fail_str
fail_loc32:
.long fail_str
ok_loc16:
.word ok_str
ok_loc32:
.long ok_str
.text
.global _write_and_exit
_write_and_exit:
;ssize_t write(int fd, const void *buf, size_t count);
;Integer arguments have to be zero extended.
.if (sim_cpu)
#if __INT_MAX__ == 32767
extu.l er0
#endif
.endif
jsr @@0xc7
mov #0, r0
jmp _exit
.global _exit
_exit:
mov.b r0l, r0h
mov.w #0xdead, r1
mov.w #0xbeef, r2
sleep
.global _main
_main:
.endm
; Exit with an exit code
.macro exit code
mov.w #\code, r0
jmp _exit
.endm
; Output "pass\n"
.macro pass
mov.w #0, r0 ; fd == stdout
.if (sim_cpu == h8300)
mov.w #pass_str, r1 ; buf == "pass\n"
mov.w #5, r2 ; len == 5
.else
mov.l #pass_str, er1 ; buf == "pass\n"
mov.l #5, er2 ; len == 5
.endif
jmp _write_and_exit
.endm
; Output "fail\n"
.macro fail
mov.w #0, r0 ; fd == stdout
.if (sim_cpu == h8300)
mov.w #fail_str, r1 ; buf == "fail\n"
mov.w #5, r2 ; len == 5
.else
mov.l #fail_str, er1 ; buf == "fail\n"
mov.l #5, er2 ; len == 5
.endif
jmp _write_and_exit
.endm
; Load an 8-bit immediate value into a general register
; (reg must be r0l - r7l or r0h - r7h)
.macro mvi_h_gr8 val reg
mov.b #\val, \reg
.endm
; Load a 16-bit immediate value into a general register
; (reg must be r0 - r7)
.macro mvi_h_gr16 val reg
mov.w #\val, \reg
.endm
; Load a 32-bit immediate value into a general register
; (reg must be er0 - er7)
.macro mvi_h_gr32 val reg
mov.l #\val, \reg
.endm
; Test the value of an 8-bit immediate against a general register
; (reg must be r0l - r7l or r0h - r7h)
.macro test_h_gr8 val reg
cmp.b #\val, \reg
beq .Ltest_gr8\@
fail
.Ltest_gr8\@:
.endm
; Test the value of a 16-bit immediate against a general register
; (reg must be r0 - r7)
.macro test_h_gr16 val reg h=h l=l
.if (sim_cpu == h8300)
test_h_gr8 (\val >> 8) \reg\h
test_h_gr8 (\val & 0xff) \reg\l
.else
cmp.w #\val, \reg
beq .Ltest_gr16\@
fail
.Ltest_gr16\@:
.endif
.endm
; Test the value of a 32-bit immediate against a general register
; (reg must be er0 - er7)
.macro test_h_gr32 val reg
cmp.l #\val, \reg
beq .Ltest_gr32\@
fail
.Ltest_gr32\@:
.endm
; Set a general register to the fixed pattern 'a5a5a5a5'
.macro set_gr_a5a5 reg
.if (sim_cpu == 0)
; h8300
mov.w #0xa5a5, r\reg
.else
mov.l #0xa5a5a5a5, er\reg
.endif
.endm
; Set all general registers to the fixed pattern 'a5a5a5a5'
.macro set_grs_a5a5
.if (sim_cpu == 0)
; h8300
mov.w #0xa5a5, r0
mov.w #0xa5a5, r1
mov.w #0xa5a5, r2
mov.w #0xa5a5, r3
mov.w #0xa5a5, r4
mov.w #0xa5a5, r5
mov.w #0xa5a5, r6
mov.w #0xa5a5, r7
.else
mov.l #0xa5a5a5a5, er0
mov.l #0xa5a5a5a5, er1
mov.l #0xa5a5a5a5, er2
mov.l #0xa5a5a5a5, er3
mov.l #0xa5a5a5a5, er4
mov.l #0xa5a5a5a5, er5
mov.l #0xa5a5a5a5, er6
mov.l #0xa5a5a5a5, er7
.endif
.endm
; Test that a general register contains the fixed pattern 'a5a5a5a5'
.macro test_gr_a5a5 reg
.if (sim_cpu == 0)
; h8300
test_h_gr16 0xa5a5 r\reg
.else
test_h_gr32 0xa5a5a5a5 er\reg
.endif
.endm
; Test that all general regs contain the fixed pattern 'a5a5a5a5'
.macro test_grs_a5a5
test_gr_a5a5 0
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endm
; Set condition code register to an explicit value
.macro set_ccr val
ldc #\val, ccr
.endm
; Set all condition code flags to zero
.macro set_ccr_zero
ldc #0, ccr
.endm
; Set carry flag to value
.macro set_carry_flag val
.data
scf\@: .byte 0
.text
mov.b r0l, @scf\@
mov.b #\val:8, r0l
or.b r0l, r0l
beq .Lccf\@ ; clear
stc ccr, r0l ; set
or.b #0x1, r0l
jmp .Lecf\@
.Lccf\@: ; clear
stc ccr, r0l
and.b #0xfe, r0l
.Lecf\@:
ldc r0l, ccr
mov @scf\@, r0l
.endm
; Test that carry flag is clear
.macro test_carry_clear
bcc .Lcc\@
fail ; carry flag not clear
.Lcc\@:
.endm
; Test that carry flag is set
.macro test_carry_set
bcs .Lcs\@
fail ; carry flag not clear
.Lcs\@:
.endm
; Test that overflow flag is clear
.macro test_ovf_clear
bvc .Lvc\@
fail ; overflow flag not clear
.Lvc\@:
.endm
; Test that overflow flag is set
.macro test_ovf_set
bvs .Lvs\@
fail ; overflow flag not clear
.Lvs\@:
.endm
; Test that zero flag is clear
.macro test_zero_clear
bne .Lne\@
fail ; zero flag not clear
.Lne\@:
.endm
; Test that zero flag is set
.macro test_zero_set
beq .Leq\@
fail ; zero flag not clear
.Leq\@:
.endm
; Test that neg flag is clear
.macro test_neg_clear
bpl .Lneg\@
fail ; negative flag not clear
.Lneg\@:
.endm
; Test that neg flag is set
.macro test_neg_set
bmi .Lneg\@
fail ; negative flag not clear
.Lneg\@:
.endm
; Test ccr against an explicit value
.macro test_ccr val
.data
tccr\@: .byte 0
.text
mov.b r0l, @tccr\@
stc ccr, r0l
cmp.b #\val, r0l
bne .Ltcc\@
fail
.Ltcc\@:
mov.b @tccr\@, r0l
.endm
; Test that all (accessable) condition codes are clear
.macro test_cc_clear
test_carry_clear
test_ovf_clear
test_zero_clear
test_neg_clear
; leaves H, I, U, and UI untested
.endm
; Compare memory, fail if not equal (h8sx only, len > 0).
.macro memcmp src dst len
mov.l #\src, er5
mov.l #\dst, er6
mov.l #\len, er4
.Lmemcmp_\@:
cmp.b @er5+, @er6+
beq .Lmemcmp2_\@
fail
.Lmemcmp2_\@:
dec.l #1, er4
bne .Lmemcmp_\@
.endm

327
sim/testsuite/sim/h8300/xor.b.s Normal file
View File

@ -0,0 +1,327 @@
# Hitachi H8 testcase 'xor.b'
# mach(): all
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
# Instructions tested:
# xor.b #xx:8, rd ; d rd xxxxxxxx
# xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx
# xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx
# xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx
# xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx
# xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx
# xor.b rs, rd ; 1 5 rs rd
# xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ????
# xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs
# xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs
# xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs
# xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs
#
# Coming soon:
# ...
.data
pre_byte: .byte 0
byte_dest: .byte 0xa5
post_byte: .byte 0
start
xor_b_imm8_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.b #xx:8,Rd
xor.b #0xff, r0l ; Immediate 8-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
xor_b_imm8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b #xx:8,@eRd
mov #byte_dest, er0
xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst
;;; .word 0x7d00
;;; .word 0xd0ff
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 byte_dest, er0 ; er0 still contains address
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the xor to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x5a, r0l
beq .L1
fail
.L1:
xor_b_imm8_postinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b #xx:8,@eRd+
mov #byte_dest, er0
xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst
;;; .word 0x0174
;;; .word 0x6c08
;;; .word 0xd0ff
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 post_byte, er0 ; er0 contains address plus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the xor to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L2
fail
.L2:
xor_b_imm8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b #xx:8,@eRd-
mov #byte_dest, er0
xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst
;;; .word 0x0176
;;; .word 0x6c08
;;; .word 0xd0ff
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 pre_byte, er0 ; er0 contains address minus one
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the xor to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x5a, r0l
beq .L3
fail
.L3:
.endif
xor_b_reg8_reg8:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.b Rs,Rd
mov.b #0xff, r0h
xor.b r0h, r0l ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.if (sim_cpu == h8sx)
xor_b_reg8_rdind:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b rs8,@eRd ; xor reg8 to register indirect
mov #byte_dest, er0
mov #0xff, r1l
xor.b r1l, @er0 ; reg8 src, reg indirect dest
;;; .word 0x7d00
;;; .word 0x1590
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 byte_dest er0 ; er0 still contains address
test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L4
fail
.L4:
xor_b_reg8_rdpostinc:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment
mov #byte_dest, er0
mov #0xff, r1l
xor.b r1l, @er0+ ; reg8 src, reg post-increment dest
;;; .word 0x0179
;;; .word 0x8059
test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_clear
test_h_gr32 post_byte er0 ; er0 contains address plus one
test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0x5a, r0l
beq .L5
fail
.L5:
xor_b_reg8_rdpostdec:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement
mov #byte_dest, er0
mov #0xff, r1l
xor.b r1l, @er0- ; reg8 src, reg indirect dest
;;; .word 0x0179
;;; .word 0xa059
test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
test_ovf_clear
test_zero_clear
test_neg_set
test_h_gr32 pre_byte er0 ; er0 contains address minus one
test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
;; Now check the result of the or to memory.
sub.b r0l, r0l
mov.b @byte_dest, r0l
cmp.b #0xa5, r0l
beq .L6
fail
.L6:
xorc_imm8_ccr:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
set_ccr_zero
;; xorc #xx:8,ccr
test_neg_clear
xorc #0x8, ccr ; Immediate 8-bit operand (neg flag)
test_neg_set
xorc #0x8, ccr
test_neg_clear
test_zero_clear
xorc #0x4, ccr ; Immediate 8-bit operand (zero flag)
test_zero_set
xorc #0x4, ccr
test_zero_clear
test_ovf_clear
xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
test_ovf_set
xorc #0x2, ccr
test_ovf_clear
test_carry_clear
xorc #0x1, ccr ; Immediate 8-bit operand (carry flag)
test_carry_set
xorc #0x1, ccr
test_carry_clear
test_gr_a5a5 0 ; Make sure other general regs not disturbed
test_gr_a5a5 1
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
pass
exit 0

77
sim/testsuite/sim/h8300/xor.l.s Normal file
View File

@ -0,0 +1,77 @@
# Hitachi H8 testcase 'xor.l'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
xor_l_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l #xx:16,Rd
xor.l #0xffff:16, er0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
xor_l_imm32:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l #xx:32,Rd
xor.l #0xffffffff, er0 ; Immediate 32-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
xor_l_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.l Rs,Rd
mov.l #0xffffffff, er1
xor.l er1, er0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff
test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0

61
sim/testsuite/sim/h8300/xor.w.s Normal file
View File

@ -0,0 +1,61 @@
# Hitachi H8 testcase 'xor.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
xor_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w #xx:16,Rd
xor.w #0xffff, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
xor_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w Rs,Rd
mov.w #0xffff, r1
xor.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
test_h_gr16 0xffff r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0