Add support for Intel CET instructions
Support Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (cpu_arch): Add .cet. * doc/c-i386.texi: Document cet. * testsuite/gas/i386/cet-intel.d: New file. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/cet.s: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/x86-64-cet.s: Likewise. * testsuite/gas/i386/i386.exp: Run Intel CET tests. opcodes/ * i386-dis.c (REG_0F1E_MOD_3): New enum. (MOD_0F1E_PREFIX_1): Likewise. (MOD_0F38F5_PREFIX_2): Likewise. (MOD_0F38F6_PREFIX_0): Likewise. (RM_0F1E_MOD_3_REG_7): Likewise. (PREFIX_MOD_0_0F01_REG_5): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. (PREFIX_0F1E): Likewise. (PREFIX_MOD_0_0FAE_REG_5): Likewise. (PREFIX_0F38F5): Likewise. (dis386_twobyte): Use PREFIX_0F1E. (reg_table): Add REG_0F1E_MOD_3. (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update PREFIX_0FAE_REG_6 and PREFIX_0F38F6. (three_byte_table): Use PREFIX_0F38F5. (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and PREFIX_MOD_3_0F01_REG_5_RM_2. * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. (cpu_flags): Add CpuCET. * i386-opc.h (CpuCET): New enum. (CpuUnused): Commented out. (i386_cpu_flags): Add cpucet. * i386-opc.tbl: Add Intel CET instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
parent
1cccfb31f5
commit
603555e563
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@ -1,3 +1,15 @@
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2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (cpu_arch): Add .cet.
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* doc/c-i386.texi: Document cet.
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* testsuite/gas/i386/cet-intel.d: New file.
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* testsuite/gas/i386/cet.d: Likewise.
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* testsuite/gas/i386/cet.s: Likewise.
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* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
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* testsuite/gas/i386/x86-64-cet.d: Likewise.
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* testsuite/gas/i386/x86-64-cet.s: Likewise.
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* testsuite/gas/i386/i386.exp: Run Intel CET tests.
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2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
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@ -978,6 +978,8 @@ static const arch_entry cpu_arch[] =
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CPU_RDPID_FLAGS, 0 },
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{ STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
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CPU_PTWRITE_FLAGS, 0 },
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{ STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
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CPU_CET_FLAGS, 0 },
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};
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static const noarch_entry cpu_noarch[] =
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@ -167,6 +167,7 @@ accept various extension mnemonics. For example,
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@code{sha},
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@code{rdpid},
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@code{ptwrite},
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@code{cet},
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@code{prefetchwt1},
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@code{clflushopt},
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@code{se1},
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@ -1198,6 +1199,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
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@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
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@item @samp{.avx512_vpopcntdq} @tab @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
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@item @samp{.cet}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
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@ -0,0 +1,31 @@
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#source: cet.s
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#as: -J
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#objdump: -dw -Mintel
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#name: i386 CET (Intel mode)
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 0f 01 29 rstorssp QWORD PTR \[ecx\]
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+[a-f0-9]+: 0f 38 f6 04 02 wrssd \[edx\+eax\*1\],eax
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[eax\]
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f 1e c9 rdsspd ecx
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 0f 01 2c 01 rstorssp QWORD PTR \[ecx\+eax\*1\]
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+[a-f0-9]+: 0f 38 f6 02 wrssd \[edx\],eax
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd \[edi\+ebp\*1\],edx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[eax\]
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy QWORD PTR \[esp\+eax\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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#pass
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@ -0,0 +1,29 @@
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#objdump: -dw
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#name: i386 CET
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.*: file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 0f 01 29 rstorssp \(%ecx\)
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+[a-f0-9]+: 0f 38 f6 04 02 wrssd %eax,\(%edx,%eax,1\)
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%eax\)
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 0f 1e c9 rdsspd %ecx
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 0f 01 2c 01 rstorssp \(%ecx,%eax,1\)
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+[a-f0-9]+: 0f 38 f6 02 wrssd %eax,\(%edx\)
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+[a-f0-9]+: 66 0f 38 f5 14 2f wrussd %edx,\(%edi,%ebp,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%eax\)
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+[a-f0-9]+: f3 0f ae 34 04 clrssbsy \(%esp,%eax,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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#pass
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@ -0,0 +1,25 @@
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# Check CET instructions
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.text
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_start:
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incsspd
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rdsspd %ecx
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savessp
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rstorssp (%ecx)
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wrssd %eax, (%edx, %eax)
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wrussd %edx, (%edi, %ebp)
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setssbsy (%eax)
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clrssbsy (%esp, %eax)
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endbr64
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endbr32
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.intel_syntax noprefix
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incsspd
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rdsspd ecx
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savessp
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rstorssp QWORD PTR [ecx + eax]
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wrssd [edx],eax
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wrussd [edi + ebp],edx
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setssbsy QWORD PTR [eax]
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clrssbsy QWORD PTR [esp + eax]
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endbr64
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endbr32
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@ -382,6 +382,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_list_test "avx512vl-1" "-al"
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run_list_test "avx512vl-2" "-al"
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run_dump_test "fpu-bad"
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run_dump_test "cet"
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run_dump_test "cet-intel"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -799,6 +801,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_list_test "x86-64-avx512vl-1" "-al"
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run_list_test "x86-64-avx512vl-2" "-al"
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run_dump_test "x86-64-opcode-bad"
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run_dump_test "x86-64-cet"
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run_dump_test "x86-64-cet-intel"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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@ -0,0 +1,38 @@
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#source: x86-64-cet.s
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#objdump: -dw -Mintel
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#name: x86-64 CET (Intel mode)
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp QWORD PTR \[r12\]
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+[a-f0-9]+: 41 0f 38 f6 04 24 wrssd \[r12\],eax
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[rax\]
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp QWORD PTR \[r12\]
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+[a-f0-9]+: 41 0f 38 f6 04 24 wrssd \[r12\],eax
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx
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+[a-f0-9]+: f3 0f ae 28 setssbsy QWORD PTR \[rax\]
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\]
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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#pass
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@ -0,0 +1,37 @@
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#objdump: -dw
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#name: x86-64 CET
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd %r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq %rax
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp \(%r12\)
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+[a-f0-9]+: 41 0f 38 f6 04 24 wrssd %eax,\(%r12\)
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq %rdx,\(%rcx,%r15,1\)
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd %eax,\(%r12\)
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq %rcx,\(%rbx,%rax,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%rax\)
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy \(%rsi,%r12,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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+[a-f0-9]+: f3 0f 01 e9 incsspd
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+[a-f0-9]+: f3 48 0f 01 e9 incsspq
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+[a-f0-9]+: f3 41 0f 1e cc rdsspd %r12d
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+[a-f0-9]+: f3 48 0f 1e c8 rdsspq %rax
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+[a-f0-9]+: f3 0f 01 ea savessp
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+[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp \(%r12\)
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+[a-f0-9]+: 41 0f 38 f6 04 24 wrssd %eax,\(%r12\)
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+[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq %rdx,\(%rcx,%r15,1\)
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+[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd %eax,\(%r12\)
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+[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq %rcx,\(%rbx,%rax,1\)
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+[a-f0-9]+: f3 0f ae 28 setssbsy \(%rax\)
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+[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy \(%rsi,%r12,1\)
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+[a-f0-9]+: f3 0f 1e fa endbr64
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+[a-f0-9]+: f3 0f 1e fb endbr32
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#pass
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@ -0,0 +1,33 @@
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# Check 64bit CET instructions
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.text
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_start:
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incsspd
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incsspq
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rdsspd %r12d
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rdsspq %rax
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savessp
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rstorssp (%r12)
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wrssd %eax, (%r12)
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wrssq %rdx, (%rcx, %r15)
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wrussd %eax, (%r12)
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wrussq %rcx, (%rbx, %rax)
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setssbsy (%rax)
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clrssbsy (%rsi, %r12)
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endbr64
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endbr32
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.intel_syntax noprefix
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incsspd
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incsspq
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rdsspd r12d
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rdsspq rax
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savessp
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rstorssp QWORD PTR [r12]
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wrssd [r12],eax
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wrssq [rcx+r15],rdx
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wrussd [r12],eax
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wrussq [rbx+rax],rcx
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setssbsy QWORD PTR [rax]
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clrssbsy QWORD PTR [rsi+r12]
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endbr64
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endbr32
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@ -1,3 +1,37 @@
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2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (REG_0F1E_MOD_3): New enum.
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(MOD_0F1E_PREFIX_1): Likewise.
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(MOD_0F38F5_PREFIX_2): Likewise.
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(MOD_0F38F6_PREFIX_0): Likewise.
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(RM_0F1E_MOD_3_REG_7): Likewise.
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(PREFIX_MOD_0_0F01_REG_5): Likewise.
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(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
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(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
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(PREFIX_0F1E): Likewise.
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(PREFIX_MOD_0_0FAE_REG_5): Likewise.
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(PREFIX_0F38F5): Likewise.
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(dis386_twobyte): Use PREFIX_0F1E.
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(reg_table): Add REG_0F1E_MOD_3.
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(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
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PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
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PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
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PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
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(three_byte_table): Use PREFIX_0F38F5.
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(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
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Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
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(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
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RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
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PREFIX_MOD_3_0F01_REG_5_RM_2.
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* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
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(cpu_flags): Add CpuCET.
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* i386-opc.h (CpuCET): New enum.
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(CpuUnused): Commented out.
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(i386_cpu_flags): Add cpucet.
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* i386-opc.tbl: Add Intel CET instructions.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
|
||||
|
||||
2017-03-06 Alan Modra <amodra@gmail.com>
|
||||
|
||||
PR 21124
|
||||
|
|
|
@ -723,6 +723,7 @@ enum
|
|||
REG_0F01,
|
||||
REG_0F0D,
|
||||
REG_0F18,
|
||||
REG_0F1E_MOD_3,
|
||||
REG_0F71,
|
||||
REG_0F72,
|
||||
REG_0F73,
|
||||
|
@ -776,6 +777,7 @@ enum
|
|||
MOD_0F1A_PREFIX_0,
|
||||
MOD_0F1B_PREFIX_0,
|
||||
MOD_0F1B_PREFIX_1,
|
||||
MOD_0F1E_PREFIX_1,
|
||||
MOD_0F24,
|
||||
MOD_0F26,
|
||||
MOD_0F2B_PREFIX_0,
|
||||
|
@ -814,6 +816,8 @@ enum
|
|||
MOD_0FE7_PREFIX_2,
|
||||
MOD_0FF0_PREFIX_3,
|
||||
MOD_0F382A_PREFIX_2,
|
||||
MOD_0F38F5_PREFIX_2,
|
||||
MOD_0F38F6_PREFIX_0,
|
||||
MOD_62_32BIT,
|
||||
MOD_C4_32BIT,
|
||||
MOD_C5_32BIT,
|
||||
|
@ -933,6 +937,7 @@ enum
|
|||
RM_0F01_REG_3,
|
||||
RM_0F01_REG_5,
|
||||
RM_0F01_REG_7,
|
||||
RM_0F1E_MOD_3_REG_7,
|
||||
RM_0FAE_REG_5,
|
||||
RM_0FAE_REG_6,
|
||||
RM_0FAE_REG_7
|
||||
|
@ -941,12 +946,16 @@ enum
|
|||
enum
|
||||
{
|
||||
PREFIX_90 = 0,
|
||||
PREFIX_MOD_0_0F01_REG_5,
|
||||
PREFIX_MOD_3_0F01_REG_5_RM_1,
|
||||
PREFIX_MOD_3_0F01_REG_5_RM_2,
|
||||
PREFIX_0F10,
|
||||
PREFIX_0F11,
|
||||
PREFIX_0F12,
|
||||
PREFIX_0F16,
|
||||
PREFIX_0F1A,
|
||||
PREFIX_0F1B,
|
||||
PREFIX_0F1E,
|
||||
PREFIX_0F2A,
|
||||
PREFIX_0F2B,
|
||||
PREFIX_0F2C,
|
||||
|
@ -985,6 +994,7 @@ enum
|
|||
PREFIX_0FAE_REG_3,
|
||||
PREFIX_MOD_0_0FAE_REG_4,
|
||||
PREFIX_MOD_3_0FAE_REG_4,
|
||||
PREFIX_MOD_0_0FAE_REG_5,
|
||||
PREFIX_0FAE_REG_6,
|
||||
PREFIX_0FAE_REG_7,
|
||||
PREFIX_0FB8,
|
||||
|
@ -1048,6 +1058,7 @@ enum
|
|||
PREFIX_0F38DF,
|
||||
PREFIX_0F38F0,
|
||||
PREFIX_0F38F1,
|
||||
PREFIX_0F38F5,
|
||||
PREFIX_0F38F6,
|
||||
PREFIX_0F3A08,
|
||||
PREFIX_0F3A09,
|
||||
|
@ -2839,7 +2850,7 @@ static const struct dis386 dis386_twobyte[] = {
|
|||
{ PREFIX_TABLE (PREFIX_0F1B) },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ PREFIX_TABLE (PREFIX_0F1E) },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
/* 20 */
|
||||
{ "movZ", { Rm, Cm }, 0 },
|
||||
|
@ -3589,6 +3600,17 @@ static const struct dis386 reg_table[][8] = {
|
|||
{ MOD_TABLE (MOD_0F18_REG_6) },
|
||||
{ MOD_TABLE (MOD_0F18_REG_7) },
|
||||
},
|
||||
/* REG_0F1E_MOD_3 */
|
||||
{
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "rdsspK", { Rdq }, PREFIX_OPCODE },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ RM_TABLE (RM_0F1E_MOD_3_REG_7) },
|
||||
},
|
||||
/* REG_0F71 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
@ -3758,6 +3780,24 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
|
||||
},
|
||||
|
||||
/* PREFIX_MOD_0_0F01_REG_5 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "rstorssp", { Mq }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_MOD_3_0F01_REG_5_RM_1 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "incsspK", { Skip_MODRM }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_MOD_3_0F01_REG_5_RM_2 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "savessp", { Skip_MODRM }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F10 */
|
||||
{
|
||||
{ "movups", { XM, EXx }, PREFIX_OPCODE },
|
||||
|
@ -3805,6 +3845,14 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "bndcn", { Gbnd, Ev_bnd }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_0F1E */
|
||||
{
|
||||
{ "nopQ", { Ev }, PREFIX_OPCODE },
|
||||
{ MOD_TABLE (MOD_0F1E_PREFIX_1) },
|
||||
{ "nopQ", { Ev }, PREFIX_OPCODE },
|
||||
{ "nopQ", { Ev }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F2A */
|
||||
{
|
||||
{ "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
|
||||
|
@ -4080,11 +4128,17 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "ptwrite%LQ", { Edq }, 0 },
|
||||
},
|
||||
|
||||
/* PREFIX_MOD_0_0FAE_REG_5 */
|
||||
{
|
||||
{ "xrstor", { FXSAVE }, PREFIX_OPCODE },
|
||||
{ "setssbsy", { Mq }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0FAE_REG_6 */
|
||||
{
|
||||
{ "xsaveopt", { FXSAVE }, 0 },
|
||||
{ Bad_Opcode },
|
||||
{ "clwb", { Mb }, 0 },
|
||||
{ "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
|
||||
{ "clrssbsy", { Mq }, PREFIX_OPCODE },
|
||||
{ "clwb", { Mb }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0FAE_REG_7 */
|
||||
|
@ -4513,9 +4567,16 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{ "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
|
||||
},
|
||||
|
||||
/* PREFIX_0F38F6 */
|
||||
/* PREFIX_0F38F5 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ MOD_TABLE (MOD_0F38F5_PREFIX_2) },
|
||||
},
|
||||
|
||||
/* PREFIX_0F38F6 */
|
||||
{
|
||||
{ MOD_TABLE (MOD_0F38F6_PREFIX_0) },
|
||||
{ "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
|
||||
{ "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
|
||||
{ Bad_Opcode },
|
||||
|
@ -7246,7 +7307,7 @@ static const struct dis386 three_byte_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_0F38F5) },
|
||||
{ PREFIX_TABLE (PREFIX_0F38F6) },
|
||||
{ Bad_Opcode },
|
||||
/* f8 */
|
||||
|
@ -11406,7 +11467,7 @@ static const struct dis386 mod_table[][2] = {
|
|||
},
|
||||
{
|
||||
/* MOD_0F01_REG_5 */
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
|
||||
{ RM_TABLE (RM_0F01_REG_5) },
|
||||
},
|
||||
{
|
||||
|
@ -11479,6 +11540,11 @@ static const struct dis386 mod_table[][2] = {
|
|||
{ "bndmk", { Gbnd, Ev_bnd }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
},
|
||||
{
|
||||
/* MOD_0F1E_PREFIX_1 */
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ REG_TABLE (REG_0F1E_MOD_3) },
|
||||
},
|
||||
{
|
||||
/* MOD_0F24 */
|
||||
{ Bad_Opcode },
|
||||
|
@ -11587,7 +11653,7 @@ static const struct dis386 mod_table[][2] = {
|
|||
},
|
||||
{
|
||||
/* MOD_0FAE_REG_5 */
|
||||
{ "xrstor", { FXSAVE }, 0 },
|
||||
{ PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
|
||||
{ RM_TABLE (RM_0FAE_REG_5) },
|
||||
},
|
||||
{
|
||||
|
@ -11655,6 +11721,14 @@ static const struct dis386 mod_table[][2] = {
|
|||
/* MOD_0F382A_PREFIX_2 */
|
||||
{ "movntdqa", { XM, Mx }, 0 },
|
||||
},
|
||||
{
|
||||
/* MOD_0F38F5_PREFIX_2 */
|
||||
{ "wrussK", { M, Gdq }, PREFIX_OPCODE },
|
||||
},
|
||||
{
|
||||
/* MOD_0F38F6_PREFIX_0 */
|
||||
{ "wrssK", { M, Gdq }, PREFIX_OPCODE },
|
||||
},
|
||||
{
|
||||
/* MOD_62_32BIT */
|
||||
{ "bound{S|}", { Gv, Ma }, 0 },
|
||||
|
@ -12157,8 +12231,8 @@ static const struct dis386 rm_table[][8] = {
|
|||
{
|
||||
/* RM_0F01_REG_5 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1) },
|
||||
{ PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
@ -12173,6 +12247,17 @@ static const struct dis386 rm_table[][8] = {
|
|||
{ "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
|
||||
{ "clzero", { Skip_MODRM }, 0 },
|
||||
},
|
||||
{
|
||||
/* RM_0F1E_MOD_3_REG_7 */
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
|
||||
{ "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
{ "nopQ", { Ev }, 0 },
|
||||
},
|
||||
{
|
||||
/* RM_0FAE_REG_5 */
|
||||
{ "lfence", { Skip_MODRM }, 0 },
|
||||
|
|
|
@ -263,6 +263,8 @@ static initializer cpu_flag_init[] =
|
|||
"CpuRDPID" },
|
||||
{ "CPU_PTWRITE_FLAGS",
|
||||
"CpuPTWRITE" },
|
||||
{ "CPU_CET_FLAGS",
|
||||
"CpuCET" },
|
||||
{ "CPU_ANY_X87_FLAGS",
|
||||
"CPU_ANY_287_FLAGS|Cpu8087" },
|
||||
{ "CPU_ANY_287_FLAGS",
|
||||
|
@ -524,6 +526,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuOSPKE),
|
||||
BITFIELD (CpuRDPID),
|
||||
BITFIELD (CpuPTWRITE),
|
||||
BITFIELD (CpuCET),
|
||||
BITFIELD (CpuRegMMX),
|
||||
BITFIELD (CpuRegXMM),
|
||||
BITFIELD (CpuRegYMM),
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -37,7 +37,7 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -100,133 +100,133 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ZNVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -282,49 +282,49 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -359,35 +359,35 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -457,7 +457,7 @@
|
|||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BMI2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -506,14 +506,14 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -534,7 +534,7 @@
|
|||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -548,112 +548,112 @@
|
|||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512F_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512CD_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512ER_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512PF_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512DQ_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512BW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512VL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512IFMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512VBMI_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512_4FMAPS_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512_4VNNIW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512_VPOPCNTDQ_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1 } }
|
||||
|
||||
#define CPU_K1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1 } }
|
||||
|
||||
#define CPU_IAMCU_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -702,7 +702,7 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSHOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -781,6 +781,13 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CET_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_X87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
@ -814,7 +821,7 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
|
@ -877,7 +884,7 @@
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
|
||||
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX512CD_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
|
|
@ -208,6 +208,8 @@ enum
|
|||
CpuRDPID,
|
||||
/* PTWRITE instruction required */
|
||||
CpuPTWRITE,
|
||||
/* CET instruction support required */
|
||||
CpuCET,
|
||||
/* MMX register support required */
|
||||
CpuRegMMX,
|
||||
/* XMM register support required */
|
||||
|
@ -233,7 +235,9 @@ enum
|
|||
|
||||
/* If you get a compiler error for zero width of the unused field,
|
||||
comment it out. */
|
||||
#if 0
|
||||
#define CpuUnused (CpuMax + 1)
|
||||
#endif
|
||||
|
||||
/* We can check if an instruction is available with array instead
|
||||
of bitfield. */
|
||||
|
@ -329,6 +333,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuospke:1;
|
||||
unsigned int cpurdpid:1;
|
||||
unsigned int cpuptwrite:1;
|
||||
unsigned int cpucet:1;
|
||||
unsigned int cpuregmmx:1;
|
||||
unsigned int cpuregxmm:1;
|
||||
unsigned int cpuregymm:1;
|
||||
|
|
|
@ -5996,3 +5996,22 @@ rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_
|
|||
ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
||||
// PTWRITE instructions end.
|
||||
|
||||
// CET instructions.
|
||||
|
||||
incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 }
|
||||
rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
|
||||
rdsspq, 1, 0xf30f1e, 0x1, 2, CpuRDPID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
|
||||
savessp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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rstorssp, 1, 0xf30f01, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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wrussd, 2, 0x660f38f5, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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wrussq, 2, 0x660f38f5, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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setssbsy, 1, 0xf30fae, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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clrssbsy, 1, 0xf30fae, 0x6, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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endbr64, 0, 0xf30f1efa, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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endbr32, 0, 0xf30f1efb, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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// CET instructions end.
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Load Diff
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Reference in New Issue