Fix powerpc testsuite source errors
PR 21118 work exposed these errors in the testsuite. * testsuite/gas/ppc/cell.s: Correct invalid registers. * testsuite/gas/ppc/vle-simple-1.s: Likewise. * testsuite/gas/ppc/vle-simple-2.s: Likewise.
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@ -1,3 +1,9 @@
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2017-02-14 Alan Modra <amodra@gmail.com>
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* testsuite/gas/ppc/cell.s: Correct invalid registers.
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* testsuite/gas/ppc/vle-simple-1.s: Likewise.
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* testsuite/gas/ppc/vle-simple-2.s: Likewise.
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2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
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2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
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* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
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@ -1,21 +1,21 @@
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.text
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.text
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lvlx %r0, %r1, %r2
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lvlx %v0, %r1, %r2
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lvlx %r0, 0, %r2
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lvlx %v0, 0, %r2
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lvlxl %r0, %r1, %r2
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lvlxl %v0, %r1, %r2
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lvlxl %r0, 0, %r2
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lvlxl %v0, 0, %r2
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lvrx %r0, %r1, %r2
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lvrx %v0, %r1, %r2
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lvrx %r0, 0, %r2
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lvrx %v0, 0, %r2
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lvrxl %r0, %r1, %r2
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lvrxl %v0, %r1, %r2
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lvrxl %r0, 0, %r2
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lvrxl %v0, 0, %r2
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stvlx %r0, %r1, %r2
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stvlx %v0, %r1, %r2
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stvlx %r0, 0, %r2
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stvlx %v0, 0, %r2
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stvlxl %r0, %r1, %r2
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stvlxl %v0, %r1, %r2
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stvlxl %r0, 0, %r2
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stvlxl %v0, 0, %r2
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stvrx %r0, %r1, %r2
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stvrx %v0, %r1, %r2
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stvrx %r0, 0, %r2
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stvrx %v0, 0, %r2
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stvrxl %r0, %r1, %r2
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stvrxl %v0, %r1, %r2
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stvrxl %r0, 0, %r2
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stvrxl %v0, 0, %r2
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ldbrx %r0, 0, %r1
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ldbrx %r0, 0, %r1
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ldbrx %r0, %r1, %r2
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ldbrx %r0, %r1, %r2
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@ -4,7 +4,7 @@ target0:
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se_beq target3
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se_beq target3
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target1:
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target1:
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se_bf cr1, target4
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se_bf gt, target4
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target2:
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target2:
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se_bge target2
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se_bge target2
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@ -29,6 +29,6 @@ target8:
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se_bso target8
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se_bso target8
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target9:
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target9:
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se_bt cr2, target6
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se_bt eq, target6
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se_bun target9
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se_bun target9
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@ -13,10 +13,10 @@ target1:
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target2:
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target2:
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e_beql cr0, target1
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e_beql cr0, target1
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e_beql target6
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e_beql target6
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e_bf cr1, target3
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e_bf 4*cr0+gt, target3
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target3:
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target3:
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e_bfl cr3, target0
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e_bfl cr0*4+un, target0
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e_bge cr1, target1
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e_bge cr1, target1
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e_bge target5
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e_bge target5
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@ -69,8 +69,8 @@ target8:
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target9:
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target9:
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e_bsol cr0, target8
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e_bsol cr0, target8
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e_bsol target8
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e_bsol target8
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e_bt cr1, target7
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e_bt gt+cr0*4, target7
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e_btl cr0, target5
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e_btl lt+4*cr0, target5
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e_bun cr1, target4
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e_bun cr1, target4
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e_bun target4
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e_bun target4
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e_bunl cr2, target0
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e_bunl cr2, target0
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