* simops.c: "add imm,sp" does not effect the condition codes.
"inc dn" does effect the condition codes. Just something I noticed.
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@ -1,3 +1,8 @@
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Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: "add imm,sp" does not effect the condition codes.
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"inc dn" does effect the condition codes.
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Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
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Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
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* simops.c: Treat both operands as signed values for
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* simops.c: Treat both operands as signed values for
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@ -1148,16 +1148,6 @@ void OP_F8FE00 ()
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imm = SEXT8 (insn & 0xff);
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imm = SEXT8 (insn & 0xff);
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value = reg1 + imm;
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value = reg1 + imm;
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State.regs[REG_SP] = value;
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State.regs[REG_SP] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((reg1 & 0x80000000) != (imm & 0x80000000)
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&& (reg1 & 0x80000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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}
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/* add imm16,sp */
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/* add imm16,sp */
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@ -1170,16 +1160,6 @@ void OP_FAFE0000 ()
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imm = SEXT16 (insn & 0xffff);
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imm = SEXT16 (insn & 0xffff);
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value = reg1 + imm;
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value = reg1 + imm;
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State.regs[REG_SP] = value;
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State.regs[REG_SP] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((reg1 & 0x80000000) != (imm & 0x80000000)
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&& (reg1 & 0x80000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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}
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/* add imm32, sp */
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/* add imm32, sp */
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@ -1192,16 +1172,6 @@ void OP_FCFE0000 ()
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imm = ((insn & 0xffff) << 16) | extension;
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imm = ((insn & 0xffff) << 16) | extension;
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value = reg1 + imm;
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value = reg1 + imm;
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State.regs[REG_SP] = value;
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State.regs[REG_SP] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < imm);
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v = ((reg1 & 0x80000000) != (imm & 0x80000000)
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&& (reg1 & 0x80000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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}
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/* addc dm,dn */
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/* addc dm,dn */
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@ -1453,7 +1423,21 @@ void OP_F270 ()
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/* inc dn */
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/* inc dn */
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void OP_40 ()
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void OP_40 ()
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{
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{
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State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
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int z,n,c,v;
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unsigned int value;
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value = State.regs[REG_D0 + ((insn & 0xc) >> 2)] + 1;
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State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
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z = (value == 0);
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n = (value & 0x80000000);
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c = (reg1 < reg2);
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v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
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&& (reg2 & 0x80000000) != (value & 0x80000000));
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PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
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PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
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| (c ? PSW_C : 0) | (v ? PSW_V : 0));
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}
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}
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/* inc an */
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/* inc an */
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