* gencode.c: Add tx49 configury and insns.
* configure.in: Add tx49 configury. * configure: Update.
This commit is contained in:
Gavin Romig-Koch
parent
01b9cd49ca
commit
6205f37913
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@ -119,6 +119,36 @@ else
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fi
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tx49_files="ChangeLog configure.in configure gencode.c"
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if ( echo $* | grep keep\-tx49 > /dev/null ) ; then
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for i in $tx49_files ; do
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if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Keeping tx49 stuff in $i
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fi
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fi
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done
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else
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for i in * ; do
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if test ! -d $i && (grep sanitize-tx49 $i > /dev/null) ; then
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if [ -n "${verbose}" ] ; then
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echo Removing traces of \"tx49\" from $i...
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fi
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cp $i new
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sed '/start\-sanitize\-tx49/,/end-\sanitize\-tx49/d' < $i > new
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if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
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if [ -n "${verbose}" ] ; then
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echo Caching $i in .Recover...
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fi
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mv $i .Recover
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fi
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mv new $i
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fi
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done
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fi
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vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen"
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if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
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@ -1,3 +1,11 @@
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start-sanitize-tx49
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Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
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* gencode.c: Add tx49 configury and insns.
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* configure.in: Add tx49 configury.
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* configure: Update.
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end-sanitize-tx49
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Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen:
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@ -1599,6 +1599,9 @@ case "${target}" in
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# start-sanitize-tx19
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mipstx19*-*-*) SIMCONF="-mips1 -mcpu=r1900 -mno-fp --warnings";;
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# end-sanitize-tx19
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# start-sanitize-tx49
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mips64tx49*-*-*) SIMCONF="-mips3 --warnings -mcpu=r4900";;
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# end-sanitize-tx49
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# start-sanitize-r5900
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mips64r59*-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";;
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# end-sanitize-r5900
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@ -1804,17 +1807,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h
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do
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ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
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echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
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echo "configure:1808: checking for $ac_hdr" >&5
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echo "configure:1811: checking for $ac_hdr" >&5
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if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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else
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cat > conftest.$ac_ext <<EOF
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#line 1813 "configure"
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#line 1816 "configure"
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#include "confdefs.h"
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#include <$ac_hdr>
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:1818: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:1821: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out`
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if test -z "$ac_err"; then
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rm -rf conftest*
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@ -1841,7 +1844,7 @@ fi
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done
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echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
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echo "configure:1845: checking for fabs in -lm" >&5
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echo "configure:1848: checking for fabs in -lm" >&5
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ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
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if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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@ -1849,7 +1852,7 @@ else
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ac_save_LIBS="$LIBS"
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LIBS="-lm $LIBS"
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cat > conftest.$ac_ext <<EOF
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#line 1853 "configure"
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#line 1856 "configure"
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#include "confdefs.h"
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/* Override any gcc2 internal prototype to avoid an error. */
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/* We use char because int might match the return type of a gcc2
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@ -1860,7 +1863,7 @@ int main() {
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fabs()
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; return 0; }
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EOF
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if { (eval echo configure:1864: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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if { (eval echo configure:1867: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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rm -rf conftest*
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eval "ac_cv_lib_$ac_lib_var=yes"
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else
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@ -1890,12 +1893,12 @@ fi
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for ac_func in aint anint sqrt
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do
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echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
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echo "configure:1894: checking for $ac_func" >&5
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echo "configure:1897: checking for $ac_func" >&5
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if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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else
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cat > conftest.$ac_ext <<EOF
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#line 1899 "configure"
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#line 1902 "configure"
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#include "confdefs.h"
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/* System header to define __stub macros and hopefully few prototypes,
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which can conflict with char $ac_func(); below. */
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@ -1918,7 +1921,7 @@ $ac_func();
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; return 0; }
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EOF
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if { (eval echo configure:1922: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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if { (eval echo configure:1925: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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rm -rf conftest*
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eval "ac_cv_func_$ac_func=yes"
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else
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@ -17,6 +17,9 @@ case "${target}" in
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# start-sanitize-tx19
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mipstx19*-*-*) SIMCONF="-mips1 -mcpu=r1900 -mno-fp --warnings";;
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# end-sanitize-tx19
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# start-sanitize-tx49
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mips64tx49*-*-*) SIMCONF="-mips3 --warnings -mcpu=r4900";;
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# end-sanitize-tx49
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# start-sanitize-r5900
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mips64r59*-*-*) SIMCONF="-mips3 --warnings -mcpu=r5900";;
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# end-sanitize-r5900
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@ -480,6 +480,10 @@ typedef struct instruction {
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#define ARCH_R5900 ((unsigned)1 << 30) /* Toshiba r5900 extension instructions */
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/* end-sanitize-r5900 */
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#define ARCH_R3900 ((unsigned)1 << 29) /* Toshiba r3900 (tx39) */
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/* start-sanitize-tx49 */
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#define ARCH_R4900 ((unsigned)1 << 28) /* Toshiba r4900 (tx49) */
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/* end-sanitize-tx49 */
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/* start-sanitize-tx19 */
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/* The r1900 (tx19) is a tx39 with a mips16 decoder. For the purposes
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of implementing the simulator we treat them as the same. */
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@ -488,6 +492,9 @@ typedef struct instruction {
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/* A list (or'ed) of extension insn sets that can be requested independant of the ISA# */
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#define MASK_ISA_INDEP (0 \
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| ARCH_R3900 \
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/* start-sanitize-tx49 */ \
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| ARCH_R4900 \
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/* end-sanitize-tx49 */ \
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/* start-sanitize-r5900 */ \
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| ARCH_R5900 \
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/* end-sanitize-r5900 */ \
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@ -516,6 +523,9 @@ typedef struct instruction {
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#define G5 (0 \
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| ARCH_R3900 \
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/* start-sanitize-tx49 */ \
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| ARCH_R4900 \
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/* end-sanitize-tx49 */ \
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/* start-sanitize-r5900 */ \
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| ARCH_R5900 \
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/* end-sanitize-r5900 */ \
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@ -523,7 +533,27 @@ typedef struct instruction {
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#define G6 (3 | ARCH_R3900)
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#define T3 ARCH_R3900
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#define G7 (ARCH_R3900 \
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/* start-sanitize-tx49 */ \
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| ARCH_R4900 \
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/* end-sanitize-tx49 */ \
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)
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#define G8 (4 \
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/* start-sanitize-tx49 */ \
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| ARCH_R4900 \
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/* end-sanitize-tx49 */ \
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/* start-sanitize-r5900 */ \
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| ARCH_R5900 \
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/* end-sanitize-r5900 */ \
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)
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#define G9 (3 \
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/* start-sanitize-tx49 */ \
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| ARCH_R4900 \
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/* end-sanitize-tx49 */ \
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)
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/* start-sanitize-r5900 */
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#define T5 ARCH_R5900
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/* end-sanitize-r5900 */
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@ -588,8 +618,9 @@ struct instruction MIPS_DECODE[] = {
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{"DIVU1", T5,"011100sssssggggg0000000000011011",MMINORM,DIV, (WORD | WORD32 | UNSIGNED | SIGNEXTEND | HI | LO | PIPE1)},
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/* end-sanitize-r5900 */
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{"DMADD16",G1,"000000sssssggggg0000000000101001",SPECIAL,MADD16, (DOUBLEWORD | HI | LO)},
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{"DMULT", 3,"000000sssssggggg0000000000011100",SPECIAL,MUL, (DOUBLEWORD | HI | LO)},
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{"DMULTU", 3,"000000sssssggggg0000000000011101",SPECIAL,MUL, (DOUBLEWORD | UNSIGNED | HI | LO)},
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/* See note near MULT for explanation of 3op-ness. */
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{"DMULT", G9,"000000sssssgggggddddd00000011100",SPECIAL,MUL, (OP3 | DOUBLEWORD | HI | LO)},
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{"DMULTU", G9,"000000sssssgggggddddd00000011101",SPECIAL,MUL, (OP3 | DOUBLEWORD | UNSIGNED | HI | LO)},
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{"DMxC1", 3,"01000100x01kkkkkvvvvv00000000000",COP1S, FPMOVEC, (FP | DOUBLEWORD)},
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{"DSLL", 3,"00000000000gggggdddddaaaaa111000",SPECIAL,SHIFT, (DOUBLEWORD | LEFT | LOGICAL)},
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{"DSLLV", 3,"000000sssssgggggddddd00000010100",SPECIAL,SHIFT, (DOUBLEWORD | LEFT | LOGICAL | REG)},
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@ -671,6 +702,10 @@ struct instruction MIPS_DECODE[] = {
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{"MSUB.D", G3,"010011bbbbbkkkkkvvvvvrrrrr101001",COP1X, FPSUB, (FP | MULTIPLY | DOUBLE)},
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{"MSUB.S", G3,"010011bbbbbkkkkkvvvvvrrrrr101000",COP1X, FPSUB, (FP | MULTIPLY | SINGLE)},
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{"MUL", 1,"01000110mmmkkkkkvvvvvrrrrr000010",COP1, FPMUL, (FP | HI | LO)},
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/* The 3op version of MULT and MULTU are TX39 (and related chips) specific.
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They should be removed from other chips sets, so that using the 3op opcode
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causes a reserved instruction exception, but gencode can't deal with
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that currently. */
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{"MULT", 1,"000000sssssgggggddddd00000011000",SPECIAL,MUL, (OP3 | WORD | WORD32 | HI | LO)},
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/* start-sanitize-r5900 */
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{"MULT1", T5,"011100sssssgggggddddd00000011000",MMINORM,MUL, (OP3 | WORD | WORD32 | HI | LO | PIPE1)},
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@ -811,7 +846,7 @@ struct instruction MIPS_DECODE[] = {
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{"PXOR", T5,"011100SSSSSTTTTTddddd10011001001",MMI2, POP, (POP_XOR)},
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/* end-sanitize-r5900 */
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{"PREF", G2,"110011sssssnnnnnyyyyyyyyyyyyyyyy",NORMAL, PREFETCH, (NONE)},
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{"PREF", G8,"110011sssssnnnnnyyyyyyyyyyyyyyyy",NORMAL, PREFETCH, (NONE)},
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{"PREFX", 4,"010011sssssgggggvvvvv00000001111",COP1X, FPPREFX, (FP)},
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/* start-sanitize-r5900 */
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@ -827,7 +862,7 @@ struct instruction MIPS_DECODE[] = {
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{"SCD", 3,"111100sssssgggggeeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD | ATOMIC)},
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{"SD", 3,"111111sssssgggggeeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD)},
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{"SDC1", 2,"111101sssssttttteeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD | COPROC)},
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{"SDBBP", T3,"000000????????????????????001110",SPECIAL,SDBBP, (NOARG)},
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{"SDBBP", G7,"000000????????????????????001110",SPECIAL,SDBBP, (NOARG)},
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{"SDC2", 2,"111110sssssttttteeeeeeeeeeeeeeee",NORMAL, STORE, (DOUBLEWORD | COPROC)},
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{"SDL", 3,"101100sssssgggggyyyyyyyyyyyyyyyy",NORMAL, STORE, (DOUBLEWORD | LEFT)},
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{"SDR", 3,"101101sssssgggggyyyyyyyyyyyyyyyy",NORMAL, STORE, (DOUBLEWORD | RIGHT)},
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@ -946,7 +981,7 @@ static const struct instruction MIPS16_DECODE[] = {
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{"NOT", 1, "11101dddyyy01111Z", RR, OR, NOT },
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{"OR", 1, "11101wwwyyy01101", RR, OR, NONE },
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{"SB", 1, "11000xxxyyy55555", RRI, STORE, BYTE },
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{"SDBBP", T3, "11100??????00001", RR, SDBBP, NOARG },
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{"SDBBP", G7, "11100??????00001", RR, SDBBP, NOARG },
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{"SD", 3, "01111xxxyyyDDDDD", RRI, STORE, DOUBLEWORD },
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{"SDSP", 3, "11111001yyyDDDDDs", RI64, STORE, DOUBLEWORD },
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{"SDRASP", 3, "11111010CCCCCCCCsQ", I64, STORE, DOUBLEWORD },
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@ -4429,6 +4464,9 @@ struct architectures {
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static const struct architectures available_architectures[] = {
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{"4100",ARCH_VR4100}, /* NEC MIPS VR4100 */
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{"3900",ARCH_R3900}, /* Toshiba R3900 (TX39) */
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/* start-sanitize-tx49 */
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{"4900",ARCH_R4900}, /* Toshiba R4900 (TX49) */
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/* end-sanitize-tx49 */
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/* start-sanitize-tx19 */
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{"1900",ARCH_R3900}, /* Toshiba R1900 (TX19) */
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/* end-sanitize-tx19 */
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