2010-12-23 Yao Qi <yao@codesourcery.com>
* arm-tdep.c (thumb_analyze_prologue): Move some code ... (EXTRACT_MOVW_MOVT_IMM_T): ... here. New macro. (EXTRACT_MOVW_MOVT_IMM_A): New macro. (arm_analyze_load_stack_chk_guard): New. (arm_skip_stack_protector): New. (arm_skip_prologue): Adjust post_prologue_pc by arm_skip_stack_protector.
This commit is contained in:
Yao Qi
parent
81ec3cceb2
commit
621c6d5b11
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@ -1,3 +1,13 @@
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2010-12-23 Yao Qi <yao@codesourcery.com>
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* arm-tdep.c (thumb_analyze_prologue): Move some code ...
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(EXTRACT_MOVW_MOVT_IMM_T): ... here. New macro.
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(EXTRACT_MOVW_MOVT_IMM_A): New macro.
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(arm_analyze_load_stack_chk_guard): New.
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(arm_skip_stack_protector): New.
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(arm_skip_prologue): Adjust post_prologue_pc by
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arm_skip_stack_protector.
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2010-12-23 Joel Brobecker <brobecker@adacore.com>
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* mi/mi-main.c (mi_cmd_remove_inferior): Use _() marker for error
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208
gdb/arm-tdep.c
208
gdb/arm-tdep.c
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@ -496,6 +496,21 @@ skip_prologue_function (CORE_ADDR pc)
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#define BranchDest(addr,instr) \
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((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
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/* Extract the immediate from instruction movw/movt of encoding T. INSN1 is
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the first 16-bit of instruction, and INSN2 is the second 16-bit of
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instruction. */
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#define EXTRACT_MOVW_MOVT_IMM_T(insn1, insn2) \
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((bits ((insn1), 0, 3) << 12) \
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| (bits ((insn1), 10, 10) << 11) \
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| (bits ((insn2), 12, 14) << 8) \
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| bits ((insn2), 0, 7))
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/* Extract the immediate from instruction movw/movt of encoding A. INSN is
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the 32-bit instruction. */
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#define EXTRACT_MOVW_MOVT_IMM_A(insn) \
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((bits ((insn), 16, 19) << 12) \
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| bits ((insn), 0, 11))
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/* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
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static unsigned int
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@ -1004,10 +1019,8 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
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{
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unsigned int imm = ((bits (insn, 0, 3) << 12)
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| (bits (insn, 10, 10) << 11)
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| (bits (inst2, 12, 14) << 8)
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| bits (inst2, 0, 7));
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unsigned int imm
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= EXTRACT_MOVW_MOVT_IMM_T (insn, inst2);
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regs[bits (inst2, 8, 11)] = pv_constant (imm);
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}
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@ -1130,6 +1143,188 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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return unrecognized_pc;
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}
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/* Try to analyze the instructions starting from PC, which load symbol
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__stack_chk_guard. Return the address of instruction after loading this
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symbol, set the dest register number to *BASEREG, and set the size of
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instructions for loading symbol in OFFSET. Return 0 if instructions are
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not recognized. */
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static CORE_ADDR
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arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch,
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unsigned int *destreg, int *offset)
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{
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enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
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int is_thumb = arm_pc_is_thumb (gdbarch, pc);
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unsigned int low, high, address;
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address = 0;
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if (is_thumb)
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{
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unsigned short insn1
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= read_memory_unsigned_integer (pc, 2, byte_order_for_code);
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if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
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{
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*destreg = bits (insn1, 8, 10);
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*offset = 2;
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address = bits (insn1, 0, 7);
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}
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else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
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{
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unsigned short insn2
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= read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
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low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
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insn1
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= read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
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insn2
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= read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
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/* movt Rd, #const */
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if ((insn1 & 0xfbc0) == 0xf2c0)
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{
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high = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
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*destreg = bits (insn2, 8, 11);
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*offset = 8;
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address = (high << 16 | low);
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}
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}
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}
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else
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{
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unsigned int insn
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= read_memory_unsigned_integer (pc, 4, byte_order_for_code);
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if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */
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{
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address = bits (insn, 0, 11);
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*destreg = bits (insn, 12, 15);
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*offset = 4;
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}
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else if ((insn & 0x0ff00000) == 0x03000000) /* movw Rd, #const */
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{
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low = EXTRACT_MOVW_MOVT_IMM_A (insn);
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insn
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= read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
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if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
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high = EXTRACT_MOVW_MOVT_IMM_A (insn);
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address = (high << 16 | low);
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*destreg = bits (insn, 12, 15);
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*offset = 8;
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}
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}
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return address;
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}
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/* Try to skip a sequence of instructions used for stack protector. If PC
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points to the first instruction of this sequence, return the address of first
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instruction after this sequence, otherwise, return original PC.
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On arm, this sequence of instructions is composed of mainly three steps,
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Step 1: load symbol __stack_chk_guard,
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Step 2: load from address of __stack_chk_guard,
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Step 3: store it to somewhere else.
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Usually, instructions on step 2 and step 3 are the same on various ARM
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architectures. On step 2, it is one instruction 'ldr Rx, [Rn, #0]', and
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on step 3, it is also one instruction 'str Rx, [r7, #immd]'. However,
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instructions in step 1 vary from different ARM architectures. On ARMv7,
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they are,
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movw Rn, #:lower16:__stack_chk_guard
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movt Rn, #:upper16:__stack_chk_guard
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On ARMv5t, it is,
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ldr Rn, .Label
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....
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.Lable:
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.word __stack_chk_guard
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Since ldr/str is a very popular instruction, we can't use them as
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'fingerprint' or 'signature' of stack protector sequence. Here we choose
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sequence {movw/movt, ldr}/ldr/str plus symbol __stack_chk_guard, if not
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stripped, as the 'fingerprint' of a stack protector cdoe sequence. */
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static CORE_ADDR
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arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch)
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{
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enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
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unsigned int address, basereg;
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struct minimal_symbol *stack_chk_guard;
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int offset;
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int is_thumb = arm_pc_is_thumb (gdbarch, pc);
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CORE_ADDR addr;
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/* Try to parse the instructions in Step 1. */
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addr = arm_analyze_load_stack_chk_guard (pc, gdbarch,
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&basereg, &offset);
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if (!addr)
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return pc;
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stack_chk_guard = lookup_minimal_symbol_by_pc (addr);
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/* If name of symbol doesn't start with '__stack_chk_guard', this
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instruction sequence is not for stack protector. If symbol is
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removed, we conservatively think this sequence is for stack protector. */
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if (stack_chk_guard
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&& strcmp (SYMBOL_LINKAGE_NAME(stack_chk_guard), "__stack_chk_guard"))
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return pc;
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if (is_thumb)
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{
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unsigned int destreg;
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unsigned short insn
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= read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
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/* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
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if ((insn & 0xf800) != 0x6800)
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return pc;
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if (bits (insn, 3, 5) != basereg)
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return pc;
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destreg = bits (insn, 0, 2);
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insn = read_memory_unsigned_integer (pc + offset + 2, 2,
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byte_order_for_code);
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/* Step 3: str Rd, [Rn, #immed], encoding T1. */
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if ((insn & 0xf800) != 0x6000)
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return pc;
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if (destreg != bits (insn, 0, 2))
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return pc;
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}
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else
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{
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unsigned int destreg;
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unsigned int insn
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= read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
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/* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
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if ((insn & 0x0e500000) != 0x04100000)
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return pc;
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if (bits (insn, 16, 19) != basereg)
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return pc;
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destreg = bits (insn, 12, 15);
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/* Step 3: str Rd, [Rn, #immed], encoding A1. */
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insn = read_memory_unsigned_integer (pc + offset + 4,
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4, byte_order_for_code);
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if ((insn & 0x0e500000) != 0x04000000)
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return pc;
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if (bits (insn, 12, 15) != destreg)
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return pc;
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}
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/* The size of total two instructions ldr/str is 4 on Thumb-2, while 8
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on arm. */
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if (is_thumb)
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return pc + offset + 4;
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else
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return pc + offset + 8;
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}
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/* Advance the PC across any function entry prologue instructions to
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reach some "real" code.
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@ -1163,6 +1358,11 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
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= skip_prologue_using_sal (gdbarch, func_addr);
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struct symtab *s = find_pc_symtab (func_addr);
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if (post_prologue_pc)
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post_prologue_pc
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= arm_skip_stack_protector (post_prologue_pc, gdbarch);
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/* GCC always emits a line note before the prologue and another
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one after, even if the two are at the same address or on the
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same line. Take advantage of this so that we do not need to
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