checkpoint
This commit is contained in:
Steve Chamberlain
parent
c4413e2c9b
commit
62b66d6df1
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@ -1,3 +1,3 @@
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# Target: H8300 with HMS monitor and H8 simulator
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TDEPFILES= exec.o h8300-tdep.o remote-hms.o remote-sim.o ../h8300sim/code.o
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TDEPFILES= exec.o h8300-tdep.o remote-hms.o remote-sim.o ../h8300sim/code.o ../h8300sim/perifs.o
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TM_FILE= tm-h8300.h
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@ -793,7 +793,7 @@ static char *
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get_reg_name (regno)
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int regno;
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{
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static char *rn[NUM_REGS] = REGISTER_NAMES;
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static char *rn[] = REGISTER_NAMES;
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return rn[regno];
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}
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@ -1217,6 +1217,7 @@ hms_read_inferior_memory (memaddr, myaddr, len)
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}
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}
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expect("emory>");
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hms_write_cr (" ");
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expect_prompt ();
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return len;
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@ -102,8 +102,8 @@ UNSIGNED_SHORT(read_memory_integer (read_register (SP_REGNUM), 2))
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#define REGISTER_TYPE unsigned short
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# define NUM_REGS 10
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# define REGISTER_BYTES (10*2)
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# define NUM_REGS 10 /* 20 for fake HW support */
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# define REGISTER_BYTES (NUM_REGS*2)
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/* Index within `registers' of the first byte of the space for
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@ -154,7 +154,8 @@ UNSIGNED_SHORT(read_memory_integer (read_register (SP_REGNUM), 2))
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Entries beyond the first NUM_REGS are ignored. */
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#define REGISTER_NAMES \
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{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp","ccr","pc"}
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{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp",\
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"ccr","pc","cycles","hcheck","tier","tcsr","frc","ocra","ocrb","tcr","tocr","icra"}
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/* Register numbers of various important registers.
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@ -61,8 +61,8 @@ DEP = mkdep
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all: run
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run: code.o run.o
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$(CC) -o run code.o run.o ../bfd/libbfd.a ../libiberty/libiberty.a
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run: code.o run.o perifs.o
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$(CC) -o run code.o perifs.o run.o ../bfd/libbfd.a ../libiberty/libiberty.a
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code.c:p1.c p2.c p3.c
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cat $(VPATH)/p1.c p2.c $(VPATH)/p3.c | cb >code.c
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@ -73,7 +73,7 @@ p2.c:writecode
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writecode:writecode.c
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$(CC_FOR_BUILD) -o writecode -g $(CSEARCH) $(srcdir)/writecode.c
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$(CC) -o writecode -g $(CSEARCH) $(srcdir)/writecode.c
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108
sim/h8300/p1.c
108
sim/h8300/p1.c
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@ -22,41 +22,16 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdio.h>
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#include <stdlib.h>
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#include <signal.h>
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#define SET_WORD_MEM(x,y) {mem[x] = (y)>>8;mem[x+1] = y;}
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#define SET_BYTE_MEM(x,y) mem[x]=y
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#define WORD_MEM(x) ((mem[x]<<8) | (mem[x+1]))
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#define BYTE_MEM(x) mem[x]
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#define PC 9
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#define CCR 8
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struct state
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{
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int cycles;
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unsigned short int reg[10];
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unsigned char *(bregp[16]);
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unsigned char *(bregp_NNNNxxxx[256]);
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unsigned char *(bregp_xxxxNNNN[256]);
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unsigned short int *(wregp_xNNNxxxx[256]);
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unsigned short int *(wregp_xxxxxNNN[256]);
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}
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saved_state;
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#include "state.h"
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#define V (v!=0)
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#define C (c!=0)
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#define N (n!=0)
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#define Z (z!=0)
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#define SET_CCR(x) n = x & 0x8; v = x & 0x2; z = x & 0x4; c = x & 0x1;
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#define GET_CCR() ((N << 3) | (Z<<2) | (V<<1) | C)
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#define SET_CCR(x) n = x & 0x8; v = x & 0x2; z = x & 0x4; c = x & 0x1;saved_state.ienable=x&0x80;
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#define GET_CCR() ((N << 3) | (Z<<2) | (V<<1) | C) | ((!saved_state.ienable)<<7)
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int exception;
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static unsigned char *mem;
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static union
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@ -76,11 +51,11 @@ littleendian;
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static void
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meminit ()
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{
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if (!mem)
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if (!saved_state.mem)
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{
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int tmp;
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mem = calloc (1024, 64);
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saved_state.mem = calloc (1024, 64);
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littleendian.i = 1;
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/* initialze the array of pointers to byte registers */
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for (tmp = 0; tmp < 8; tmp++)
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@ -89,11 +64,15 @@ meminit ()
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{
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saved_state.bregp[tmp] = (unsigned char *) (saved_state.reg + tmp);
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saved_state.bregp[tmp + 8] = saved_state.bregp[tmp] + 1;
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if (HOST_IS_LITTLE_ENDIAN)
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abort();
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}
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else
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{
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saved_state.bregp[tmp + 8] = (unsigned char *) (saved_state.reg + tmp);
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saved_state.bregp[tmp] = saved_state.bregp[tmp + 8] + 1;
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if (!HOST_IS_LITTLE_ENDIAN)
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abort();
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}
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}
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@ -113,7 +92,10 @@ meminit ()
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saved_state.wregp_xxxxxNNN[tmp] = &saved_state.reg[tmp & 0x7];
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}
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saved_state.reg[HCHECK] = 10000000; /* don't check the hardware
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often */
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}
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}
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@ -124,7 +106,7 @@ control_c (sig, code, scp, addr)
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char *scp;
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char *addr;
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{
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exception = SIGINT;
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saved_state.exception = SIGINT;
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}
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void
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@ -151,8 +133,11 @@ sim_write (to, from, len)
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char *from;
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int len;
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{
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int i;
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meminit ();
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memcpy (mem + to, from, len);
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for ( i = 0; i < len; i++)
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SET_BYTE_MEM(to + i, from[i]);
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}
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void
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@ -162,14 +147,46 @@ sim_read (from, to, len)
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int len;
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{
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int i;
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meminit ();
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memcpy (to, mem + from, len);
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for (i = 0; i < len; i++) {
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to[i] = BYTE_MEM(from + i);
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}
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}
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int
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sim_stop_signal ()
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{
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return exception;
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return saved_state.exception;
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}
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void
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load_timer_state_from_mem()
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{
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saved_state.reg[TIER] = BYTE_MEM(0xff90);
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saved_state.reg[TCSR] = BYTE_MEM(0xff91);
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saved_state.reg[FRC] = WORD_MEM(0xff92);
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saved_state.reg[TCR] = BYTE_MEM(0xff96);
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saved_state.reg[TOCR] = BYTE_MEM(0xff97);
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if ((saved_state.reg[TOCR] & OCRS) == 0)
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{
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saved_state.reg[OCRA] = WORD_MEM(0xff94);
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}
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else
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{
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saved_state.reg[OCRB] = WORD_MEM(0xff94);
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}
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}
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void
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store_timer_state_to_mem()
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{
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BYTE_MEM(0xff91) = saved_state.reg[TCSR];
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SET_WORD_MEM(0xff92, saved_state.reg[FRC]);
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}
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void
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@ -181,30 +198,31 @@ int sig;
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int tmp;
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int b0;
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int b1;
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int checkfreq;
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int ni; /* Number of insts to execute before checking hw state */
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unsigned char **blow;
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unsigned char **bhigh;
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unsigned short **wlow;
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unsigned short **whigh;
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unsigned char *npc;
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unsigned short *npc;
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int rn;
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unsigned short int *reg;
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unsigned char **bregp;
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void (*prev) ();
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unsigned char *pc;
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unsigned short *pc;
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int srca;
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int srcb;
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int dst;
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int cycles = saved_state.cycles;
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int cycles ;
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int n;
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int v;
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int z;
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int c;
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SET_CCR (saved_state.reg[CCR]);
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pc = saved_state.reg[PC] + mem;
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/* Set up pointers to areas */
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reg = saved_state.reg;
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bregp = saved_state.bregp;
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blow = saved_state.bregp_xxxxNNNN;
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@ -213,17 +231,21 @@ int sig;
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wlow = saved_state.wregp_xxxxxNNN;
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whigh = saved_state.wregp_xNNNxxxx;
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prev = signal (SIGINT, control_c);
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meminit();
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LOAD_INTERPRETER_STATE();
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if (step)
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exception = SIGTRAP;
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saved_state.exception = SIGTRAP;
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else
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{
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exception = sig;
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saved_state.exception = sig;
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}
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do
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{
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b0 = pc[0];
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b1 = pc[1];
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b1 = pc[0];
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b0 = b1>> 8;
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b1 &= 0xff;
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@ -22,7 +22,7 @@ goto next;
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goto next;
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setflags:;
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SET_CCR(tmp);
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break;
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goto next;
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logflags:
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shiftflags:
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v = 0;
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@ -32,13 +32,20 @@ break;
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goto next;
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next: ;
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pc = npc;
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if (ni > checkfreq)
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{
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ni = 0;
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SAVE_INTERPRETER_STATE();
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perifs();
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LOAD_INTERPRETER_STATE();
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#ifdef __GO32__
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if (kbhit())
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exception = SIGINT;
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if (kbhit())
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saved_state.exception = SIGINT;
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#endif
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} while (!exception);
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saved_state.cycles = cycles;
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saved_state.reg[PC] = pc - mem;
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saved_state.reg[CCR] = GET_CCR();
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}
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ni++;
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} while (!saved_state.exception);
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SAVE_INTERPRETER_STATE();
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}
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@ -0,0 +1,78 @@
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/* Fake peripherals for the H8/330 */
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#include "state.h"
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perifs( )
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/* This routine is called every few instructions to see if some sort
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of hardware event is needed */
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{
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int interrupt = 0;
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int lval;
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int tmp;
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/* What to do about the 16 bit timer */
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/* Free running counter same as reg a */
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if (saved_state.reg[OCRA] == saved_state.reg[FRC])
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{
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/* Set the counter A overflow bit */
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saved_state.reg[TCSR] |= OCFA;
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if (saved_state.reg[TCSR] & CCLRA)
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{
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saved_state.reg[FRC] = 0;
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}
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if (saved_state.reg[TIER] & OCIEA)
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{
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interrupt = 16;
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}
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}
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/* Free running counter same as reg b */
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if (saved_state.reg[OCRB] == saved_state.reg[FRC])
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{
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saved_state.reg[TCSR] |= OCFB;
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if (saved_state.reg[TIER] & OCIEB)
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{
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interrupt = 17;
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}
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}
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/* inc free runnning counter */
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saved_state.reg[FRC]++;
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if (saved_state.reg[FRC] == 0)
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{
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/* Must have overflowed */
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saved_state.reg[TCSR] |= OVF;
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if (BYTE_MEM(TIER) & OVIE)
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interrupt = 18;
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}
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/* If we've had an interrupt and the bit is on */
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if (interrupt && saved_state.ienable)
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{
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int ccr;
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saved_state.ienable = 0;
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ccr = saved_state.reg[CCR];
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lval = WORD_MEM((interrupt)<<1);
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lval = WORD_MEM(lval);
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{
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/* Push PC */
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saved_state.reg[7] -= 2;
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tmp = saved_state.reg[7];
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SET_WORD_MEM (tmp, saved_state.reg[PC]);
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/* Push CCR twice */
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saved_state.reg[7] -=2 ;
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tmp = saved_state.reg[7];
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SET_BYTE_MEM(tmp,ccr);
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SET_BYTE_MEM(tmp+1,ccr);
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/* Set pc to point to first instruction of i vector */
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saved_state.reg[PC] = lval;
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}
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}
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}
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@ -44,21 +44,21 @@ char *nibs[] =
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"(b0&0xf)",
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"((b1>>4)&0xf)",
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"((b1)&0xf)",
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"((pc[2]>>4)&0xf)",
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"((pc[2])&0xf)",
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"((pc[3]>>4)&0xf)",
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"((pc[3])&0xf)",
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"((pc[1]>>12)&0xf)",
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"((pc[1]>>8)&0xf)",
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"((pc[1]>>4)&0xf)",
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"((pc[1])&0xf)",
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0, 0};
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/* how to get at the 3 bit immediate in the instruction */
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char *imm3[] =
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{"foo",
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"foo",
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"((pc[1]>>4)&0x7)",
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"((b1>>4)&0x7)",
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"foo",
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"foo",
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"foo",
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"((pc[3]>>4)&0x7)"};
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"(pc[1]>>4)&0x7"};
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/* How to get at a byte register from an index in the instruction at
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nibble n */
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@ -225,7 +225,7 @@ decode (p, fetch, size)
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case MEMIND:
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if (fetch)
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{
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printf ("lval = ((pc[2]<<8)|pc[3]);\n");
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printf ("lval = pc[1];\n");
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}
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break;
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case RDDEC:
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@ -246,7 +246,7 @@ decode (p, fetch, size)
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break;
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case IMM16:
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if (fetch)
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printf ("srca =( pc[2] << 8) | pc[3];\n");
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printf ("srca =( pc[1]);\n");
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break;
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case ABS8SRC:
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if (fetch)
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@ -276,7 +276,7 @@ decode (p, fetch, size)
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case ABS16SRC:
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if (fetch)
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{
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printf ("lval = ((pc[2] << 8) + pc[3]);\n");
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printf ("lval = pc[1];\n");
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printf ("srca = %s_MEM(lval);\n", size == 8 ? "BYTE" : "WORD");
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}
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break;
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@ -288,14 +288,14 @@ decode (p, fetch, size)
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case DISPSRC:
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if (fetch)
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{
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printf ("lval = 0xffff&((pc[2] << 8) + pc[3] +reg[rn]);\n");
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printf ("lval = 0xffff&(pc[1] +reg[rn]);\n");
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printf ("srca = %s_MEM(lval);\n", size == 8 ? "BYTE" : "WORD");
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}
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break;
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case DISPDST:
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if (fetch)
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{
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printf ("lval = 0xffff&((pc[2] << 8) + pc[3] +reg[rn]);\n");
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printf ("lval = 0xffff&(pc[1] +reg[rn]);\n");
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printf ("srcb = %s_MEM(lval);\n", size == 8 ? "BYTE" : "WORD");
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}
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else
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@ -306,7 +306,7 @@ decode (p, fetch, size)
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case ABS16DST:
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if (fetch)
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{
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printf ("lval = ((pc[2] << 8) + pc[3]);\n");
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printf ("lval = (pc[1]);\n");
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printf ("srcb = %s_MEM(lval);\n", ss);
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}
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else
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|
|
@ -322,7 +322,7 @@ decode (p, fetch, size)
|
|||
default:
|
||||
if (p->data.nib[i] > HexF)
|
||||
{
|
||||
printf ("exception = SIGILL;\n");
|
||||
printf ("saved_state.exception = SIGILL;\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -332,7 +332,7 @@ decode (p, fetch, size)
|
|||
static void
|
||||
esleep ()
|
||||
{
|
||||
printf ("exception = SIGSTOP;\n");
|
||||
printf ("saved_state.exception = SIGSTOP;\n");
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -387,7 +387,7 @@ bra (p, a)
|
|||
struct h8_opcode *p;
|
||||
char *a;
|
||||
{
|
||||
printf ("if (%s) npc += (((char *)pc)[1]);\n", a);
|
||||
printf ("if (%s) npc += ((char )b1)>>1;\n", a);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -397,8 +397,8 @@ bsr (p, a)
|
|||
{
|
||||
printf ("reg[7]-=2;\n");
|
||||
printf ("tmp = reg[7];\n");
|
||||
printf ("SET_WORD_MEM(tmp, npc-mem);\n");
|
||||
printf ("npc += (((char *)pc)[1]);\n");
|
||||
printf ("SET_WORD_MEM(tmp, (npc-saved_state.mem)*2);\n");
|
||||
printf ("npc += (((char *)pc)[1])>>1;\n");
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -425,8 +425,8 @@ jsr (p, a, s)
|
|||
printf ("else {\n");
|
||||
printf ("reg[7]-=2;\n");
|
||||
printf ("tmp = reg[7];\n");
|
||||
printf ("SET_WORD_MEM(tmp, npc-mem);\n");
|
||||
printf ("npc = lval + mem;\n");
|
||||
printf ("SET_WORD_MEM(tmp, (npc-saved_state.mem)*2);\n");
|
||||
printf ("npc = (lval>>1) + saved_state.mem;\n");
|
||||
printf ("}");
|
||||
}
|
||||
|
||||
|
|
@ -436,7 +436,7 @@ jmp (p, a, s)
|
|||
char *a;
|
||||
int s;
|
||||
{
|
||||
printf ("npc = lval + mem;\n");
|
||||
printf ("npc = (lval>>1) + saved_state.mem;\n");
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -447,7 +447,20 @@ rts (p, a, s)
|
|||
{
|
||||
printf ("tmp = reg[7];\n");
|
||||
printf ("reg[7]+=2;\n");
|
||||
printf ("npc = mem + WORD_MEM(tmp);\n");
|
||||
printf ("npc = saved_state.mem + (WORD_MEM(tmp)>>1);\n");
|
||||
}
|
||||
|
||||
static void
|
||||
rte (p, a, s)
|
||||
struct h8_opcode *p;
|
||||
char *a;
|
||||
int s;
|
||||
{
|
||||
printf ("reg[7]+=2;\n");
|
||||
printf ("tmp = reg[7];\n");
|
||||
printf ("reg[7]+=2;\n");
|
||||
printf ("SET_CCR(tmp);\n");
|
||||
printf("npc = saved_state.mem + (WORD_MEM(tmp)>>1);\n");
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -466,7 +479,7 @@ bpt (p, a, s)
|
|||
char *a;
|
||||
int s;
|
||||
{
|
||||
printf ("exception = SIGTRAP;\n");
|
||||
printf ("saved_state.exception = SIGTRAP;\n");
|
||||
printf ("npc = pc;\n");
|
||||
}
|
||||
|
||||
|
|
@ -675,6 +688,7 @@ table [] =
|
|||
{ nx, 1, "jsr", jsr, 0, 0 } ,
|
||||
{ nx, 1, "jmp", jmp, 0, 0 } ,
|
||||
{ nx, 0, "rts", rts, 0, 0 } ,
|
||||
{ nx, 0, "rte", rte, 0, 0 } ,
|
||||
{ nx, 1, "andc", andc, 0, 0 } ,
|
||||
{ sf, 1, "shal", shal, 0, 0 } ,
|
||||
{ sf, 1, "shar", shar, 0, 0 } ,
|
||||
|
|
@ -727,7 +741,7 @@ edo (p)
|
|||
if (table[i].decode)
|
||||
decode (p, 1, table[i].size);
|
||||
printf ("cycles += %d;\n", p->time);
|
||||
printf ("npc = pc + %d;\n", p->length);
|
||||
printf ("npc = pc + %d;\n", p->length/2);
|
||||
table[i].func (p, table[i].arg, table[i].size);
|
||||
if (table[i].decode)
|
||||
decode (p, 0, table[i].size);
|
||||
|
|
@ -740,7 +754,7 @@ edo (p)
|
|||
}
|
||||
}
|
||||
printf ("%s not found %s\n", cs, ce);
|
||||
printf ("exception = SIGILL;\n");
|
||||
printf ("saved_state.exception = SIGILL;\n");
|
||||
printf ("break;\n");
|
||||
}
|
||||
|
||||
|
|
@ -834,10 +848,19 @@ owrite (i)
|
|||
{
|
||||
if (mask0[c] | mask1[c])
|
||||
{
|
||||
int sh;
|
||||
if (needand)
|
||||
printf ("\n&&");
|
||||
printf ("((pc[%d]&0x%02x)==0x%x)",
|
||||
c, mask0[c] | mask1[c], mask1[c]);
|
||||
if (c & 1) sh = 0;else sh = 8;
|
||||
if (c/2 == 0 && sh == 0)
|
||||
printf("((b1&0x%x)==0x%x)", mask0[c]| mask1[c],
|
||||
mask1[c]);
|
||||
else {
|
||||
printf ("((pc[%d]&(0x%02x<<%d))==(0x%x<<%d))",
|
||||
c/2, mask0[c] | mask1[c],sh,
|
||||
mask1[c],sh);
|
||||
}
|
||||
|
||||
needand = 1;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue