* Fixes for PRs 17559, 16602, brought over from sky branch.
start-sanitize-r5900 Fri Oct 23 12:06:00 EDT 1998 Frank Ch. Eigler <fche@cygnus.com> * mips-opc.c (vrget, vclipw, vrnext): Correct COP2 opcodes and masks. end-sanitize-r5900
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@ -1,4 +1,39 @@
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start-sanitize-r5900
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Fri Oct 23 12:06:00 EDT 1998 Frank Ch. Eigler <fche@cygnus.com>
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* mips-opc.c (vrget, vclipw, vrnext): Correct COP2 opcodes
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and masks.
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end-sanitize-r5900
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Mon Oct 19 13:03:19 1998 Doug Evans <devans@seba.cygnus.com>
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start-sanitize-cygnus
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* cgen-asm.in (insert_1): New function.
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(insert_normal): Progress on handling ! CGEN_INT_INSN_P.
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(insert_insn_normal): Update handling of CGEN_INT_INSN_P.
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(@arch@_cgen_assemble_insn): Update type of `buf' arg.
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* cgen-dis.in (extract_1): New function.
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(extract_normal): buf_ctrl renamed to ex_info, update type.
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Progress on handling of CGEN_INT_INSN_P.
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(extract_insn_normal): buf_ctrl renamed to ex_info, update type.
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Update handling of CGEN_INT_INSN_P. Handle errors from
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@arch@_cgen_extract_operand.
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(print_insn): Renamed from print_int_insn. Handle ! CGEN_INT_INSN_P.
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(default_print_insn): Renamed from print_insn.
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Handle ! CGEN_INT_INSN_P.
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(print_insn_@arch@): Handle error returns from print_insn.
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* cgen-opc.in (cgen_get_insn_value, cgen_put_insn_value): New fns.
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(@arch@_cgen_lookup_insn): Update handling of CGEN_INT_INSN_P.
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(@arch@_cgen_lookup_get_insn_operands): Ditto.
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end-sanitize-cygnus
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* m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate.
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start-sanitize-am33
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Wed Oct 14 12:12:25 1998 Jeffrey A Law (law@cygnus.com)
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* m10300-opc.c: Allow autoincrement stores using the same register
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for source and destination operands.
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Mon Oct 12 10:43:51 1998 Jeffrey A Law (law@cygnus.com)
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* m10300-opc.c: DSP instrutions which only write to one general
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@ -172,7 +172,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"vaddaz", "&UK,2K,1#z", 0x4a00003e, 0xfe0007ff, 0, T5},
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{"vcallms","O", 0x4a000038, 0xffe0003f, 0, T5},
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{"vcallmsr", "9", 0x4a00d839, 0xffffffff, 0, T5},
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{"vclip","2", 0x4be001ff, 0xffff07ff, 0, T5},
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{"vclipw","&2K,1#w", 0x4a0001ff, 0xfe0007ff, 0, T5},
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{"vdiv","Q,8,7", 0x4a0003bc, 0xfe0007ff, 0, T5},
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{"vftoi0", "&1K,2K", 0x4a00017c, 0xfe0007ff, 0, T5},
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{"vftoi4", "&1K,2K", 0x4a00017d, 0xfe0007ff, 0, T5},
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@ -258,9 +258,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
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{"vnop","", 0x4a0002ff, 0xffffffff, 0, T5},
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{"vopmula", ";UK,2K,1K", 0x4bc002fe, 0xffe007ff, 0, T5},
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{"vopmsub", ";3K,2K,1K", 0x4bc0002e, 0xffe0003f, 0, T5},
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{"vrget", "&1K,X", 0x4a20043d, 0xfe00ffff, 0, T5},
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{"vrget", "&1K,X", 0x4a00043d, 0xfe00ffff, 0, T5},
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{"vrinit", "X,8", 0x4a00043e, 0xff9f07ff, 0, T5},
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{"vrnext", "&1K,X", 0x4a20043c, 0xfe00ffff, 0, T5},
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{"vrnext", "&1K,X", 0x4a00043c, 0xfe00ffff, 0, T5},
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{"vrsqrt","Q,8,7", 0x4a0003be, 0xfe0007ff, 0, T5},
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{"vrxor", "X,8", 0x4a00043f, 0xff9f07ff, 0, T5},
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{"vsqd", "&2K,(--4)K", 0x4a00037f, 0xfe0007ff, 0, T5},
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