From Jie Zhang <jie.zhang@analog.com>
* config/tc-bfin.h (bfin_anomaly_checks): Declare. (AC_05000074): Define. (ENABLE_AC_05000074): Define. * config/tc-bfin.c (enum bfin_cpu_type): New. (bfin_cpu_t): Typedef. (bfin_cpu_type): Define. (bfin_si_revision): Define. (bfin_anomaly_checks): Define. (struct bfin_cpu): New. (bfin_cpus[]): New. (struct bfin_cpu_isa): Define. (bfin_isa): New global variable. (OPTION_MCPU): Define. (md_longopts[]): Add -mcpu option. (md_parse_option): Deal with -mcpu option and initialize bfin_anomaly_checks. * doc/c-bfin.texi: Rename BFIN to Blackfin throughout. Document -mcpu option. * config/bfin-parse.y (gen_multi_instr_1): Check anomaly 05000074.
This commit is contained in:
Bernd Schmidt
parent
d55cb1c59e
commit
6306cd859b
@ -12,6 +12,27 @@
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decode_dsp32alu_0, decode_dsp32shift_0, decode_dsp32shitimm_0,
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insn_regmask): New functions.
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From Jie Zhang <jie.zhang@analog.com>
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* config/tc-bfin.h (bfin_anomaly_checks): Declare.
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(AC_05000074): Define.
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(ENABLE_AC_05000074): Define.
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* config/tc-bfin.c (enum bfin_cpu_type): New.
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(bfin_cpu_t): Typedef.
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(bfin_cpu_type): Define.
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(bfin_si_revision): Define.
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(bfin_anomaly_checks): Define.
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(struct bfin_cpu): New.
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(bfin_cpus[]): New. (struct bfin_cpu_isa): Define.
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(bfin_isa): New global variable.
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(OPTION_MCPU): Define.
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(md_longopts[]): Add -mcpu option.
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(md_parse_option): Deal with -mcpu option and initialize
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bfin_anomaly_checks.
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* doc/c-bfin.texi: Rename BFIN to Blackfin throughout. Document
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-mcpu option.
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* config/bfin-parse.y (gen_multi_instr_1): Check anomaly
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05000074.
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2009-08-11 Mike Frysinger <vapier@gentoo.org>
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* config/bfin-parse.y (binary): Change "compiler" to "assembler".
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@ -394,6 +394,16 @@ gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
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if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
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yyerror ("resource conflict in multi-issue instruction");
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/* Anomaly 05000074 */
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if (ENABLE_AC_05000074
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&& (dsp32->value & 0xf780) == 0xc680
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&& ((dsp16_grp1->value & 0xfe40) == 0x9240
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|| (dsp16_grp1->value & 0xfe08) == 0xba08
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|| (dsp16_grp1->value & 0xfc00) == 0xbc00))
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yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
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dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
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return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
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}
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@ -305,14 +305,178 @@ const char EXP_CHARS[] = "eE";
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As in 0f12.456 or 0d1.2345e12. */
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const char FLT_CHARS[] = "fFdDxX";
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typedef enum bfin_cpu_type
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{
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BFIN_CPU_UNKNOWN,
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BFIN_CPU_BF512,
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BFIN_CPU_BF514,
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BFIN_CPU_BF516,
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BFIN_CPU_BF518,
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BFIN_CPU_BF522,
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BFIN_CPU_BF523,
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BFIN_CPU_BF524,
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BFIN_CPU_BF525,
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BFIN_CPU_BF526,
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BFIN_CPU_BF527,
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BFIN_CPU_BF531,
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BFIN_CPU_BF532,
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BFIN_CPU_BF533,
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BFIN_CPU_BF534,
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BFIN_CPU_BF536,
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BFIN_CPU_BF537,
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BFIN_CPU_BF538,
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BFIN_CPU_BF539,
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BFIN_CPU_BF542,
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BFIN_CPU_BF542M,
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BFIN_CPU_BF544,
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BFIN_CPU_BF544M,
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BFIN_CPU_BF547,
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BFIN_CPU_BF547M,
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BFIN_CPU_BF548,
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BFIN_CPU_BF548M,
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BFIN_CPU_BF549,
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BFIN_CPU_BF549M,
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BFIN_CPU_BF561
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} bfin_cpu_t;
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bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN;
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/* -msi-revision support. There are three special values:
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-1 -msi-revision=none.
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0xffff -msi-revision=any. */
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int bfin_si_revision;
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unsigned int bfin_anomaly_checks = 0;
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struct bfin_cpu
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{
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const char *name;
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bfin_cpu_t type;
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int si_revision;
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unsigned int anomaly_checks;
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};
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struct bfin_cpu bfin_cpus[] =
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{
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{"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
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{"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
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{"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074},
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{"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074},
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{"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074},
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{"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074},
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{"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074},
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{"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074},
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{"bf522", BFIN_CPU_BF522, 0x0002, AC_05000074},
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{"bf522", BFIN_CPU_BF522, 0x0001, AC_05000074},
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{"bf522", BFIN_CPU_BF522, 0x0000, AC_05000074},
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{"bf523", BFIN_CPU_BF523, 0x0002, AC_05000074},
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{"bf523", BFIN_CPU_BF523, 0x0001, AC_05000074},
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{"bf523", BFIN_CPU_BF523, 0x0000, AC_05000074},
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{"bf524", BFIN_CPU_BF524, 0x0002, AC_05000074},
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{"bf524", BFIN_CPU_BF524, 0x0001, AC_05000074},
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{"bf524", BFIN_CPU_BF524, 0x0000, AC_05000074},
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{"bf525", BFIN_CPU_BF525, 0x0002, AC_05000074},
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{"bf525", BFIN_CPU_BF525, 0x0001, AC_05000074},
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{"bf525", BFIN_CPU_BF525, 0x0000, AC_05000074},
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{"bf526", BFIN_CPU_BF526, 0x0002, AC_05000074},
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{"bf526", BFIN_CPU_BF526, 0x0001, AC_05000074},
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{"bf526", BFIN_CPU_BF526, 0x0000, AC_05000074},
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{"bf527", BFIN_CPU_BF527, 0x0002, AC_05000074},
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{"bf527", BFIN_CPU_BF527, 0x0001, AC_05000074},
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{"bf527", BFIN_CPU_BF527, 0x0000, AC_05000074},
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{"bf531", BFIN_CPU_BF531, 0x0006, AC_05000074},
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{"bf531", BFIN_CPU_BF531, 0x0005, AC_05000074},
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{"bf531", BFIN_CPU_BF531, 0x0004, AC_05000074},
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{"bf531", BFIN_CPU_BF531, 0x0003, AC_05000074},
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{"bf532", BFIN_CPU_BF532, 0x0006, AC_05000074},
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{"bf532", BFIN_CPU_BF532, 0x0005, AC_05000074},
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{"bf532", BFIN_CPU_BF532, 0x0004, AC_05000074},
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{"bf532", BFIN_CPU_BF532, 0x0003, AC_05000074},
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{"bf533", BFIN_CPU_BF533, 0x0006, AC_05000074},
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{"bf533", BFIN_CPU_BF533, 0x0005, AC_05000074},
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{"bf533", BFIN_CPU_BF533, 0x0004, AC_05000074},
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{"bf533", BFIN_CPU_BF533, 0x0003, AC_05000074},
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{"bf534", BFIN_CPU_BF534, 0x0003, AC_05000074},
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{"bf534", BFIN_CPU_BF534, 0x0002, AC_05000074},
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{"bf534", BFIN_CPU_BF534, 0x0001, AC_05000074},
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{"bf536", BFIN_CPU_BF536, 0x0003, AC_05000074},
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{"bf536", BFIN_CPU_BF536, 0x0002, AC_05000074},
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{"bf536", BFIN_CPU_BF536, 0x0001, AC_05000074},
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{"bf537", BFIN_CPU_BF537, 0x0003, AC_05000074},
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{"bf537", BFIN_CPU_BF537, 0x0002, AC_05000074},
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{"bf537", BFIN_CPU_BF537, 0x0001, AC_05000074},
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{"bf538", BFIN_CPU_BF538, 0x0005, AC_05000074},
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{"bf538", BFIN_CPU_BF538, 0x0004, AC_05000074},
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{"bf538", BFIN_CPU_BF538, 0x0003, AC_05000074},
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{"bf538", BFIN_CPU_BF538, 0x0002, AC_05000074},
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{"bf539", BFIN_CPU_BF539, 0x0005, AC_05000074},
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{"bf539", BFIN_CPU_BF539, 0x0004, AC_05000074},
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{"bf539", BFIN_CPU_BF539, 0x0003, AC_05000074},
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{"bf539", BFIN_CPU_BF539, 0x0002, AC_05000074},
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{"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074},
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{"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074},
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{"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074},
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{"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074},
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{"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074},
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{"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074},
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{"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074},
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{"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074},
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{"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074},
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{"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074},
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{"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074},
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{"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074},
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{"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074},
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{"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074},
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{"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074},
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{"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074},
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{"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074},
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{"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074},
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{"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074},
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{"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074},
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{"bf561", BFIN_CPU_BF561, 0x0005, AC_05000074},
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{"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074},
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{"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074},
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{NULL, 0, 0, 0}
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};
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/* Define bfin-specific command-line options (there are none). */
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const char *md_shortopts = "";
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#define OPTION_FDPIC (OPTION_MD_BASE)
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#define OPTION_NOPIC (OPTION_MD_BASE + 1)
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#define OPTION_MCPU (OPTION_MD_BASE + 2)
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struct option md_longopts[] =
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{
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{ "mcpu", required_argument, NULL, OPTION_MCPU },
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{ "mfdpic", no_argument, NULL, OPTION_FDPIC },
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{ "mnopic", no_argument, NULL, OPTION_NOPIC },
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{ "mno-fdpic", no_argument, NULL, OPTION_NOPIC },
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@ -330,6 +494,76 @@ md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
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default:
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return 0;
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case OPTION_MCPU:
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{
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const char *p, *q;
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int i;
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i = 0;
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while ((p = bfin_cpus[i].name) != NULL)
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{
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if (strncmp (arg, p, strlen (p)) == 0)
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break;
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i++;
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}
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if (p == NULL)
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{
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error ("-mcpu=%s is not valid", arg);
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return 0;
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}
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bfin_cpu_type = bfin_cpus[i].type;
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q = arg + strlen (p);
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if (*q == '\0')
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{
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bfin_si_revision = bfin_cpus[i].si_revision;
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bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
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}
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else if (strcmp (q, "-none") == 0)
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bfin_si_revision = -1;
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else if (strcmp (q, "-any") == 0)
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{
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bfin_si_revision = 0xffff;
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while (bfin_cpus[i].type == bfin_cpu_type)
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{
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bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
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i++;
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}
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}
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else
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{
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unsigned int si_major, si_minor;
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int rev_len, n;
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rev_len = strlen (q);
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if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2
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|| n != rev_len
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|| si_major > 0xff || si_minor > 0xff)
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{
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invalid_silicon_revision:
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error ("-mcpu=%s has invalid silicon revision", arg);
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return 0;
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}
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bfin_si_revision = (si_major << 8) | si_minor;
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while (bfin_cpus[i].type == bfin_cpu_type
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&& bfin_cpus[i].si_revision != bfin_si_revision)
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i++;
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if (bfin_cpus[i].type != bfin_cpu_type)
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goto invalid_silicon_revision;
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bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
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}
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break;
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}
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case OPTION_FDPIC:
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bfin_flags |= EF_BFIN_FDPIC;
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bfin_pic_flag = "-mfdpic";
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@ -78,4 +78,10 @@ extern long md_pcrel_from_section (struct fix *, segT);
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/* This target is buggy, and sets fix size too large. */
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#define TC_FX_SIZE_SLACK(FIX) 2
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extern unsigned int bfin_anomaly_checks;
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/* Anomaly checking */
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#define AC_05000074 0x00000001
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#define ENABLE_AC_05000074 (bfin_anomaly_checks & AC_05000074)
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/* end of tc-bfin.h */
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@ -14,14 +14,60 @@
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@cindex Blackfin support
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@menu
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* BFIN Syntax:: BFIN Syntax
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* BFIN Directives:: BFIN Directives
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* Blackfin Options:: Blackfin Options
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* Blackfin Syntax:: Blackfin Syntax
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* Blackfin Directives:: Blackfin Directives
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@end menu
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@node BFIN Syntax
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@node Blackfin Options
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@section Options
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@cindex Blackfin options (none)
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@cindex options for Blackfin (none)
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@table @code
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@cindex @code{-mcpu=} command line option, Blackfin
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@item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]}
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This option specifies the target processor. The optional @var{sirevision}
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is not used in assembler. It's here such that GCC can easily pass down its
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@code{-mcpu=} option. The assembler will issue an
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error message if an attempt is made to assemble an instruction which
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will not execute on the target processor. The following processor names are
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recognized:
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@code{bf522},
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@code{bf523},
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@code{bf524},
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@code{bf525},
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@code{bf526},
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@code{bf527},
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@code{bf531},
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@code{bf532},
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@code{bf533},
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@code{bf534},
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@code{bf535} (not implemented yet),
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@code{bf536},
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@code{bf537},
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@code{bf538},
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@code{bf539},
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@code{bf542},
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@code{bf542m},
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@code{bf544},
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@code{bf544m},
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@code{bf547},
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@code{bf547m},
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@code{bf548},
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@code{bf548m},
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@code{bf549},
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@code{bf549m},
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and
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@code{bf561}.
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@end table
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@node Blackfin Syntax
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@section Syntax
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@cindex BFIN syntax
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@cindex syntax, BFIN
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@cindex Blackfin syntax
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@cindex syntax, Blackfin
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@table @code
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@item Special Characters
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@ -164,10 +210,10 @@ the Blackfin(r) Processor Instruction Set Reference.
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@end table
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@node BFIN Directives
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@node Blackfin Directives
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@section Directives
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@cindex BFIN directives
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@cindex directives, BFIN
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@cindex Blackfin directives
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@cindex directives, Blackfin
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The following directives are provided for compatibility with the VDSP assembler.
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