* gas/ppc/astest.d: Adjust for relocs reduced to section sym.
* gas/ppc/astest2.d: Likewise. * gas/ppc/astest2_64.d: Likewise. * ppc/astest64.d: Likewise. * ppc/booke.d: Likewise. * ppc/power4.d: Likewise. * ppc/test1elf32.d: Likewise. * ppc/test1elf64.d: Likewise.
This commit is contained in:
parent
ab1e9ef77f
commit
632d447c67
|
@ -1,3 +1,14 @@
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2005-03-02 Alan Modra <amodra@bigpond.net.au>
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* gas/ppc/astest.d: Adjust for relocs reduced to section sym.
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* gas/ppc/astest2.d: Likewise.
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* gas/ppc/astest2_64.d: Likewise.
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* ppc/astest64.d: Likewise.
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* ppc/booke.d: Likewise.
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* ppc/power4.d: Likewise.
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* ppc/test1elf32.d: Likewise.
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* ppc/test1elf64.d: Likewise.
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2005-03-02 Jan Beulich <jbeulich@novell.com>
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* gas/i386/cr-err.[ls]: New.
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@ -810,8 +821,8 @@
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* gas/all/altmac2.[sd]: ... to here.
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* gas/all/excl.s: New.
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* gas/all/gas.exp: Suppress both tests for a few targets known to
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break. Run the new (split out) test only when the target doesn't
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use '!' as a comment character.
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break. Run the new (split out) test only when the target doesn't
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use '!' as a comment character.
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2004-08-18 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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@ -1229,10 +1240,10 @@
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* gas/dlx/alltests.exp: Execute new lohi test.
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* gas/dlx/lohi.s: New test for spurious lo16/hi16
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reloc overflow checking.
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reloc overflow checking.
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* gas/dlx/lohi.d: New file: expected output.
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* gas/dlx/lhi.d: Updated to properly expect lo16
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relocations where asked for.
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relocations where asked for.
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* gas/dlx/itype.d: Likewise.
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* gas/dlx/lhi.d: Corrected cut+paste error in test name.
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@ -33,37 +33,41 @@ Disassembly of section \.text:
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38: 48 00 00 00 b 38 <apfour\+0x28>
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38: R_PPC_LOCAL24PC a
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3c: 4b ff ff d4 b 10 <apfour>
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40: 00 00 00 40 \.long 0x40
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40: R_PPC_ADDR32 \.text\+0x40
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44: 00 00 00 4c \.long 0x4c
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44: R_PPC_ADDR32 \.text\+0x4c
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48: 00 00 00 00 \.long 0x0
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48: R_PPC_REL32 x
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4c: 00 00 00 04 \.long 0x4
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4c: R_PPC_REL32 x\+0x4
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\.\.\.
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50: 00 00 00 00 \.long 0x0
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50: R_PPC_REL32 z
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54: R_PPC_REL32 y
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54: 00 00 00 04 \.long 0x4
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54: R_PPC_REL32 \.data\+0x4
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58: 00 00 00 00 \.long 0x0
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58: R_PPC_ADDR32 x
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5c: R_PPC_ADDR32 y
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5c: 00 00 00 04 \.long 0x4
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5c: R_PPC_ADDR32 \.data\+0x4
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60: 00 00 00 00 \.long 0x0
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60: R_PPC_ADDR32 z
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64: ff ff ff fc fnmsub f31,f31,f31,f31
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64: R_PPC_ADDR32 x\+0xf+ffffffc
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68: ff ff ff fc fnmsub f31,f31,f31,f31
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68: R_PPC_ADDR32 y\+0xf+ffffffc
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68: 00 00 00 00 \.long 0x0
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68: R_PPC_ADDR32 \.data
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6c: ff ff ff fc fnmsub f31,f31,f31,f31
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6c: R_PPC_ADDR32 z\+0xf+ffffffc
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70: ff ff ff 9c \.long 0xffffff9c
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74: ff ff ff 9c \.long 0xffffff9c
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\.\.\.
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78: 00 00 00 00 \.long 0x0
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78: R_PPC_ADDR32 a
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7c: R_PPC_ADDR32 b
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80: R_PPC_ADDR32 apfour
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7c: 00 00 00 10 \.long 0x10
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7c: R_PPC_ADDR32 \.text\+0x10
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80: 00 00 00 10 \.long 0x10
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80: R_PPC_ADDR32 \.text\+0x10
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84: ff ff ff fc fnmsub f31,f31,f31,f31
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88: 00 00 00 02 \.long 0x2
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88: R_PPC_ADDR32 apfour\+0x2
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88: 00 00 00 12 \.long 0x12
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88: R_PPC_ADDR32 \.text\+0x12
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8c: 00 00 00 00 \.long 0x0
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Disassembly of section \.data:
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@ -29,26 +29,28 @@ Disassembly of section \.text:
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38: 48 00 00 00 b 38 <foo\+0x38>
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38: R_PPC_LOCAL24PC a
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3c: 48 00 00 40 b 7c <apfour>
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40: 00 00 00 40 \.long 0x40
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40: R_PPC_ADDR32 \.text\+0x40
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44: 00 00 00 4c \.long 0x4c
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44: R_PPC_ADDR32 \.text\+0x4c
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48: 00 00 00 00 \.long 0x0
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48: R_PPC_REL32 x
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4c: 00 00 00 04 \.long 0x4
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4c: R_PPC_REL32 x\+0x4
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\.\.\.
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50: 00 00 00 00 \.long 0x0
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50: R_PPC_REL32 z
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54: R_PPC_REL32 y
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54: 00 00 00 04 \.long 0x4
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54: R_PPC_REL32 \.data\+0x4
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58: 00 00 00 00 \.long 0x0
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58: R_PPC_ADDR32 x
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5c: R_PPC_ADDR32 y
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5c: 00 00 00 04 \.long 0x4
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5c: R_PPC_ADDR32 \.data\+0x4
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60: 00 00 00 00 \.long 0x0
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60: R_PPC_ADDR32 z
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64: ff ff ff fc fnmsub f31,f31,f31,f31
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64: R_PPC_ADDR32 x\+0xf+ffffffc
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68: ff ff ff fc fnmsub f31,f31,f31,f31
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68: R_PPC_ADDR32 y\+0xf+ffffffc
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68: 00 00 00 00 \.long 0x0
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68: R_PPC_ADDR32 \.data
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6c: ff ff ff fc fnmsub f31,f31,f31,f31
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6c: R_PPC_ADDR32 z\+0xf+ffffffc
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70: 00 00 00 08 \.long 0x8
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@ -59,12 +61,13 @@ Disassembly of section \.text:
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78: R_PPC_ADDR32 a
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0+000007c <apfour>:
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\.\.\.
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7c: R_PPC_ADDR32 b
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80: R_PPC_ADDR32 apfour
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7c: 00 00 00 7c \.long 0x7c
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7c: R_PPC_ADDR32 \.text\+0x7c
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80: 00 00 00 7c \.long 0x7c
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80: R_PPC_ADDR32 \.text\+0x7c
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84: ff ff ff fc fnmsub f31,f31,f31,f31
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88: 00 00 00 02 \.long 0x2
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88: R_PPC_ADDR32 apfour\+0x2
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88: 00 00 00 7e \.long 0x7e
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88: R_PPC_ADDR32 \.text\+0x7e
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8c: 00 00 00 00 \.long 0x0
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90: 60 00 00 00 nop
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94: 40 a5 ff fc ble- cr1,90 <apfour\+0x14>
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@ -34,16 +34,20 @@ Disassembly of section \.text:
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40: R_PPC64_REL32 x
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44: 00 00 00 04 \.long 0x4
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44: R_PPC64_REL32 x\+0x4
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\.\.\.
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48: 00 00 00 00 \.long 0x0
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48: R_PPC64_REL32 z
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4c: R_PPC64_REL32 y
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4c: 00 00 00 04 \.long 0x4
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4c: R_PPC64_REL32 \.data\+0x4
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50: 00 00 00 00 \.long 0x0
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50: R_PPC64_ADDR32 x
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54: R_PPC64_ADDR32 y
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54: 00 00 00 04 \.long 0x4
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54: R_PPC64_ADDR32 \.data\+0x4
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58: 00 00 00 00 \.long 0x0
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58: R_PPC64_ADDR32 z
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5c: ff ff ff fc fnmsub f31,f31,f31,f31
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5c: R_PPC64_ADDR32 x\+0xfffffffffffffffc
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60: ff ff ff fc fnmsub f31,f31,f31,f31
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60: R_PPC64_ADDR32 y\+0xfffffffffffffffc
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60: 00 00 00 00 \.long 0x0
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60: R_PPC64_ADDR32 \.data
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64: ff ff ff fc fnmsub f31,f31,f31,f31
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64: R_PPC64_ADDR32 z\+0xfffffffffffffffc
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68: 00 00 00 08 \.long 0x8
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@ -54,12 +58,13 @@ Disassembly of section \.text:
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70: R_PPC64_ADDR32 a
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0000000000000074 <apfour>:
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\.\.\.
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74: R_PPC64_ADDR32 b
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78: R_PPC64_ADDR32 apfour
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74: 00 00 00 74 \.long 0x74
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74: R_PPC64_ADDR32 \.text\+0x74
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78: 00 00 00 74 \.long 0x74
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78: R_PPC64_ADDR32 \.text\+0x74
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7c: ff ff ff fc fnmsub f31,f31,f31,f31
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80: 00 00 00 02 \.long 0x2
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80: R_PPC64_ADDR32 apfour\+0x2
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80: 00 00 00 76 \.long 0x76
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80: R_PPC64_ADDR32 \.text\+0x76
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84: 00 00 00 00 \.long 0x0
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Disassembly of section \.data:
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@ -38,27 +38,33 @@ Disassembly of section \.text:
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40: R_PPC64_REL32 x
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44: 00 00 00 04 \.long 0x4
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44: R_PPC64_REL32 x\+0x4
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\.\.\.
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48: 00 00 00 00 \.long 0x0
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48: R_PPC64_REL32 z
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4c: R_PPC64_REL32 y
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4c: 00 00 00 04 \.long 0x4
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4c: R_PPC64_REL32 \.data\+0x4
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50: 00 00 00 00 \.long 0x0
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50: R_PPC64_ADDR32 x
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54: R_PPC64_ADDR32 y
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54: 00 00 00 04 \.long 0x4
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54: R_PPC64_ADDR32 \.data\+0x4
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58: 00 00 00 00 \.long 0x0
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58: R_PPC64_ADDR32 z
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5c: ff ff ff fc fnmsub f31,f31,f31,f31
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5c: R_PPC64_ADDR32 x\+0xfffffffffffffffc
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60: ff ff ff fc fnmsub f31,f31,f31,f31
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60: R_PPC64_ADDR32 y\+0xfffffffffffffffc
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60: 00 00 00 00 \.long 0x0
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60: R_PPC64_ADDR32 \.data
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64: ff ff ff fc fnmsub f31,f31,f31,f31
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64: R_PPC64_ADDR32 z\+0xfffffffffffffffc
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68: ff ff ff a4 \.long 0xffffffa4
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6c: ff ff ff a4 \.long 0xffffffa4
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\.\.\.
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70: 00 00 00 00 \.long 0x0
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70: R_PPC64_ADDR32 a
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74: R_PPC64_ADDR32 b
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78: R_PPC64_ADDR32 apfour
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74: 00 00 00 10 \.long 0x10
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74: R_PPC64_ADDR32 \.text\+0x10
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78: 00 00 00 10 \.long 0x10
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78: R_PPC64_ADDR32 \.text\+0x10
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7c: ff ff ff fc fnmsub f31,f31,f31,f31
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80: 00 00 00 02 \.long 0x2
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80: R_PPC64_ADDR32 apfour\+0x2
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80: 00 00 00 12 \.long 0x12
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80: R_PPC64_ADDR32 \.text\+0x12
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84: 00 00 00 00 \.long 0x0
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Disassembly of section \.data:
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@ -9,20 +9,20 @@ Disassembly of section \.text:
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0+0000000 <start>:
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0: 24 25 00 30 bce 1,4\*cr1\+gt,30 <branch_target_1>
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4: 24 46 00 3d bcel 2,4\*cr1\+eq,40 <branch_target_2>
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8: 24 67 00 02 bcea 3,4\*cr1\+so,0 <start>
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8: R_PPC(64)?_ADDR14 branch_target_3
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c: 24 88 00 03 bcela 4,4\*cr2\+lt,0 <start>
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c: R_PPC(64)?_ADDR14 branch_target_4
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8: 24 67 00 52 bcea 3,4\*cr1\+so,50 <branch_target_3>
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8: R_PPC(64)?_ADDR14 \.text\+0x50
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c: 24 88 00 73 bcela 4,4\*cr2\+lt,70 <branch_target_4>
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c: R_PPC(64)?_ADDR14 \.text\+0x70
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10: 4c a9 00 22 bclre 5,4\*cr2\+gt
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14: 4c aa 00 23 bclrel 5,4\*cr2\+eq
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18: 4d 0b 04 22 bcctre 8,4\*cr2\+so
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1c: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt
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20: 58 00 00 74 be 94 <branch_target_5>
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24: 58 00 00 89 bel ac <branch_target_6>
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28: 58 00 00 02 bea 0 <start>
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28: R_PPC(64)?_ADDR24 branch_target_7
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2c: 58 00 00 03 bela 0 <start>
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2c: R_PPC(64)?_ADDR24 branch_target_8
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28: 58 00 00 f6 bea f4 <branch_target_7>
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28: R_PPC(64)?_ADDR24 \.text\+0xf4
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2c: 58 00 01 2b bela 128 <branch_target_8>
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2c: R_PPC(64)?_ADDR24 \.text\+0x128
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0+0000030 <branch_target_1>:
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30: e9 09 00 80 lbze r8,8\(r9\)
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@ -35,13 +35,13 @@ Disassembly of section \.text:
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0+ <\.text>:
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+0: e0 83 00 00 lq r4,0\(r3\)
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2: R_PPC64_ADDR16_LO_DS dsym0
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2: R_PPC64_ADDR16_LO_DS \.data
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+4: e0 83 00 00 lq r4,0\(r3\)
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6: R_PPC64_ADDR16_LO_DS dsym1
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6: R_PPC64_ADDR16_LO_DS \.data\+0x8
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+8: e0 83 00 00 lq r4,0\(r3\)
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a: R_PPC64_ADDR16_LO_DS usym0
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+c: e0 83 00 00 lq r4,0\(r3\)
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e: R_PPC64_ADDR16_LO_DS usym1
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a: R_PPC64_ADDR16_LO_DS \.data\+0x8
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+c: e0 83 00 10 lq r4,16\(r3\)
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e: R_PPC64_ADDR16_LO_DS \.data\+0x10
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+10: e0 83 00 00 lq r4,0\(r3\)
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12: R_PPC64_ADDR16_LO_DS esym0
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+14: e0 83 00 00 lq r4,0\(r3\)
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@ -63,15 +63,15 @@ Disassembly of section \.text:
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+34: e0 80 00 00 lq r4,0\(0\)
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36: R_PPC64_ADDR16_LO_DS \.text
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+38: e0 c3 00 00 lq r6,0\(r3\)
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3a: R_PPC64_GOT16_DS dsym0
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3a: R_PPC64_GOT16_DS \.data
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+3c: e0 c3 00 00 lq r6,0\(r3\)
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3e: R_PPC64_GOT16_LO_DS dsym0
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3e: R_PPC64_GOT16_LO_DS \.data
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+40: e0 c3 00 00 lq r6,0\(r3\)
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42: R_PPC64_PLT16_LO_DS dsym0
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42: R_PPC64_PLT16_LO_DS \.data
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+44: e0 c3 00 00 lq r6,0\(r3\)
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46: R_PPC64_SECTOFF_DS dsym1
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46: R_PPC64_SECTOFF_DS \.data\+0x8
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+48: e0 c3 00 00 lq r6,0\(r3\)
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4a: R_PPC64_SECTOFF_LO_DS dsym1
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4a: R_PPC64_SECTOFF_LO_DS \.data\+0x8
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+4c: e0 c4 00 10 lq r6,16\(r4\)
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+50: f8 c7 00 02 stq r6,0\(r7\)
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+54: f8 c7 00 12 stq r6,16\(r7\)
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|
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|
@ -36,13 +36,13 @@ Disassembly of section \.text:
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0+0000 <\.text>:
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0: 80 63 00 00 lwz r3,0\(r3\)
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2: R_PPC_ADDR16_LO dsym0
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4: 80 63 00 00 lwz r3,0\(r3\)
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6: R_PPC_ADDR16_LO dsym1
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8: 80 63 00 00 lwz r3,0\(r3\)
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a: R_PPC_ADDR16_LO usym0
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c: 80 63 00 00 lwz r3,0\(r3\)
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e: R_PPC_ADDR16_LO usym1
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2: R_PPC_ADDR16_LO \.data
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4: 80 63 00 04 lwz r3,4\(r3\)
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6: R_PPC_ADDR16_LO \.data\+0x4
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8: 80 63 00 04 lwz r3,4\(r3\)
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a: R_PPC_ADDR16_LO \.data\+0x4
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c: 80 63 00 08 lwz r3,8\(r3\)
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e: R_PPC_ADDR16_LO \.data\+0x8
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10: 80 63 00 00 lwz r3,0\(r3\)
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12: R_PPC_ADDR16_LO esym0
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14: 80 63 00 00 lwz r3,0\(r3\)
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|
@ -54,11 +54,11 @@ Disassembly of section \.text:
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28: 38 60 ff fc li r3,-4
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2c: 38 60 00 04 li r3,4
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30: 38 60 00 00 li r3,0
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32: R_PPC_ADDR16_LO dsym0
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32: R_PPC_ADDR16_LO \.data
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34: 38 60 00 00 li r3,0
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36: R_PPC_ADDR16_HI dsym0
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36: R_PPC_ADDR16_HI \.data
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38: 38 60 00 00 li r3,0
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3a: R_PPC_ADDR16_HA dsym0
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3a: R_PPC_ADDR16_HA \.data
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3c: 38 60 ff fc li r3,-4
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40: 38 60 ff ff li r3,-1
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44: 38 60 00 00 li r3,0
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|
|
|
@ -41,13 +41,13 @@ Disassembly of section \.text:
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|
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0000000000000000 <\.text>:
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0: e8 63 00 00 ld r3,0\(r3\)
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2: R_PPC64_ADDR16_LO_DS dsym0
|
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4: e8 63 00 00 ld r3,0\(r3\)
|
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6: R_PPC64_ADDR16_LO_DS dsym1
|
||||
8: e8 63 00 00 ld r3,0\(r3\)
|
||||
a: R_PPC64_ADDR16_LO_DS usym0
|
||||
c: e8 63 00 00 ld r3,0\(r3\)
|
||||
e: R_PPC64_ADDR16_LO_DS usym1
|
||||
2: R_PPC64_ADDR16_LO_DS \.data
|
||||
4: e8 63 00 08 ld r3,8\(r3\)
|
||||
6: R_PPC64_ADDR16_LO_DS \.data\+0x8
|
||||
8: e8 63 00 08 ld r3,8\(r3\)
|
||||
a: R_PPC64_ADDR16_LO_DS \.data\+0x8
|
||||
c: e8 63 00 10 ld r3,16\(r3\)
|
||||
e: R_PPC64_ADDR16_LO_DS \.data\+0x10
|
||||
10: e8 63 00 00 ld r3,0\(r3\)
|
||||
12: R_PPC64_ADDR16_LO_DS esym0
|
||||
14: e8 63 00 00 ld r3,0\(r3\)
|
||||
|
@ -75,19 +75,19 @@ Disassembly of section \.text:
|
|||
48: 38 60 ff f8 li r3,-8
|
||||
4c: 38 60 00 08 li r3,8
|
||||
50: 38 60 00 00 li r3,0
|
||||
52: R_PPC64_ADDR16_LO dsym0
|
||||
52: R_PPC64_ADDR16_LO \.data
|
||||
54: 38 60 00 00 li r3,0
|
||||
56: R_PPC64_ADDR16_HI dsym0
|
||||
56: R_PPC64_ADDR16_HI \.data
|
||||
58: 38 60 00 00 li r3,0
|
||||
5a: R_PPC64_ADDR16_HA dsym0
|
||||
5a: R_PPC64_ADDR16_HA \.data
|
||||
5c: 38 60 00 00 li r3,0
|
||||
5e: R_PPC64_ADDR16_HIGHER dsym0
|
||||
5e: R_PPC64_ADDR16_HIGHER \.data
|
||||
60: 38 60 00 00 li r3,0
|
||||
62: R_PPC64_ADDR16_HIGHERA dsym0
|
||||
62: R_PPC64_ADDR16_HIGHERA \.data
|
||||
64: 38 60 00 00 li r3,0
|
||||
66: R_PPC64_ADDR16_HIGHEST dsym0
|
||||
66: R_PPC64_ADDR16_HIGHEST \.data
|
||||
68: 38 60 00 00 li r3,0
|
||||
6a: R_PPC64_ADDR16_HIGHESTA dsym0
|
||||
6a: R_PPC64_ADDR16_HIGHESTA \.data
|
||||
6c: 38 60 ff f8 li r3,-8
|
||||
70: 38 60 ff ff li r3,-1
|
||||
74: 38 60 00 00 li r3,0
|
||||
|
@ -137,9 +137,15 @@ Disassembly of section \.toc:
|
|||
|
||||
0000000000000000 <\.toc>:
|
||||
\.\.\.
|
||||
0: R_PPC64_ADDR64 dsym0
|
||||
8: R_PPC64_ADDR64 dsym1
|
||||
10: R_PPC64_ADDR64 usym0
|
||||
18: R_PPC64_ADDR64 usym1
|
||||
0: R_PPC64_ADDR64 \.data
|
||||
8: R_PPC64_ADDR64 \.data\+0x8
|
||||
c: 00 00 00 08 \.long 0x8
|
||||
10: 00 00 00 00 \.long 0x0
|
||||
10: R_PPC64_ADDR64 \.data\+0x8
|
||||
14: 00 00 00 08 \.long 0x8
|
||||
18: 00 00 00 00 \.long 0x0
|
||||
18: R_PPC64_ADDR64 \.data\+0x10
|
||||
1c: 00 00 00 10 \.long 0x10
|
||||
\.\.\.
|
||||
20: R_PPC64_ADDR64 esym0
|
||||
28: R_PPC64_ADDR64 esym1
|
||||
|
|
Loading…
Reference in New Issue