RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0
These are all invalid instructions, so they should not disassemble. opcodes/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (match_c_addi16sp) : New function. (match_c_addi4spn): New function. (match_c_lui): Don't allow 0-immediate encodings. (riscv_opcodes) <addi>: Use the above functions. <add>: Likewise. <c.addi4spn>: Likewise. <c.addi16sp>: Likewise. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-addi16sp-fail.d: New test. testsuite/gas/riscv/c-addi16sp-fail.l: Likewise. testsuite/gas/riscv/c-addi16sp-fail.s: Likewise. testsuite/gas/riscv/c-addi4spn-fail.d: Likewise. testsuite/gas/riscv/c-addi4spn-fail.l: Likewise. testsuite/gas/riscv/c-addi4spn-fail.s: Likewise. testsuite/gas/riscv/riscv.exp: Add new tests.
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@ -1,3 +1,13 @@
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2017-10-24 Andrew Waterman <andrew@sifive.com>
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* testsuite/gas/riscv/c-addi16sp-fail.d: New test.
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testsuite/gas/riscv/c-addi16sp-fail.l: Likewise.
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testsuite/gas/riscv/c-addi16sp-fail.s: Likewise.
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testsuite/gas/riscv/c-addi4spn-fail.d: Likewise.
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testsuite/gas/riscv/c-addi4spn-fail.l: Likewise.
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testsuite/gas/riscv/c-addi4spn-fail.s: Likewise.
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testsuite/gas/riscv/riscv.exp: Add new tests.
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2017-10-24 Andrew Waterman <andrew@sifive.com>
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* testsuite/gas/riscv/c-lui-fail.d: New testcase.
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3
gas/testsuite/gas/riscv/c-addi16sp-fail.d
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3
gas/testsuite/gas/riscv/c-addi16sp-fail.d
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#as: -march=rv32ic
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#source: c-addi16sp-fail.s
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#error-output: c-addi16sp-fail.l
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2
gas/testsuite/gas/riscv/c-addi16sp-fail.l
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2
gas/testsuite/gas/riscv/c-addi16sp-fail.l
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.*: Assembler messages:
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.*: Error: illegal operands `c.addi16sp x1,0'
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2
gas/testsuite/gas/riscv/c-addi16sp-fail.s
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2
gas/testsuite/gas/riscv/c-addi16sp-fail.s
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target:
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c.addi16sp x1, 0
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3
gas/testsuite/gas/riscv/c-addi4spn-fail.d
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3
gas/testsuite/gas/riscv/c-addi4spn-fail.d
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#as: -march=rv32ic
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#source: c-addi4spn-fail.s
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#error-output: c-addi4spn-fail.l
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2
gas/testsuite/gas/riscv/c-addi4spn-fail.l
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2
gas/testsuite/gas/riscv/c-addi4spn-fail.l
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.*: Assembler messages:
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.*: Error: illegal operands `c.addi4spn x1,0'
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2
gas/testsuite/gas/riscv/c-addi4spn-fail.s
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2
gas/testsuite/gas/riscv/c-addi4spn-fail.s
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target:
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c.addi4spn x1, 0
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@ -22,4 +22,6 @@ if [istarget riscv*-*-*] {
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run_dump_test "t_insns"
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run_dump_test "fmv.x"
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run_dump_test "c-lui-fail"
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run_dump_test "c-addi4spn-fail"
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run_dump_test "c-addi16sp-fail"
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}
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@ -1,3 +1,13 @@
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2017-10-24 Andrew Waterman <andrew@sifive.com>
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* riscv-opc.c (match_c_addi16sp) : New function.
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(match_c_addi4spn): New function.
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(match_c_lui): Don't allow 0-immediate encodings.
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(riscv_opcodes) <addi>: Use the above functions.
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<add>: Likewise.
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<c.addi4spn>: Likewise.
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<c.addi16sp>: Likewise.
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2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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* i386-init.h: Regenerate
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@ -113,10 +113,26 @@ match_c_add (const struct riscv_opcode *op, insn_t insn)
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return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0);
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}
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static int
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match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
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{
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return (match_opcode (op, insn)
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&& (((insn & MASK_RD) >> OP_SH_RD) == 2)
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&& EXTRACT_RVC_ADDI16SP_IMM (insn) != 0);
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}
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static int
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match_c_lui (const struct riscv_opcode *op, insn_t insn)
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{
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return match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2);
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return (match_rd_nonzero (op, insn)
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&& (((insn & MASK_RD) >> OP_SH_RD) != 2)
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&& EXTRACT_RVC_LUI_IMM (insn) != 0);
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}
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static int
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match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
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{
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return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
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}
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const struct riscv_opcode riscv_opcodes[] =
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@ -188,15 +204,15 @@ const struct riscv_opcode riscv_opcodes[] =
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{"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS },
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{"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS },
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{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 },
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{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
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{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
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{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
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{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
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{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
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{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
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{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
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{"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
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{"add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
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{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS },
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{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS },
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{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
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{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
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{"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
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{"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
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{"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
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@ -628,8 +644,8 @@ const struct riscv_opcode riscv_opcodes[] =
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{"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 },
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{"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 },
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{"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
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{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
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{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
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{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 },
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{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 },
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{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
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{"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 },
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{"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
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