i386: Check for reserved VEX.vvvv and EVEX.vvvv
If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. gas/ PR binutils/24626 * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv and EVEX.vvvv. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24626 * i386-dis.c (print_insn): Check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. (OP_VEX): Set vex.register_specifier to 0 after readding vex.register_specifier. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_LWP_E): Likewise. (OP_EX_Vex): Don't check vex.register_specifier. (OP_XMM_Vex): Likewise.
This commit is contained in:
H.J. Lu
parent
ad118caa9f
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63c6fc6cac
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@ -1,3 +1,12 @@
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2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/24626
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* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
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and EVEX.vvvv.
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* testsuite/gas/i386/x86-64-disassem.s: Likewise.
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* testsuite/gas/i386/disassem.d: Updated.
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* testsuite/gas/i386/x86-64-disassem.d: Likewise.
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2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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Lili Cui <lili.cui@intel.com>
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@ -341,4 +341,9 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%esi\),\(%dx\)
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[ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*3f[ ]*aas[ ]*
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[ ]*[a-f0-9]+:[ ]*c4 e2 01 1c[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*41[ ]*inc[ ]*%ecx
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[ ]*[a-f0-9]+:[ ]*37[ ]*aaa[ ]*
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[ ]*[a-f0-9]+:[ ]*62 f2 ad 08 1c[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*01[ ]*.byte[ ]*0x1
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#pass
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@ -167,3 +167,5 @@
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x9B
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
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.byte 0xc4, 0xe2, 0x1, 0x1c, 0x41, 0x37
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.byte 0x62, 0xf2, 0xad, 0x08, 0x1c, 0x01
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@ -341,4 +341,8 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*6f[ ]*outsl %ds:\(%rsi\),\(%dx\)
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[ ]*[a-f0-9]+:[ ]*c4 e1 f9 93[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*3f[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*c4 62 01 1c[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*41 37[ ]*rex.B \(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*62 72 ad 08 1c[ ]*\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]*01[ ]*.byte[ ]*0x1
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#pass
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@ -167,3 +167,5 @@
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x9B
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x3F
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.byte 0xc4, 0x62, 0x1, 0x1c, 0x41, 0x37
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.byte 0x62, 0x72, 0xad, 0x08, 0x1c, 0x01
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@ -1,3 +1,16 @@
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2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/24626
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* i386-dis.c (print_insn): Check for unused VEX.vvvv and
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EVEX.vvvv when disassembling VEX and EVEX instructions.
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(OP_VEX): Set vex.register_specifier to 0 after readding
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vex.register_specifier.
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(OP_Vex_2src_1): Likewise.
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(OP_Vex_2src_2): Likewise.
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(OP_LWP_E): Likewise.
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(OP_EX_Vex): Don't check vex.register_specifier.
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(OP_XMM_Vex): Likewise.
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2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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Lili Cui <lili.cui@intel.com>
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@ -12155,6 +12155,14 @@ print_insn (bfd_vma pc, disassemble_info *info)
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}
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}
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/* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
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are all 0s in inverted form. */
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if (need_vex && vex.register_specifier != 0)
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{
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(*info->fprintf_func) (info->stream, "(bad)");
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return end_codep - priv.the_buffer;
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}
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/* Check if the REX prefix is used. */
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if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
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all_prefixes[last_rex_prefix] = 0;
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@ -15921,6 +15929,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
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return;
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reg = vex.register_specifier;
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vex.register_specifier = 0;
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if (address_mode != mode_64bit)
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reg &= 7;
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else if (vex.evex && !vex.v)
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@ -16204,6 +16213,7 @@ OP_Vex_2src_1 (int bytemode, int sizeflag)
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if (vex.w)
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{
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unsigned int reg = vex.register_specifier;
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vex.register_specifier = 0;
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if (address_mode != mode_64bit)
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reg &= 7;
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@ -16221,6 +16231,7 @@ OP_Vex_2src_2 (int bytemode, int sizeflag)
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else
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{
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unsigned int reg = vex.register_specifier;
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vex.register_specifier = 0;
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if (address_mode != mode_64bit)
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reg &= 7;
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@ -16298,11 +16309,7 @@ static void
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OP_EX_Vex (int bytemode, int sizeflag)
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{
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if (modrm.mod != 3)
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{
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if (vex.register_specifier != 0)
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BadOp ();
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need_vex_reg = 0;
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}
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need_vex_reg = 0;
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OP_EX (bytemode, sizeflag);
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}
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@ -16310,11 +16317,7 @@ static void
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OP_XMM_Vex (int bytemode, int sizeflag)
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{
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if (modrm.mod != 3)
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{
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if (vex.register_specifier != 0)
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BadOp ();
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need_vex_reg = 0;
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}
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need_vex_reg = 0;
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OP_XMM (bytemode, sizeflag);
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}
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@ -16594,6 +16597,7 @@ OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
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{
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const char **names;
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unsigned int reg = vex.register_specifier;
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vex.register_specifier = 0;
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if (rex & REX_W)
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names = names64;
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