Jakub Jelinek <jj@ultra.linux.cz>
* config/tc-sparc.c (md_assemble): Fix up setx, support setsw. Optimize set if sizeof(bfd_vma) == 64. (sparc_ip): Fix sethi - without %hi() it should generate R_SPARC_32 reloc, not R_SPARC_HI22. (tc_gen_reloc): Handle BFD_RELOC_SPARC22.
This commit is contained in:
parent
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63fab58c7d
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@ -1,3 +1,11 @@
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1999-06-07 Jakub Jelinek <jj@ultra.linux.cz>
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* config/tc-sparc.c (md_assemble): Fix up setx, support setsw.
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Optimize set if sizeof(bfd_vma) == 64.
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(sparc_ip): Fix sethi - without %hi() it should generate
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R_SPARC_32 reloc, not R_SPARC_HI22.
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(tc_gen_reloc): Handle BFD_RELOC_SPARC22.
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1999-06-07 Jakub Jelinek <jj@ultra.linux.cz>
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1999-06-07 Jakub Jelinek <jj@ultra.linux.cz>
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* config/tc-sparc.c (md_begin): Handle native wordsize aliases.
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* config/tc-sparc.c (md_begin): Handle native wordsize aliases.
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@ -913,6 +913,7 @@ static int special_case;
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/* Bit masks of various insns. */
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/* Bit masks of various insns. */
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#define NOP_INSN 0x01000000
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#define NOP_INSN 0x01000000
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#define OR_INSN 0x80100000
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#define OR_INSN 0x80100000
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#define XOR_INSN 0x80180000
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#define FMOVS_INSN 0x81A00020
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#define FMOVS_INSN 0x81A00020
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#define SETHI_INSN 0x01000000
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#define SETHI_INSN 0x01000000
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#define SLLX_INSN 0x81281000
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#define SLLX_INSN 0x81281000
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@ -964,222 +965,295 @@ md_assemble (str)
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as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
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as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
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}
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}
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switch (special_case)
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for (;;)
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{
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{
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case SPECIAL_CASE_NONE:
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switch (special_case)
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/* normal insn */
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{
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output_insn (insn, &the_insn);
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case SPECIAL_CASE_NONE:
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break;
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/* normal insn */
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output_insn (insn, &the_insn);
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return;
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case SPECIAL_CASE_SET:
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case SPECIAL_CASE_SETSW:
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{
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if (the_insn.exp.X_op == O_constant)
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int need_hi22_p = 0;
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{
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int low32;
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if (the_insn.exp.X_add_number < -(offsetT)0x80000000
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|| the_insn.exp.X_add_number > (offsetT) 0xffffffff)
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as_warn (_("setsw: number not in -2147483648..4294967295 range"));
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/* "set" is not defined for negative numbers in v9: it doesn't yield
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low32 = the_insn.exp.X_add_number;
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what you expect it to. */
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if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
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if (low32 < 0)
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&& the_insn.exp.X_op == O_constant)
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{
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{
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int rd = (the_insn.opcode & RD (~0)) >> 25;
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if (the_insn.exp.X_add_number < 0)
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int opc = OR_INSN;
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as_warn (_("set: used with negative number"));
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else if (the_insn.exp.X_add_number > (offsetT) 0xffffffff)
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the_insn.reloc = BFD_RELOC_NONE;
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as_warn (_("set: number larger than 4294967295"));
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/* See if operand is absolute and small; skip sethi if so. */
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}
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if (low32 < -(1 << 12))
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{
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the_insn.opcode = (SETHI_INSN | RD (rd)
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| (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
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output_insn (insn, &the_insn);
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low32 = 0x1c00 | (low32 & 0x3ff);
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opc = RS1 (rd) | XOR_INSN;
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}
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/* See if operand is absolute and small; skip sethi if so. */
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the_insn.opcode = (opc | RD (rd) | IMMED
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if (the_insn.exp.X_op != O_constant
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| (low32 & 0x1fff));
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|| the_insn.exp.X_add_number >= (1 << 12)
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output_insn (insn, &the_insn);
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|| the_insn.exp.X_add_number < -(1 << 12))
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return;
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{
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}
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output_insn (insn, &the_insn);
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}
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need_hi22_p = 1;
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/* FALLTHROUGH */
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}
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/* See if operand has no low-order bits; skip OR if so. */
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case SPECIAL_CASE_SET:
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if (the_insn.exp.X_op != O_constant
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|| (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
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|| ! need_hi22_p)
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{
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{
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int need_hi22_p = 0;
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int rd = (the_insn.opcode & RD (~0)) >> 25;
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int rd = (the_insn.opcode & RD (~0)) >> 25;
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the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
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| RD (rd)
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| IMMED
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| (the_insn.exp.X_add_number
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& (need_hi22_p ? 0x3ff : 0x1fff)));
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the_insn.reloc = (the_insn.exp.X_op != O_constant
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? BFD_RELOC_LO10
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: BFD_RELOC_NONE);
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output_insn (insn, &the_insn);
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}
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break;
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}
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case SPECIAL_CASE_SETSW:
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if (the_insn.exp.X_op == O_constant)
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{
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/* FIXME: Not finished. */
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break;
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}
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case SPECIAL_CASE_SETX:
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{
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#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
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int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
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int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
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#undef SIGNEXT32
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int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
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int dstreg = (the_insn.opcode & RD (~0)) >> 25;
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/* Output directly to dst reg if lower 32 bits are all zero. */
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int upper_dstreg = (the_insn.exp.X_op == O_constant
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&& lower32 == 0) ? dstreg : tmpreg;
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int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
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/* The tmp reg should not be the dst reg. */
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if (tmpreg == dstreg)
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as_warn (_("setx: temporary register same as destination register"));
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/* Reset X_add_number, we've extracted it as upper32/lower32.
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Otherwise fixup_segment will complain about not being able to
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write an 8 byte number in a 4 byte field. */
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the_insn.exp.X_add_number = 0;
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/* ??? Obviously there are other optimizations we can do
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(e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
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doing some of these. Later. If you do change things, try to
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change all of this to be table driven as well. */
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/* What to output depends on the number if it's constant.
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Compute that first, then output what we've decided upon. */
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if (the_insn.exp.X_op != O_constant)
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need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
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else
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{
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/* Only need hh22 if `or' insn can't handle constant. */
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if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
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need_hh22_p = 1;
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/* Does bottom part (after sethi) have bits? */
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if ((need_hh22_p && (upper32 & 0x3ff) != 0)
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/* No hh22, but does upper32 still have bits we can't set
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from lower32? */
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|| (! need_hh22_p
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&& upper32 != 0
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&& (upper32 != -1 || lower32 >= 0)))
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need_hm10_p = 1;
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/* If the lower half is all zero, we build the upper half directly
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into the dst reg. */
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if (lower32 != 0
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/* Need lower half if number is zero. */
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|| (! need_hh22_p && ! need_hm10_p))
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{
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{
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/* No need for sethi if `or' insn can handle constant. */
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if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
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if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
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{
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/* Note that we can't use a negative constant in the `or'
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if (the_insn.exp.X_add_number < 0
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insn unless the upper 32 bits are all ones. */
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|| the_insn.exp.X_add_number > (offsetT) 0xffffffff)
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|| (lower32 < 0 && upper32 != -1))
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as_warn (_("set: number not in 0..4294967295 range"));
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need_hi22_p = 1;
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}
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else
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/* Does bottom part (after sethi) have bits? */
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{
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if ((need_hi22_p && (lower32 & 0x3ff) != 0)
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if (the_insn.exp.X_add_number < (offsetT)-0x80000000
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/* No sethi. */
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|| the_insn.exp.X_add_number > (offsetT) 0xffffffff)
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|| (! need_hi22_p && (lower32 & 0x1fff) != 0)
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as_warn (_("set: number not in -2147483648..4294967295 range"));
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/* Need `or' if we didn't set anything else. */
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if (the_insn.exp.X_add_number >= (offsetT)0x80000000)
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|| (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
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the_insn.exp.X_add_number -= (offsetT)0x100000000;
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need_lo10_p = 1;
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}
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}
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/* See if operand is absolute and small; skip sethi if so. */
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if (the_insn.exp.X_op != O_constant
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|| the_insn.exp.X_add_number >= (1 << 12)
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|| the_insn.exp.X_add_number < -(1 << 12))
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{
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the_insn.opcode = (SETHI_INSN | RD (rd)
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| ((the_insn.exp.X_add_number >> 10)
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& the_insn.exp.X_op == O_constant ? 0x3fffff : 0));
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the_insn.reloc = BFD_RELOC_HI22;
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output_insn (insn, &the_insn);
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need_hi22_p = 1;
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}
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}
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}
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if (need_hh22_p)
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/* See if operand has no low-order bits; skip OR if so. */
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if (the_insn.exp.X_op != O_constant
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|| (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
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|| ! need_hi22_p)
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{
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the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
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| RD (rd)
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| IMMED
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| (the_insn.exp.X_add_number
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& (the_insn.exp.X_op != O_constant ? 0 :
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need_hi22_p ? 0x3ff : 0x1fff)));
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the_insn.reloc = (the_insn.exp.X_op != O_constant
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? BFD_RELOC_LO10
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: BFD_RELOC_NONE);
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output_insn (insn, &the_insn);
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}
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if (special_case == SPECIAL_CASE_SETSW
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&& the_insn.exp.X_op != O_constant)
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{
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/* Need to sign extend it. */
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the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
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the_insn.reloc = BFD_RELOC_NONE;
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output_insn (insn, &the_insn);
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}
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return;
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}
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case SPECIAL_CASE_SETX:
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{
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{
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the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
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int upper32, lower32;
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| ((upper32 >> 10) & 0x3fffff));
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int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
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the_insn.reloc = (the_insn.exp.X_op != O_constant
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int dstreg = (the_insn.opcode & RD (~0)) >> 25;
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? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
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int upper_dstreg;
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output_insn (insn, &the_insn);
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int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
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}
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int need_xor10_p = 0;
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#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
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lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
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upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
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#undef SIGNEXT32
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if (need_hm10_p)
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upper_dstreg = tmpreg;
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/* The tmp reg should not be the dst reg. */
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if (tmpreg == dstreg)
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as_warn (_("setx: temporary register same as destination register"));
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/* ??? Obviously there are other optimizations we can do
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(e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
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|
doing some of these. Later. If you do change things, try to
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|
change all of this to be table driven as well. */
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/* What to output depends on the number if it's constant.
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Compute that first, then output what we've decided upon. */
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if (the_insn.exp.X_op != O_constant)
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{
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if (sparc_arch_size == 32)
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{
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/* When arch size is 32, we want setx to be equivalent
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to setuw for anything but constants. */
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the_insn.exp.X_add_number &= 0xffffffff;
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special_case = SPECIAL_CASE_SET;
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continue;
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}
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need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
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lower32 = 0; upper32 = 0;
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}
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else
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{
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/* Reset X_add_number, we've extracted it as upper32/lower32.
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Otherwise fixup_segment will complain about not being able to
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write an 8 byte number in a 4 byte field. */
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the_insn.exp.X_add_number = 0;
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/* Only need hh22 if `or' insn can't handle constant. */
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if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
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need_hh22_p = 1;
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/* Does bottom part (after sethi) have bits? */
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if ((need_hh22_p && (upper32 & 0x3ff) != 0)
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/* No hh22, but does upper32 still have bits we can't set
|
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from lower32? */
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|| (! need_hh22_p && upper32 != 0 && upper32 != -1))
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need_hm10_p = 1;
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|
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/* If the lower half is all zero, we build the upper half directly
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into the dst reg. */
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if (lower32 != 0
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/* Need lower half if number is zero or 0xffffffff00000000. */
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|| (! need_hh22_p && ! need_hm10_p))
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{
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/* No need for sethi if `or' insn can handle constant. */
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if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
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/* Note that we can't use a negative constant in the `or'
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insn unless the upper 32 bits are all ones. */
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|| (lower32 < 0 && upper32 != -1)
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|| (lower32 >= 0 && upper32 == -1))
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need_hi22_p = 1;
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if (need_hi22_p && upper32 == -1)
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need_xor10_p = 1;
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/* Does bottom part (after sethi) have bits? */
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else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
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/* No sethi. */
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|| (! need_hi22_p && (lower32 & 0x1fff) != 0)
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/* Need `or' if we didn't set anything else. */
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|| (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
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need_lo10_p = 1;
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}
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|
else
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/* Output directly to dst reg if lower 32 bits are all
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zero. */
|
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|
upper_dstreg = dstreg;
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}
|
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|
|
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if (need_hh22_p)
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{
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the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
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| ((upper32 >> 10) & 0x3fffff));
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the_insn.reloc = (the_insn.exp.X_op != O_constant
|
||||||
|
? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
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output_insn (insn, &the_insn);
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}
|
||||||
|
|
||||||
|
if (need_hi22_p)
|
||||||
|
{
|
||||||
|
the_insn.opcode = (SETHI_INSN | RD (dstreg)
|
||||||
|
| (((need_xor10_p ? ~lower32 : lower32)
|
||||||
|
>> 10) & 0x3fffff));
|
||||||
|
the_insn.reloc = (the_insn.exp.X_op != O_constant
|
||||||
|
? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
|
||||||
|
output_insn (insn, &the_insn);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (need_hm10_p)
|
||||||
|
{
|
||||||
|
the_insn.opcode = (OR_INSN
|
||||||
|
| (need_hh22_p ? RS1 (upper_dstreg) : 0)
|
||||||
|
| RD (upper_dstreg)
|
||||||
|
| IMMED
|
||||||
|
| (upper32
|
||||||
|
& (need_hh22_p ? 0x3ff : 0x1fff)));
|
||||||
|
the_insn.reloc = (the_insn.exp.X_op != O_constant
|
||||||
|
? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
|
||||||
|
output_insn (insn, &the_insn);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (need_lo10_p)
|
||||||
|
{
|
||||||
|
/* FIXME: One nice optimization to do here is to OR the low part
|
||||||
|
with the highpart if hi22 isn't needed and the low part is
|
||||||
|
positive. */
|
||||||
|
the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
|
||||||
|
| RD (dstreg)
|
||||||
|
| IMMED
|
||||||
|
| (lower32
|
||||||
|
& (need_hi22_p ? 0x3ff : 0x1fff)));
|
||||||
|
the_insn.reloc = BFD_RELOC_LO10;
|
||||||
|
output_insn (insn, &the_insn);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If we needed to build the upper part, shift it into place. */
|
||||||
|
if (need_hh22_p || need_hm10_p)
|
||||||
|
{
|
||||||
|
the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
|
||||||
|
| IMMED | 32);
|
||||||
|
the_insn.reloc = BFD_RELOC_NONE;
|
||||||
|
output_insn (insn, &the_insn);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
|
||||||
|
if (need_xor10_p)
|
||||||
|
{
|
||||||
|
the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
|
||||||
|
| 0x1c00 | (lower32 & 0x3ff));
|
||||||
|
the_insn.reloc = BFD_RELOC_NONE;
|
||||||
|
output_insn (insn, &the_insn);
|
||||||
|
}
|
||||||
|
/* If we needed to build both upper and lower parts, OR them together. */
|
||||||
|
else if ((need_hh22_p || need_hm10_p)
|
||||||
|
&& (need_hi22_p || need_lo10_p))
|
||||||
|
{
|
||||||
|
the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
|
||||||
|
| RD (dstreg));
|
||||||
|
the_insn.reloc = BFD_RELOC_NONE;
|
||||||
|
output_insn (insn, &the_insn);
|
||||||
|
}
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
case SPECIAL_CASE_FDIV:
|
||||||
{
|
{
|
||||||
the_insn.opcode = (OR_INSN
|
int rd = (the_insn.opcode >> 25) & 0x1f;
|
||||||
| (need_hh22_p ? RS1 (upper_dstreg) : 0)
|
|
||||||
| RD (upper_dstreg)
|
|
||||||
| IMMED
|
|
||||||
| (upper32
|
|
||||||
& (need_hh22_p ? 0x3ff : 0x1fff)));
|
|
||||||
the_insn.reloc = (the_insn.exp.X_op != O_constant
|
|
||||||
? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
|
|
||||||
output_insn (insn, &the_insn);
|
output_insn (insn, &the_insn);
|
||||||
}
|
|
||||||
|
/* According to information leaked from Sun, the "fdiv" instructions
|
||||||
if (need_hi22_p)
|
on early SPARC machines would produce incorrect results sometimes.
|
||||||
{
|
The workaround is to add an fmovs of the destination register to
|
||||||
the_insn.opcode = (SETHI_INSN | RD (dstreg)
|
itself just after the instruction. This was true on machines
|
||||||
| ((lower32 >> 10) & 0x3fffff));
|
with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
|
||||||
the_insn.reloc = BFD_RELOC_HI22;
|
assert (the_insn.reloc == BFD_RELOC_NONE);
|
||||||
|
the_insn.opcode = FMOVS_INSN | rd | RD (rd);
|
||||||
output_insn (insn, &the_insn);
|
output_insn (insn, &the_insn);
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (need_lo10_p)
|
default:
|
||||||
{
|
as_fatal (_("failed special case insn sanity check"));
|
||||||
/* FIXME: One nice optimization to do here is to OR the low part
|
}
|
||||||
with the highpart if hi22 isn't needed and the low part is
|
|
||||||
positive. */
|
|
||||||
the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
|
|
||||||
| RD (dstreg)
|
|
||||||
| IMMED
|
|
||||||
| (lower32
|
|
||||||
& (need_hi22_p ? 0x3ff : 0x1fff)));
|
|
||||||
the_insn.reloc = BFD_RELOC_LO10;
|
|
||||||
output_insn (insn, &the_insn);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* If we needed to build the upper part, shift it into place. */
|
|
||||||
if (need_hh22_p || need_hm10_p)
|
|
||||||
{
|
|
||||||
the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
|
|
||||||
| IMMED | 32);
|
|
||||||
the_insn.reloc = BFD_RELOC_NONE;
|
|
||||||
output_insn (insn, &the_insn);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* If we needed to build both upper and lower parts, OR them together. */
|
|
||||||
if ((need_hh22_p || need_hm10_p)
|
|
||||||
&& (need_hi22_p || need_lo10_p))
|
|
||||||
{
|
|
||||||
the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
|
|
||||||
| RD (dstreg));
|
|
||||||
the_insn.reloc = BFD_RELOC_NONE;
|
|
||||||
output_insn (insn, &the_insn);
|
|
||||||
}
|
|
||||||
/* We didn't need both regs, but we may have to sign extend lower32. */
|
|
||||||
else if (need_hi22_p && upper32 == -1)
|
|
||||||
{
|
|
||||||
the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
|
|
||||||
| IMMED | 0);
|
|
||||||
the_insn.reloc = BFD_RELOC_NONE;
|
|
||||||
output_insn (insn, &the_insn);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
case SPECIAL_CASE_FDIV:
|
|
||||||
{
|
|
||||||
int rd = (the_insn.opcode >> 25) & 0x1f;
|
|
||||||
|
|
||||||
output_insn (insn, &the_insn);
|
|
||||||
|
|
||||||
/* According to information leaked from Sun, the "fdiv" instructions
|
|
||||||
on early SPARC machines would produce incorrect results sometimes.
|
|
||||||
The workaround is to add an fmovs of the destination register to
|
|
||||||
itself just after the instruction. This was true on machines
|
|
||||||
with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
|
|
||||||
assert (the_insn.reloc == BFD_RELOC_NONE);
|
|
||||||
the_insn.opcode = FMOVS_INSN | rd | RD (rd);
|
|
||||||
output_insn (insn, &the_insn);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
default:
|
|
||||||
as_fatal (_("failed special case insn sanity check"));
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1891,14 +1965,10 @@ sparc_ip (str, pinsn)
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case '0': /* 64 bit immediate (setx insn) */
|
case '0': /* 64 bit immediate (set, setsw, setx insn) */
|
||||||
the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
|
the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
|
||||||
goto immediate;
|
goto immediate;
|
||||||
|
|
||||||
case 'h': /* high 22 bits */
|
|
||||||
the_insn.reloc = BFD_RELOC_HI22;
|
|
||||||
goto immediate;
|
|
||||||
|
|
||||||
case 'l': /* 22 bit PC relative immediate */
|
case 'l': /* 22 bit PC relative immediate */
|
||||||
the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
|
the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
|
||||||
the_insn.pcrel = 1;
|
the_insn.pcrel = 1;
|
||||||
|
@ -1909,6 +1979,7 @@ sparc_ip (str, pinsn)
|
||||||
the_insn.pcrel = 1;
|
the_insn.pcrel = 1;
|
||||||
goto immediate;
|
goto immediate;
|
||||||
|
|
||||||
|
case 'h':
|
||||||
case 'n': /* 22 bit immediate */
|
case 'n': /* 22 bit immediate */
|
||||||
the_insn.reloc = BFD_RELOC_SPARC22;
|
the_insn.reloc = BFD_RELOC_SPARC22;
|
||||||
goto immediate;
|
goto immediate;
|
||||||
|
@ -2968,6 +3039,7 @@ tc_gen_reloc (section, fixp)
|
||||||
case BFD_RELOC_LO10:
|
case BFD_RELOC_LO10:
|
||||||
case BFD_RELOC_32_PCREL_S2:
|
case BFD_RELOC_32_PCREL_S2:
|
||||||
case BFD_RELOC_SPARC13:
|
case BFD_RELOC_SPARC13:
|
||||||
|
case BFD_RELOC_SPARC22:
|
||||||
case BFD_RELOC_SPARC_BASE13:
|
case BFD_RELOC_SPARC_BASE13:
|
||||||
case BFD_RELOC_SPARC_WDISP16:
|
case BFD_RELOC_SPARC_WDISP16:
|
||||||
case BFD_RELOC_SPARC_WDISP19:
|
case BFD_RELOC_SPARC_WDISP19:
|
||||||
|
|
Loading…
Reference in New Issue