For NEC 4100/4300 project
* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. * interp.c (CHECKHILO): Define away. (simSIGINT): New macro. (membank_size): Increase from 1MB to 2MB. (control_c): New function. (sim_resume): Rename parameter signal to signal_number. Add local variable prev. Call signal before and after simulate. (sim_stop_reason): Add simSIGINT support. (sim_warning, sim_error, dotrace, SignalException): Define as stdarg functions always. (sim_warning): Delete call to SignalException. Do call printf_filtered if logfh is NULL. (AddressTranslation): Add #ifdef DEBUG around debugging message and a call to sim_warning.
This commit is contained in:
Jim Wilson
parent
42aa243574
commit
6429b29698
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@ -1,3 +1,25 @@
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Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
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* gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
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* interp.c (CHECKHILO): Define away.
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(simSIGINT): New macro.
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(membank_size): Increase from 1MB to 2MB.
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(control_c): New function.
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(sim_resume): Rename parameter signal to signal_number. Add local
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variable prev. Call signal before and after simulate.
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(sim_stop_reason): Add simSIGINT support.
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(sim_warning, sim_error, dotrace, SignalException): Define as stdarg
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functions always.
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(sim_warning): Delete call to SignalException. Do call printf_filtered
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if logfh is NULL.
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(AddressTranslation): Add #ifdef DEBUG around debugging message and
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a call to sim_warning.
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Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
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* gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
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16 bit instructions.
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Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
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Add support for mips16 (16 bit MIPS implementation):
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@ -1862,6 +1862,9 @@ build_instruction (doisa, features, mips16, insn)
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if (insn->flags & NOT)
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printf(" op1 ^= 1;\n");
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printf(" /* NOTE: ??? Gdb gets confused if the PC is sign-extended,\n");
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printf(" so we just truncate it to 32 bits here. */\n");
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printf(" op1 = WORD64LO(op1);\n");
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printf(" /* NOTE: The jump occurs AFTER the next instruction has been executed */\n");
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printf(" DSPC = op1;\n");
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printf(" DELAYSLOT();\n");
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@ -375,7 +375,12 @@ static int LOACCESS = 0;
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following operation are spotted. */
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static ut_reg HLPC = 0;
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/* TODO: The 4300 has interlocks so we should not need to warn of the possible over-write (CHECK THIS) */
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/* ??? The 4300 and a few other processors have interlocks on hi/lo register
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reads, and hence do not have this problem. To avoid spurious warnings,
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we just disable this always. */
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#if 1
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#define CHECKHILO(s)
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#else
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/* If either of the preceding two instructions have accessed the HI or
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LO registers, then the values they see should be
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undefined. However, to keep the simulator world simple, we just let
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@ -384,6 +389,7 @@ static ut_reg HLPC = 0;
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if ((HIACCESS != 0) || (LOACCESS != 0))\
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sim_warning("%s over-writing HI and LO registers values (PC = 0x%08X%08X HLPC = 0x%08X%08X)\n",(s),(unsigned int)(PC>>32),(unsigned int)(PC&0xFFFFFFFF),(unsigned int)(HLPC>>32),(unsigned int)(HLPC&0xFFFFFFFF));\
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}
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#endif
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/* NOTE: We keep the following status flags as bit values (1 for true,
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0 for false). This allows them to be used in binary boolean
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@ -442,6 +448,7 @@ static unsigned int pipeline_ticks = 0;
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#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
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#define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
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#define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
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static unsigned int state = 0;
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static unsigned int rcexit = 0; /* _exit() reason code holder */
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@ -465,7 +472,11 @@ static unsigned int rcexit = 0; /* _exit() reason code holder */
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/* Very simple memory model to start with: */
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static unsigned char *membank = NULL;
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static ut_reg membank_base = K1BASE;
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static unsigned membank_size = (1 << 20); /* (16 << 20); */ /* power-of-2 */
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/* The ddb.ld linker script loads text at K1BASE+1MB, and the idt.ld linker
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script loads text at K1BASE+128KB. We allocate 2MB, so that we have a
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minimum of 1 MB available for the user process. We must have memory
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above _end in order for sbrk to work. */
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static unsigned membank_size = (2 << 20);
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/* Simple run-time monitor support */
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static unsigned char *monitor = NULL;
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@ -478,6 +489,7 @@ static FILE *logfh = NULL;
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#if defined(TRACE)
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static char *tracefile = "trace.din"; /* default filename for trace log */
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static FILE *tracefh = NULL;
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static void open_trace PARAMS((void));
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#endif /* TRACE */
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#if defined(PROFILE)
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@ -818,18 +830,26 @@ Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
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}
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#if defined(TRACE)
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if (state & simTRACE) {
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tracefh = fopen(tracefile,"wb+");
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if (tracefh == NULL) {
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sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile);
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tracefh = stderr;
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}
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}
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if (state & simTRACE)
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open_trace();
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#endif /* TRACE */
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return;
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}
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#if defined(TRACE)
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static void
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open_trace()
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{
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tracefh = fopen(tracefile,"wb+");
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if (tracefh == NULL)
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{
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sim_warning("Failed to create file \"%s\", writing trace information to stderr.",tracefile);
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tracefh = stderr;
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}
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}
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#endif /* TRACE */
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/* For the profile writing, we write the data in the host
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endianness. This unfortunately means we are assuming that the
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profile file we create is processed on the same host executing the
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@ -954,11 +974,23 @@ sim_close (quitting)
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}
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void
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sim_resume (step,signal)
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int step, signal;
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control_c (sig, code, scp, addr)
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int sig;
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int code;
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char *scp;
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char *addr;
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{
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state |= (simSTOP | simSIGINT);
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}
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void
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sim_resume (step,signal_number)
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int step, signal_number;
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{
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void (*prev) ();
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#ifdef DEBUG
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printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal,membank);
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printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal_number,membank);
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#endif /* DEBUG */
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if (step)
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@ -971,7 +1003,12 @@ sim_resume (step,signal)
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/* Start executing instructions from the current state (set
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explicitly by register updates, or by sim_create_inferior): */
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prev = signal (SIGINT, control_c);
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simulate();
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signal (SIGINT, prev);
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return;
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}
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@ -1222,11 +1259,14 @@ sim_stop_reason (reason,sigrc)
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#endif
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*reason = sim_exited;
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*sigrc = rcexit;
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} else if (state & simSIGINT) {
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*reason = sim_stopped;
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*sigrc = SIGINT;
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} else { /* assume single-stepping */
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*reason = sim_stopped;
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*sigrc = SIGTRAP;
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}
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state &= ~(simEXCEPTION | simEXIT);
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state &= ~(simEXCEPTION | simEXIT | simSIGINT);
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return;
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}
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@ -1516,8 +1556,11 @@ sim_trace()
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#if defined(TRACE)
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/* Ensure tracing is enabled, if available */
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if (tracefh != NULL)
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state |= simTRACE;
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if (tracefh == NULL)
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{
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open_trace();
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state |= simTRACE;
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}
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#endif /* TRACE */
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state &= ~(simSTOP | simSTEP); /* execute until event */
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@ -1766,44 +1809,37 @@ sim_monitor(reason)
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}
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void
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#ifdef _MSC_VER
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sim_warning(char *fmt,...)
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#else
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sim_warning(fmt)
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char *fmt;
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#endif
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{
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char buf[256];
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va_list ap;
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va_start(ap,fmt);
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va_start (ap,fmt);
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vsprintf (buf, fmt, ap);
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va_end (ap);
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if (logfh != NULL) {
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#if 1
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fprintf(logfh,"SIM Warning: ");
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fprintf(logfh,fmt,ap);
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fprintf(logfh,"\n");
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#else /* we should provide a method of routing log messages to the simulator output stream */
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callback->printf_filtered(callback,"SIM Warning: ");
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callback->printf_filtered(callback,fmt,ap);
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#endif
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fprintf(logfh,"SIM Warning: %s\n", buf);
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} else {
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callback->printf_filtered(callback,"SIM Warning: %s\n", buf);
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}
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va_end(ap);
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SignalException(SimulatorFault,"");
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/* This used to call SignalException with a SimulatorFault, but that causes
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the simulator to exit, and that is inappropriate for a warning. */
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return;
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}
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void
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#ifdef _MSC_VER
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sim_error(char *fmt,...)
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#else
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sim_error(fmt)
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char *fmt;
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#endif
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{
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char buf[256];
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va_list ap;
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va_start(ap,fmt);
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callback->printf_filtered(callback,"SIM Error: ");
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callback->printf_filtered(callback,fmt,ap);
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va_end(ap);
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SignalException(SimulatorFault,"");
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va_start (ap,fmt);
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vsprintf (buf, fmt, ap);
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va_end (ap);
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callback->printf_filtered(callback,"SIM Error: %s", buf);
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SignalException (SimulatorFault, buf);
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return;
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}
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@ -1888,23 +1924,16 @@ getnum(value)
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static
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#ifdef _MSC_VER
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void dotrace(FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...)
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#else
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void dotrace(tracefh,type,address,width,comment)
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FILE *tracefh;
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int type;
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SIM_ADDR address;
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int width;
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char *comment;
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#endif
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{
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if (state & simTRACE) {
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va_list ap;
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fprintf(tracefh,"%d %08x%08x ; width %d ; ",
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type,(unsigned long)(address>>32),(unsigned long)(address&0xffffffff),width);
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type,
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sizeof (address) > 4 ? (unsigned long)(address>>32) : 0,
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(unsigned long)(address&0xffffffff),width);
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va_start(ap,comment);
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fprintf(tracefh,comment,ap);
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vfprintf(tracefh,comment,ap);
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va_end(ap);
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fprintf(tracefh,"\n");
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}
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@ -2195,15 +2224,21 @@ AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw)
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if (host)
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*pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))];
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} else {
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#if 1 /* def DEBUG */
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#ifdef DEBUG
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sim_warning("Failed: AddressTranslation(0x%08X%08X,%s,%s,...) IPC = 0x%08X%08X",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),WORD64HI(IPC),WORD64LO(IPC));
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#endif /* DEBUG */
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res = 0; /* AddressTranslation has failed */
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*pAddr = (SIM_ADDR)-1;
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if (!raw) /* only generate exceptions on real memory transfers */
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SignalException((LorS == isSTORE) ? AddressStore : AddressLoad);
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#ifdef DEBUG
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else
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/* This is a normal occurance during gdb operation, for instance trying
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to print parameters at function start before they have been setup,
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and hence we should not print a warning except when debugging the
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simulator. */
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sim_warning("AddressTranslation for %s %s from 0x%08X%08X failed",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),WORD64HI(vAddr),WORD64LO(vAddr));
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#endif
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}
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return(res);
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@ -2280,7 +2315,9 @@ LoadMemory(CCA,AccessLength,pAddr,vAddr,IorD,raw)
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/* If instruction fetch then we need to check that the two lo-order
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bits are zero, otherwise raise a InstructionFetch exception: */
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if ((IorD == isINSTRUCTION) && ((pAddr & 0x3) != 0))
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if ((IorD == isINSTRUCTION)
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&& ((pAddr & 0x3) != 0)
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&& (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
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SignalException(InstructionFetch);
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else {
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unsigned int index;
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@ -2537,12 +2574,7 @@ SyncOperation(stype)
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that aborts the instruction. The instruction operation pseudocode
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will never see a return from this function call. */
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static void
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#ifdef _MSC_VER
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SignalException (int exception,...)
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#else
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SignalException(exception)
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int exception;
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#endif
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{
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/* Ensure that any active atomic read/modify/write operation will fail: */
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LLBIT = 0;
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@ -3857,15 +3889,31 @@ simulate ()
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callback->printf_filtered(callback,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
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#endif /* DEBUG */
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if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { /* Copy the action of the LW instruction */
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unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
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unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
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uword64 value;
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unsigned int byte;
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paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
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value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
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byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
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instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
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if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
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if ((vaddr & 1) == 0) {
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/* Copy the action of the LW instruction */
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unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
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unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
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uword64 value;
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unsigned int byte;
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paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
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value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
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byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
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instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
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} else {
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/* Copy the action of the LH instruction */
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unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
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unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
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uword64 value;
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unsigned int byte;
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paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
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| (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
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value = LoadMemory(cca, AccessLength_HALFWORD,
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paddr & ~ (uword64) 1,
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vaddr, isINSTRUCTION, isREAL);
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byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
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instruction = ((value >> (8 * byte)) & 0xFFFF);
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}
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} else {
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fprintf(stderr,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC),WORD64LO(PC));
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exit(1);
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@ -3897,7 +3945,10 @@ simulate ()
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/* This is required by exception processing, to ensure that we can
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cope with exceptions in the delay slots of branches that may
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already have changed the PC. */
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PC += 4; /* increment ready for the next fetch */
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if ((vaddr & 1) == 0)
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PC += 4; /* increment ready for the next fetch */
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else
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PC += 2;
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/* NOTE: If we perform a delay slot change to the PC, this
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increment is not requuired. However, it would make the
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simulator more complicated to try and avoid this small hit. */
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