AArch64: Add verifier for By elem Single and Double sized instructions.
The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns.
This commit is contained in:
Tamar Christina
parent
b2abe1bd81
commit
6456d318aa
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@ -1,3 +1,9 @@
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23212
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* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
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* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
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2019-02-07 Eric Botcazou <ebotcazou@adacore.com>
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* config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on
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@ -0,0 +1,40 @@
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#as: -march=armv8.4-a
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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[^:]+:\s+5f909000 fmul s0, s0, v16.s\[0\]
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[^:]+:\s+5ff09000 .inst 0x5ff09000 ; undefined
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[^:]+:\s+5f901000 fmla s0, s0, v16.s\[0\]
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[^:]+:\s+5ff01000 .inst 0x5ff01000 ; undefined
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[^:]+:\s+5f905000 fmls s0, s0, v16.s\[0\]
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[^:]+:\s+5ff05000 .inst 0x5ff05000 ; undefined
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[^:]+:\s+7f909000 fmulx s0, s0, v16.s\[0\]
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[^:]+:\s+7ff09000 .inst 0x7ff09000 ; undefined
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[^:]+:\s+5fd09000 fmul d0, d0, v16.d\[0\]
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[^:]+:\s+5ff09000 .inst 0x5ff09000 ; undefined
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[^:]+:\s+5fd01000 fmla d0, d0, v16.d\[0\]
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[^:]+:\s+5ff01000 .inst 0x5ff01000 ; undefined
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[^:]+:\s+5fd05000 fmls d0, d0, v16.d\[0\]
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[^:]+:\s+5ff05000 .inst 0x5ff05000 ; undefined
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[^:]+:\s+7fd09000 fmulx d0, d0, v16.d\[0\]
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[^:]+:\s+7ff09000 .inst 0x7ff09000 ; undefined
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[^:]+:\s+4f909000 fmul v0.4s, v0.4s, v16.s\[0\]
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[^:]+:\s+4ff09000 .inst 0x4ff09000 ; undefined
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[^:]+:\s+4f901000 fmla v0.4s, v0.4s, v16.s\[0\]
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[^:]+:\s+4ff01000 .inst 0x4ff01000 ; undefined
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[^:]+:\s+4f905000 fmls v0.4s, v0.4s, v16.s\[0\]
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[^:]+:\s+4ff05000 .inst 0x4ff05000 ; undefined
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[^:]+:\s+6f909000 fmulx v0.4s, v0.4s, v16.s\[0\]
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[^:]+:\s+6ff09000 .inst 0x6ff09000 ; undefined
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[^:]+:\s+4fd09000 fmul v0.2d, v0.2d, v16.d\[0\]
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[^:]+:\s+4ff09000 .inst 0x4ff09000 ; undefined
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[^:]+:\s+4fd01000 fmla v0.2d, v0.2d, v16.d\[0\]
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[^:]+:\s+4ff01000 .inst 0x4ff01000 ; undefined
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[^:]+:\s+4fd05000 fmls v0.2d, v0.2d, v16.d\[0\]
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[^:]+:\s+4ff05000 .inst 0x4ff05000 ; undefined
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[^:]+:\s+6fd09000 fmulx v0.2d, v0.2d, v16.d\[0\]
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[^:]+:\s+6ff09000 .inst 0x6ff09000 ; undefined
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@ -0,0 +1,55 @@
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# Generates tests to see if setting bit 22 (sz) and 21 (L) together correctly
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# marks the instruction as undefined. This pattern can't be created by the
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# assembler so instead manually encode it.
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.macro gen_insns opc
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.inst \opc
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.inst (\opc | 0x600000)
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.endm
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# fmul s0, s0, v16.s[0]
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gen_insns 0x5f909000
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# fmla s0, s0, v16.s[0]
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gen_insns 0x5f901000
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# fmls s0, s0, v16.s[0]
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gen_insns 0x5f905000
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# fmulx s0, s0, v16.s[0]
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gen_insns 0x7f909000
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# fmul d0, d0, v16.d[0]
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gen_insns 0x5fd09000
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# fmla d0, d0, v16.d[0]
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gen_insns 0x5fd01000
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# fmls d0, d0, v16.d[0]
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gen_insns 0x5fd05000
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# fmulx d0, d0, v16.d[0]
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gen_insns 0x7fd09000
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# fmul v0.4s, v0.4s, v16.s[0]
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gen_insns 0x4f909000
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# fmla v0.4s, v0.4s, v16.s[0]
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gen_insns 0x4f901000
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# fmls v0.4s, v0.4s, v16.s[0]
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gen_insns 0x4f905000
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# fmulx v0.4s, v0.4s, v16.s[0]
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gen_insns 0x6f909000
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# fmul v0.2d, v0.2d, v16.d[0]
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gen_insns 0x4fd09000
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# fmla v0.2d, v0.2d, v16.d[0]
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gen_insns 0x4fd01000
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# fmls v0.2d, v0.2d, v16.d[0]
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gen_insns 0x4fd05000
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# fmulx v0.2d, v0.2d, v16.d[0]
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gen_insns 0x6fd09000
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@ -1,3 +1,13 @@
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2019-02-07 Tamar Christina <tamar.christina@arm.com>
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PR binutils/23212
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* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
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* aarch64-opc.c (verify_elem_sd): New.
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(fields): Add FLD_sz entr.
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* aarch64-tbl.h (_SIMD_INSN): New.
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(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
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fmulx scalar and vector by element isns.
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2019-02-07 Nick Clifton <nickc@redhat.com>
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* po/sv.po: Updated Swedish translation.
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@ -320,6 +320,7 @@ const aarch64_field fields[] =
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{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
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{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
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{ 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
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{ 22, 1 }, /* sz: 1-bit element size select. */
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};
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enum aarch64_operand_class
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@ -4728,6 +4729,29 @@ verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
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return ERR_OK;
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}
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/* Verifier for vector by element 3 operands functions where the
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conditions `if sz:L == 11 then UNDEFINED` holds. */
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static enum err_type
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verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
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bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
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aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
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aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
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{
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const aarch64_insn undef_pattern = 0x3;
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aarch64_insn value;
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assert (inst->opcode);
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assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
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value = encoding ? inst->value : insn;
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assert (value);
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if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
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return ERR_UND;
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return ERR_OK;
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}
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/* Initialize an instruction sequence insn_sequence with the instruction INST.
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If INST is NULL the given insn_sequence is cleared and the sequence is left
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uninitialized. */
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@ -146,7 +146,8 @@ enum aarch64_field_kind
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FLD_rotate1,
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FLD_rotate2,
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FLD_rotate3,
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FLD_SM3_imm2
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FLD_SM3_imm2,
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FLD_sz
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};
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/* Field description. */
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@ -2239,6 +2239,8 @@ static const aarch64_feature_set aarch64_feature_memtag =
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{ NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
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{ NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER }
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#define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, 0, NULL }
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#define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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@ -2420,11 +2422,11 @@ struct aarch64_opcode aarch64_opcode_table[] =
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SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
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SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
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SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
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SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
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_SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
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SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
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SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
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_SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
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SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
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SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
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_SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
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SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
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SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
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SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
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@ -2434,7 +2436,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
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SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
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SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
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SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
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SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
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_SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
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SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
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RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
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RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
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@ -2748,13 +2750,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
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SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE),
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SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
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SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
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SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
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_SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
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SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
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SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
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_SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
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SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
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SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
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_SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
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SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
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SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
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_SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
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SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
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RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
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RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
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