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x86/Intel: accept "oword ptr" for INVPCID 

The insn is no different in this reagrd from INVEPT and INVVPID.
This commit is contained in:
Jan Beulich 2018-06-01 08:37:24 +02:00 committed by Jan Beulich
parent 030157d8a6
commit 6479571075
10 changed files with 27 additions and 6 deletions
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10
gas/ChangeLog
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@ -1,3 +1,13 @@
2018-06-01 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/invpcid.s,
testsuite/gas/i386/x86-64-invpcid.s: Add test with explicit
"oword ptr".
* testsuite/gas/i386/invpcid.d,
testsuite/gas/i386/invpcid-intel.d,
testsuite/gas/i386/x86-64-invpcid.d,
testsuite/gas/i386/x86-64-invpcid-intel.d: Adjust expectations.
2018-05-30 Amit Pawar <amit.pawar@amd.com>
* config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.

1
gas/testsuite/gas/i386/invpcid-intel.d
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@ -11,4 +11,5 @@ Disassembly of section .text:
0+ <foo>:
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
#pass

1
gas/testsuite/gas/i386/invpcid.d
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@ -10,4 +10,5 @@ Disassembly of section .text:
0+ <foo>:
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
#pass

1
gas/testsuite/gas/i386/invpcid.s
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@ -6,3 +6,4 @@ foo:
.intel_syntax noprefix
invpcid edx,[eax]
invpcid edx,oword ptr [eax]

1
gas/testsuite/gas/i386/x86-64-invpcid-intel.d
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@ -11,4 +11,5 @@ Disassembly of section .text:
0+ <foo>:
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
#pass

1
gas/testsuite/gas/i386/x86-64-invpcid.d
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@ -10,4 +10,5 @@ Disassembly of section .text:
0+ <foo>:
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
#pass

1
gas/testsuite/gas/i386/x86-64-invpcid.s
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@ -6,3 +6,4 @@ foo:
.intel_syntax noprefix
invpcid rdx,[rax]
invpcid rdx,oword ptr [rax]

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-06-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (invpcid): Add Oword.
* i386-tbl.h: Re-generate.
2018-06-01 Alan Modra <amodra@gmail.com>
* sysdep.h (_bfd_error_handler): Don't declare.

4
opcodes/i386-opc.tbl
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@ -1583,8 +1583,8 @@ invvpid, 2, 0x660f3881, None, 3, CpuEPT|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|
// INVPCID instruction
invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex, Reg32 }
invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Unspecified|BaseIndex, Reg64 }
invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
// SSSE3 instructions.

8
opcodes/i386-tbl.h
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@ -20804,12 +20804,12 @@ const insn_template i386_optab[] =
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
@ -20821,12 +20821,12 @@ const insn_template i386_optab[] =
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,