x86/Intel: accept "oword ptr" for INVPCID
The insn is no different in this reagrd from INVEPT and INVVPID.
This commit is contained in:
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030157d8a6
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6479571075
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@ -1,3 +1,13 @@
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2018-06-01 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/invpcid.s,
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testsuite/gas/i386/x86-64-invpcid.s: Add test with explicit
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"oword ptr".
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* testsuite/gas/i386/invpcid.d,
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testsuite/gas/i386/invpcid-intel.d,
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testsuite/gas/i386/x86-64-invpcid.d,
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testsuite/gas/i386/x86-64-invpcid-intel.d: Adjust expectations.
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2018-05-30 Amit Pawar <amit.pawar@amd.com>
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2018-05-30 Amit Pawar <amit.pawar@amd.com>
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* config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
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* config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
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@ -11,4 +11,5 @@ Disassembly of section .text:
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0+ <foo>:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid edx,\[eax\]
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#pass
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#pass
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@ -10,4 +10,5 @@ Disassembly of section .text:
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0+ <foo>:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%eax\),%edx
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#pass
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#pass
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@ -6,3 +6,4 @@ foo:
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.intel_syntax noprefix
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.intel_syntax noprefix
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invpcid edx,[eax]
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invpcid edx,[eax]
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invpcid edx,oword ptr [eax]
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@ -11,4 +11,5 @@ Disassembly of section .text:
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0+ <foo>:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid rdx,\[rax\]
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#pass
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#pass
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@ -10,4 +10,5 @@ Disassembly of section .text:
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0+ <foo>:
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0+ <foo>:
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
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[ ]*[a-f0-9]+: 66 0f 38 82 10 invpcid \(%rax\),%rdx
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#pass
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#pass
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@ -6,3 +6,4 @@ foo:
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.intel_syntax noprefix
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.intel_syntax noprefix
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invpcid rdx,[rax]
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invpcid rdx,[rax]
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invpcid rdx,oword ptr [rax]
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@ -1,3 +1,8 @@
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2018-06-01 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (invpcid): Add Oword.
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* i386-tbl.h: Re-generate.
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2018-06-01 Alan Modra <amodra@gmail.com>
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2018-06-01 Alan Modra <amodra@gmail.com>
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* sysdep.h (_bfd_error_handler): Don't declare.
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* sysdep.h (_bfd_error_handler): Don't declare.
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@ -1583,8 +1583,8 @@ invvpid, 2, 0x660f3881, None, 3, CpuEPT|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|
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// INVPCID instruction
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// INVPCID instruction
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invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex, Reg32 }
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invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
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invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Unspecified|BaseIndex, Reg64 }
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invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
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// SSSE3 instructions.
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// SSSE3 instructions.
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@ -20804,12 +20804,12 @@ const insn_template i386_optab[] =
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 1, 0 } },
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0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0 },
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0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0,
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
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0, 0, 0 } },
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0, 0, 0 } },
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -20821,12 +20821,12 @@ const insn_template i386_optab[] =
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 0, 0 } },
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0, 0, 1, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0 },
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0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
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0, 0, 0 } },
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0, 0, 0 } },
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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