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RISC-V: Add fence.tso instruction 

The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso".  This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.

I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets.  I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.

gas/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * testsuite/gas/riscv/fence-tso.d: New file.
        * testsuite/gas/riscv/fence-tso.s: Likewise.

include/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
        (MASK_FENCE_TSO): Likewise.

opcodes/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
This commit is contained in:
Palmer Dabbelt 2018-10-02 08:26:32 -07:00
parent c1168a2f66
commit 64a336ac13
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7 changed files with 30 additions and 0 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* testsuite/gas/riscv/fence-tso.d: New file.
* testsuite/gas/riscv/fence-tso.s: Likewise.
2018-09-26 Sandra Loosemore <sandra@codesourcery.com>
* testsuite/gas/all/gas.exp: Skip "Output file must be distinct

11
gas/testsuite/gas/riscv/fence-tso.d Normal file
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@ -0,0 +1,11 @@
#as: -march=rv32ic
#objdump: -dr
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <target>:
[ ]+0:[ ]+8330000f[ ]+fence.tso

2
gas/testsuite/gas/riscv/fence-tso.s Normal file
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@ -0,0 +1,2 @@
target:
fence.tso

5
include/ChangeLog
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@ -1,3 +1,8 @@
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
(MASK_FENCE_TSO): Likewise.
2018-10-01 Cupertino Miranda <cmiranda@synopsys.com>
* arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.

2
include/opcode/riscv-opc.h
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@ -141,6 +141,8 @@
#define MASK_FENCE 0x707f
#define MATCH_FENCE_I 0x100f
#define MASK_FENCE_I 0x707f
#define MATCH_FENCE_TSO 0x8330000f
#define MASK_FENCE_TSO 0xfff0707f
#define MATCH_MUL 0x2000033
#define MASK_MUL 0xfe00707f
#define MATCH_MULH 0x2001033

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
* nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions

1
opcodes/riscv-opc.c
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@ -342,6 +342,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"fence", 0, {"I", 0}, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, {"I", 0}, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, {"I", 0}, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
{"fence.tso", 0, {"I", 0}, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS },
{"rdcycle", 0, {"I", 0}, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
{"rdinstret", 0, {"I", 0}, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
{"rdtime", 0, {"I", 0}, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },