Added N step divide routines, courtesy of Sugimoto at NEC.
This commit is contained in:
Nick Clifton
parent
70caad98c1
commit
64ad9cecb6
@ -2,6 +2,9 @@ Wed Aug 20 13:56:35 1997 Nick Clifton <nickc@cygnus.com>
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* simops.c (OP_107E0, OP_107F0, OP_307E0, OP_307F0): Use correct
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interpretation of SR bit in list18 structure.
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start-sanitize-v850eq
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(divn, divun): New functions to perform N step divide functions.
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end-sanitize-v850eq
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start-sanitize-v850eq
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Mon Aug 18 10:59:02 1997 Nick Clifton <nickc@cygnus.com>
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@ -504,7 +504,6 @@ condition_met (unsigned code)
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return 1;
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}
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/* start-sanitize-v850e */
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static unsigned long
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Add32 (unsigned long a1, unsigned long a2, int * carry)
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{
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@ -576,7 +575,6 @@ Multiply64 (boolean sign, unsigned long op0)
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return;
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}
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/* end-sanitize-v850e */
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/* sld.b */
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@ -2427,6 +2425,19 @@ OP_E607E0 (void)
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return 4;
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}
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/* mulu reg1, reg2, reg3 */
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int
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OP_22207E0 (void)
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{
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trace_input ("mulu", OP_REG_REG_REG, 0);
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Multiply64 (false, State.regs[ OP[0] ]);
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trace_output (OP_REG_REG_REG);
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return 4;
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}
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/* start-sanitize-v850e */
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#define BIT_CHANGE_OP( name, binop ) \
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@ -2485,32 +2496,196 @@ OP_20007E0 (void)
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
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static void
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divun
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(
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unsigned int N,
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unsigned long int als,
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unsigned long int sfi,
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unsigned long int * quotient_ptr,
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unsigned long int * remainder_ptr,
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boolean * overflow_ptr
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)
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{
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unsigned long ald = sfi >> N - 1;
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unsigned long alo = als;
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unsigned int Q = 1;
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unsigned int C;
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unsigned int S = 0;
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unsigned int i;
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unsigned int R1 = 1;
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unsigned int OV;
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unsigned int DBZ = (als == 0) ? 1 : 0;
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unsigned long alt = Q ? ~als : als;
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/* 1st Loop */
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alo = ald + alt + Q;
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C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
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C = C ^ Q;
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Q = ~(C ^ S) & 1;
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R1 = (alo == 0) ? 0 : (R1 & Q);
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if ((S ^ (alo>>31)) && !C)
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{
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DBZ = 1;
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}
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S = alo >> 31;
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sfi = (sfi << (32-N+1)) | Q;
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ald = (alo << 1) | (sfi >> 31);
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/* 2nd - N-1th Loop */
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for (i = 2; i < N; i++)
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{
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alt = Q ? ~als : als;
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alo = ald + alt + Q;
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C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
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C = C ^ Q;
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Q = ~(C ^ S) & 1;
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R1 = (alo == 0) ? 0 : (R1 & Q);
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if ((S ^ (alo>>31)) && !C && !DBZ)
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{
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DBZ = 1;
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}
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S = alo >> 31;
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sfi = (sfi << 1) | Q;
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ald = (alo << 1) | (sfi >> 31);
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}
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/* Nth Loop */
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alt = Q ? ~als : als;
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alo = ald + alt + Q;
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C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
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C = C ^ Q;
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Q = ~(C ^ S) & 1;
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R1 = (alo == 0) ? 0 : (R1 & Q);
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if ((S ^ (alo>>31)) && !C)
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{
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DBZ = 1;
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}
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* quotient_ptr = (sfi << 1) | Q;
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* remainder_ptr = Q ? alo : (alo + als);
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* overflow_ptr = DBZ | R1;
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}
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/* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
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static void
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divn
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(
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unsigned int N,
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unsigned long int als,
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unsigned long int sfi,
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signed long int * quotient_ptr,
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signed long int * remainder_ptr,
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boolean * overflow_ptr
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)
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{
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unsigned long ald = (signed long) sfi >> (N - 1);
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unsigned long alo = als;
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unsigned int SS = als >> 31;
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unsigned int SD = sfi >> 31;
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unsigned int R1 = 1;
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unsigned int OV;
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unsigned int DBZ = als == 0 ? 1 : 0;
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unsigned int Q = ~(SS ^ SD) & 1;
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unsigned int C;
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unsigned int S;
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unsigned int i;
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unsigned long alt = Q ? ~als : als;
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/* 1st Loop */
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alo = ald + alt + Q;
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C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
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Q = C ^ SS;
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R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
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S = alo >> 31;
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sfi = (sfi << (32-N+1)) | Q;
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ald = (alo << 1) | (sfi >> 31);
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if ((alo >> 31) ^ (ald >> 31))
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{
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DBZ = 1;
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}
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/* 2nd - N-1th Loop */
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for (i = 2; i < N; i++)
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{
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alt = Q ? ~als : als;
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alo = ald + alt + Q;
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C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
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Q = C ^ SS;
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R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
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S = alo >> 31;
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sfi = (sfi << 1) | Q;
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ald = (alo << 1) | (sfi >> 31);
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if ((alo >> 31) ^ (ald >> 31))
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{
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DBZ = 1;
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}
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}
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/* Nth Loop */
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alt = Q ? ~als : als;
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alo = ald + alt + Q;
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C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
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Q = C ^ SS;
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R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
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sfi = (sfi << (32-N+1));
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ald = alo;
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/* End */
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if (alo != 0)
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{
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alt = Q ? ~als : als;
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alo = ald + alt + Q;
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}
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R1 = R1 & ((~alo >> 31) ^ SD);
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if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
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if (N != 32)
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ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
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else
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ald = sfi = sfi | Q;
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OV = DBZ | ((alo == 0) ? 0 : R1);
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* remainder_ptr = alo;
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/* Adj */
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if ((alo != 0) && ((SS ^ SD) ^ R1) || (alo == 0) && (SS ^ R1))
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alo = ald + 1;
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else
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alo = ald;
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OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
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* quotient_ptr = alo;
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* overflow_ptr = OV;
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}
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/* sdivun imm5, reg1, reg2, reg3 */
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int
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OP_1C207E0 (void)
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{
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unsigned long long int quotient;
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unsigned long long int remainder;
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unsigned long long int divisor;
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unsigned long long int dividend;
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boolean overflow = false;
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unsigned int imm5;
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unsigned long int quotient;
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unsigned long int remainder;
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unsigned long int divide_by;
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unsigned long int divide_this;
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boolean overflow = false;
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unsigned int imm5;
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trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
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imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
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divisor = State.regs[ OP[0] ] << imm5;
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dividend = State.regs[ OP[1] ];
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divide_by = State.regs[ OP[0] ];
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divide_this = State.regs[ OP[1] ] << imm5;
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State.regs[ OP[1] ] = quotient = dividend / divisor;
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State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
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divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
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if (divisor == 0)
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{
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overflow = true;
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quotient = dividend;
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}
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State.regs[ OP[1] ] = quotient;
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State.regs[ OP[2] >> 11 ] = remainder;
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/* Set condition codes. */
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PSW &= ~(PSW_Z | PSW_S | PSW_OV);
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@ -2527,28 +2702,24 @@ OP_1C207E0 (void)
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int
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OP_1C007E0 (void)
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{
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signed long long int quotient;
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signed long long int remainder;
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signed long long int divisor;
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signed long long int dividend;
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boolean overflow = false;
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unsigned int imm5;
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signed long int quotient;
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signed long int remainder;
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signed long int divide_by;
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signed long int divide_this;
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boolean overflow = false;
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unsigned int imm5;
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trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
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imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
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divisor = State.regs[ OP[0] ] << imm5;
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dividend = State.regs[ OP[1] ];
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divide_by = State.regs[ OP[0] ];
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divide_this = State.regs[ OP[1] ] << imm5;
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State.regs[ OP[1] ] = quotient = dividend / divisor;
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State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
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divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
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if (divisor == 0)
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{
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overflow = true;
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quotient = dividend;
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}
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State.regs[ OP[1] ] = quotient;
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State.regs[ OP[2] >> 11 ] = remainder;
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/* Set condition codes. */
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PSW &= ~(PSW_Z | PSW_S | PSW_OV);
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@ -2566,28 +2737,24 @@ OP_1C007E0 (void)
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int
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OP_18207E0 (void)
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{
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unsigned long long int quotient;
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unsigned long long int remainder;
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unsigned long long int divisor;
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unsigned long long int dividend;
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boolean overflow = false;
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unsigned int imm5;
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unsigned long int quotient;
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unsigned long int remainder;
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unsigned long int divide_by;
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unsigned long int divide_this;
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boolean overflow = false;
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unsigned int imm5;
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trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
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imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
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divisor = State.regs[ OP[0] ] << imm5;
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dividend = State.regs[ OP[1] ] & 0xffff;
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divide_by = State.regs[ OP[0] ] & 0xffff;
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divide_this = State.regs[ OP[1] ] << imm5;
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State.regs[ OP[1] ] = quotient = dividend / divisor;
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State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
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divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
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if (divisor == 0)
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{
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overflow = true;
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quotient = dividend;
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}
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State.regs[ OP[1] ] = quotient;
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State.regs[ OP[2] >> 11 ] = remainder;
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/* Set condition codes. */
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PSW &= ~(PSW_Z | PSW_S | PSW_OV);
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@ -2604,28 +2771,24 @@ OP_18207E0 (void)
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int
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OP_18007E0 (void)
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{
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signed long long int quotient;
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signed long long int remainder;
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signed long long int divisor;
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signed long long int dividend;
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boolean overflow = false;
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unsigned int imm5;
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signed long int quotient;
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signed long int remainder;
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signed long int divide_by;
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signed long int divide_this;
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boolean overflow = false;
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unsigned int imm5;
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trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
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imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
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divisor = State.regs[ OP[0] ] << imm5;
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dividend = SEXT16 (State.regs[ OP[1] ]);
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divide_by = SEXT16 (State.regs[ OP[0] ]);
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divide_this = State.regs[ OP[1] ] << imm5;
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State.regs[ OP[1] ] = quotient = dividend / divisor;
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State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
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divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
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if (divisor == 0)
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{
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overflow = true;
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quotient = dividend;
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}
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State.regs[ OP[1] ] = quotient;
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State.regs[ OP[2] >> 11 ] = remainder;
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/* Set condition codes. */
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PSW &= ~(PSW_Z | PSW_S | PSW_OV);
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@ -2642,14 +2805,13 @@ OP_18007E0 (void)
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/* start-sanitize-v850e */
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/* divu reg1, reg2, reg3 */
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/* divun imm5, reg1, reg2, reg3 */
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int
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OP_2C207E0 (void)
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{
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unsigned long int quotient;
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unsigned long int remainder;
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unsigned long int divisor;
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unsigned long int dividend;
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unsigned long int divide_by;
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unsigned long int divide_this;
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boolean overflow = false;
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if ((OP[3] & 0x3c0000) == 0)
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@ -2658,17 +2820,17 @@ OP_2C207E0 (void)
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/* Compute the result. */
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divisor = State.regs[ OP[0] ];
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dividend = State.regs[ OP[1] ];
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divide_by = State.regs[ OP[0] ];
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divide_this = State.regs[ OP[1] ];
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if (divisor == 0)
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if (divide_by == 0)
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{
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overflow = true;
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divisor = 1;
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divide_by = 1;
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}
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State.regs[ OP[1] ] = quotient = dividend / divisor;
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State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
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State.regs[ OP[1] ] = quotient = divide_this / divide_by;
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State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
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/* Set condition codes. */
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PSW &= ~(PSW_Z | PSW_S | PSW_OV);
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@ -2679,6 +2841,7 @@ OP_2C207E0 (void)
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trace_output (OP_REG_REG_REG);
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}
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/* start-sanitize-v850eq */
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/* divun imm5, reg1, reg2, reg3 */
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else
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{
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unsigned int imm5;
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@ -2687,19 +2850,13 @@ OP_2C207E0 (void)
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imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
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divisor = State.regs[ OP[0] ];
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dividend = State.regs[ OP[1] ];
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divide_by = State.regs[ OP[0] ];
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divide_this = State.regs[ OP[1] ];
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State.regs[ OP[1] ] = quotient = dividend / divisor;
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State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
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divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
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if ((divisor == 0)
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|| (quotient > (1 << imm5))
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|| (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
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{
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overflow = true;
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quotient = dividend;
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}
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State.regs[ OP[1] ] = quotient;
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State.regs[ OP[2] >> 11 ] = remainder;
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/* Set condition codes. */
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PSW &= ~(PSW_Z | PSW_S | PSW_OV);
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@ -2715,14 +2872,13 @@ OP_2C207E0 (void)
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}
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/* div reg1, reg2, reg3 */
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/* divn imm5, reg1, reg2, reg3 */
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int
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OP_2C007E0 (void)
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{
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signed long int quotient;
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signed long int remainder;
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signed long int divisor;
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signed long int dividend;
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signed long int divide_by;
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signed long int divide_this;
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boolean overflow = false;
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if ((OP[3] & 0x3c0000) == 0)
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@ -2731,17 +2887,17 @@ OP_2C007E0 (void)
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/* Compute the result. */
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divisor = State.regs[ OP[0] ];
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dividend = State.regs[ OP[1] ];
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divide_by = State.regs[ OP[0] ];
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divide_this = State.regs[ OP[1] ];
|
||||
|
||||
if (divisor == 0 || (divisor == -1 && dividend == (1 << 31)))
|
||||
if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
|
||||
{
|
||||
overflow = true;
|
||||
divisor = 1;
|
||||
overflow = true;
|
||||
divide_by = 1;
|
||||
}
|
||||
|
||||
State.regs[ OP[1] ] = quotient = dividend / divisor;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
|
||||
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
|
||||
|
||||
/* Set condition codes. */
|
||||
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||
@ -2753,6 +2909,7 @@ OP_2C007E0 (void)
|
||||
trace_output (OP_REG_REG_REG);
|
||||
}
|
||||
/* start-sanitize-v850eq */
|
||||
/* divn imm5, reg1, reg2, reg3 */
|
||||
else
|
||||
{
|
||||
unsigned int imm5;
|
||||
@ -2761,20 +2918,13 @@ OP_2C007E0 (void)
|
||||
|
||||
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
|
||||
|
||||
divisor = State.regs[ OP[0] ];
|
||||
dividend = State.regs[ OP[1] ];
|
||||
divide_by = State.regs[ OP[0] ];
|
||||
divide_this = State.regs[ OP[1] ];
|
||||
|
||||
State.regs[ OP[1] ] = quotient = dividend / divisor;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
|
||||
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
|
||||
|
||||
if ((divisor == 0)
|
||||
|| (quotient > (1 << imm5))
|
||||
|| (divisor == -1 && dividend == (1 << 31))
|
||||
|| (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
|
||||
{
|
||||
overflow = true;
|
||||
quotient = dividend;
|
||||
}
|
||||
State.regs[ OP[1] ] = quotient;
|
||||
State.regs[ OP[2] >> 11 ] = remainder;
|
||||
|
||||
/* Set condition codes. */
|
||||
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||
@ -2791,14 +2941,13 @@ OP_2C007E0 (void)
|
||||
}
|
||||
|
||||
/* divhu reg1, reg2, reg3 */
|
||||
/* divhun imm5, reg1, reg2, reg3 */
|
||||
int
|
||||
OP_28207E0 (void)
|
||||
{
|
||||
unsigned long int quotient;
|
||||
unsigned long int remainder;
|
||||
unsigned long int divisor;
|
||||
unsigned long int dividend;
|
||||
unsigned long int divide_by;
|
||||
unsigned long int divide_this;
|
||||
boolean overflow = false;
|
||||
|
||||
if ((OP[3] & 0x3c0000) == 0)
|
||||
@ -2807,17 +2956,17 @@ OP_28207E0 (void)
|
||||
|
||||
/* Compute the result. */
|
||||
|
||||
divisor = State.regs[ OP[0] ];
|
||||
dividend = State.regs[ OP[1] ] & 0xffff;
|
||||
divide_by = State.regs[ OP[0] ] & 0xffff;
|
||||
divide_this = State.regs[ OP[1] ];
|
||||
|
||||
if (divisor == 0)
|
||||
if (divide_by == 0)
|
||||
{
|
||||
overflow = true;
|
||||
divisor = 1;
|
||||
divide_by = 1;
|
||||
}
|
||||
|
||||
State.regs[ OP[1] ] = quotient = dividend / divisor;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
|
||||
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
|
||||
|
||||
/* Set condition codes. */
|
||||
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||
@ -2828,6 +2977,7 @@ OP_28207E0 (void)
|
||||
trace_output (OP_REG_REG_REG);
|
||||
}
|
||||
/* start-sanitize-v850eq */
|
||||
/* divhun imm5, reg1, reg2, reg3 */
|
||||
else
|
||||
{
|
||||
unsigned int imm5;
|
||||
@ -2836,19 +2986,13 @@ OP_28207E0 (void)
|
||||
|
||||
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
|
||||
|
||||
divisor = State.regs[ OP[0] ];
|
||||
dividend = State.regs[ OP[1] ] & 0xffff;
|
||||
divide_by = State.regs[ OP[0] ] & 0xffff;
|
||||
divide_this = State.regs[ OP[1] ];
|
||||
|
||||
State.regs[ OP[1] ] = quotient = dividend / divisor;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
|
||||
divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
|
||||
|
||||
if ((divisor == 0)
|
||||
|| (quotient > (1 << imm5))
|
||||
|| (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
|
||||
{
|
||||
overflow = true;
|
||||
quotient = dividend;
|
||||
}
|
||||
State.regs[ OP[1] ] = quotient;
|
||||
State.regs[ OP[2] >> 11 ] = remainder;
|
||||
|
||||
/* Set condition codes. */
|
||||
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||
@ -2864,14 +3008,13 @@ OP_28207E0 (void)
|
||||
}
|
||||
|
||||
/* divh reg1, reg2, reg3 */
|
||||
/* divhn imm5, reg1, reg2, reg3 */
|
||||
int
|
||||
OP_28007E0 (void)
|
||||
{
|
||||
signed long int quotient;
|
||||
signed long int remainder;
|
||||
signed long int divisor;
|
||||
signed long int dividend;
|
||||
signed long int divide_by;
|
||||
signed long int divide_this;
|
||||
boolean overflow = false;
|
||||
|
||||
if ((OP[3] & 0x3c0000) == 0)
|
||||
@ -2880,17 +3023,17 @@ OP_28007E0 (void)
|
||||
|
||||
/* Compute the result. */
|
||||
|
||||
divisor = State.regs[ OP[0] ];
|
||||
dividend = SEXT16 (State.regs[ OP[1] ]);
|
||||
divide_by = State.regs[ OP[0] ];
|
||||
divide_this = SEXT16 (State.regs[ OP[1] ]);
|
||||
|
||||
if (divisor == 0 || (divisor == -1 && dividend == (1 << 31)))
|
||||
if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
|
||||
{
|
||||
overflow = true;
|
||||
divisor = 1;
|
||||
divide_by = 1;
|
||||
}
|
||||
|
||||
State.regs[ OP[1] ] = quotient = dividend / divisor;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
|
||||
State.regs[ OP[1] ] = quotient = divide_this / divide_by;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
|
||||
|
||||
/* Set condition codes. */
|
||||
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||
@ -2902,6 +3045,7 @@ OP_28007E0 (void)
|
||||
trace_output (OP_REG_REG_REG);
|
||||
}
|
||||
/* start-sanitize-v850eq */
|
||||
/* divhn imm5, reg1, reg2, reg3 */
|
||||
else
|
||||
{
|
||||
unsigned int imm5;
|
||||
@ -2910,20 +3054,13 @@ OP_28007E0 (void)
|
||||
|
||||
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
|
||||
|
||||
divisor = State.regs[ OP[0] ];
|
||||
dividend = SEXT16 (State.regs[ OP[1] ]);
|
||||
divide_by = SEXT16 (State.regs[ OP[0] ]);
|
||||
divide_this = State.regs[ OP[1] ];
|
||||
|
||||
State.regs[ OP[1] ] = quotient = dividend / divisor;
|
||||
State.regs[ OP[2] >> 11 ] = remainder = dividend % divisor;
|
||||
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
|
||||
|
||||
if ((divisor == 0)
|
||||
|| (quotient > (1 << imm5))
|
||||
|| (divisor == -1 && dividend == (1 << 31))
|
||||
|| (quotient < (((imm5 & 1) ? 1 : -1) << imm5)))
|
||||
{
|
||||
overflow = true;
|
||||
quotient = dividend;
|
||||
}
|
||||
State.regs[ OP[1] ] = quotient;
|
||||
State.regs[ OP[2] >> 11 ] = remainder;
|
||||
|
||||
/* Set condition codes. */
|
||||
PSW &= ~(PSW_Z | PSW_S | PSW_OV);
|
||||
@ -2952,23 +3089,6 @@ OP_24207E0 (void)
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* end-sanitize-v850e */
|
||||
|
||||
/* mulu reg1, reg2, reg3 */
|
||||
int
|
||||
OP_22207E0 (void)
|
||||
{
|
||||
trace_input ("mulu", OP_REG_REG_REG, 0);
|
||||
|
||||
Multiply64 (false, State.regs[ OP[0] ]);
|
||||
|
||||
trace_output (OP_REG_REG_REG);
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* start-sanitize-v850e */
|
||||
|
||||
/* mul imm9, reg2, reg3 */
|
||||
int
|
||||
OP_24007E0 (void)
|
||||
@ -3290,6 +3410,59 @@ OP_30780 (void)
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* sld.hu */
|
||||
int
|
||||
OP_70 (void)
|
||||
{
|
||||
unsigned long result;
|
||||
|
||||
result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
|
||||
|
||||
/* start-sanitize-v850eq */
|
||||
#ifdef ARCH_v850eq
|
||||
trace_input ("sld.h", OP_LOAD16, 2);
|
||||
|
||||
State.regs[ OP[1] ] = SEXT16 (result);
|
||||
#else
|
||||
/* end-sanitize-v850eq */
|
||||
trace_input ("sld.hu", OP_LOAD16, 2);
|
||||
|
||||
State.regs[ OP[1] ] = result;
|
||||
/* start-sanitize-v850eq */
|
||||
#endif
|
||||
/* end-sanitize-v850eq */
|
||||
|
||||
trace_output (OP_LOAD16);
|
||||
|
||||
return 2;
|
||||
}
|
||||
|
||||
/* cmov reg1, reg2, reg3 */
|
||||
int
|
||||
OP_32007E0 (void)
|
||||
{
|
||||
trace_input ("cmov", OP_REG_REG_REG, 0);
|
||||
|
||||
State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
|
||||
|
||||
trace_output (OP_REG_REG_REG);
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* mul reg1, reg2, reg3 */
|
||||
int
|
||||
OP_22007E0 (void)
|
||||
{
|
||||
trace_input ("mul", OP_REG_REG_REG, 0);
|
||||
|
||||
Multiply64 (true, State.regs[ OP[0] ]);
|
||||
|
||||
trace_output (OP_REG_REG_REG);
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* end-sanitize-v850e */
|
||||
/* start-sanitize-v850eq */
|
||||
|
||||
@ -3409,59 +3582,3 @@ OP_307E0 (void)
|
||||
}
|
||||
|
||||
/* end-sanitize-v850eq */
|
||||
/* start-sanitize-v850e */
|
||||
|
||||
/* sld.hu */
|
||||
int
|
||||
OP_70 (void)
|
||||
{
|
||||
unsigned long result;
|
||||
|
||||
result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
|
||||
|
||||
/* start-sanitize-v850eq */
|
||||
#ifdef ARCH_v850eq
|
||||
trace_input ("sld.h", OP_LOAD16, 2);
|
||||
|
||||
State.regs[ OP[1] ] = SEXT16 (result);
|
||||
#else
|
||||
/* end-sanitize-v850eq */
|
||||
trace_input ("sld.hu", OP_LOAD16, 2);
|
||||
|
||||
State.regs[ OP[1] ] = result;
|
||||
/* start-sanitize-v850eq */
|
||||
#endif
|
||||
/* end-sanitize-v850eq */
|
||||
|
||||
trace_output (OP_LOAD16);
|
||||
|
||||
return 2;
|
||||
}
|
||||
|
||||
/* cmov reg1, reg2, reg3 */
|
||||
int
|
||||
OP_32007E0 (void)
|
||||
{
|
||||
trace_input ("cmov", OP_REG_REG_REG, 0);
|
||||
|
||||
State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
|
||||
|
||||
trace_output (OP_REG_REG_REG);
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* mul reg1, reg2, reg3 */
|
||||
int
|
||||
OP_22007E0 (void)
|
||||
{
|
||||
trace_input ("mul", OP_REG_REG_REG, 0);
|
||||
|
||||
Multiply64 (true, State.regs[ OP[0] ]);
|
||||
|
||||
trace_output (OP_REG_REG_REG);
|
||||
|
||||
return 4;
|
||||
}
|
||||
|
||||
/* end-sanitize-v850e */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user