aclocal.m4: Don't enable inlining when cross-compiling.
mips/*: Tune mips simulator - allow all memory transfer code to be inlined.
This commit is contained in:
parent
24a385253d
commit
64ed8b6a8c
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@ -1,8 +1,12 @@
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Sat Apr 4 23:24:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* aclocal.m4 (sim-inline): By default, disable sim-inline when
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cross compiling.
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Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
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Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* aclocal.m4 (sim-cflags): Add -fomit-frame-pointer to defaults.
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* aclocal.m4 (sim-cflags): Add -fomit-frame-pointer to defaults.
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(sim-inline): Update to match sim-inline.[hc]
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(sim-inline): Update to match sim-inline.[hc]
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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* Make-common.in (sim_main_headers): Add sim-inline.h
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* Make-common.in (sim_main_headers): Add sim-inline.h
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@ -1,3 +1,21 @@
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Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* Makefile.in (SIM_OBJS): Add sim-main.o.
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* sim-main.h (address_translation, load_memory, store_memory,
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cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
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as INLINE_SIM_MAIN.
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(pr_addr, pr_uword64): Declare.
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(sim-main.c): Include when H_REVEALS_MODULE_P.
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* interp.c (address_translation, load_memory, store_memory,
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cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
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from here.
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* sim-main.c: To here. Fix compilation problems.
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* configure.in: Enable inlining.
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* configure: Re-config.
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Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
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Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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@ -53,6 +53,7 @@ SIM_OBJS = \
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$(SIM_NEW_COMMON_OBJS) \
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$(SIM_NEW_COMMON_OBJS) \
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$(MIPS_EXTRA_OBJS) \
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$(MIPS_EXTRA_OBJS) \
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interp.o \
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interp.o \
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sim-main.o \
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sim-hload.o \
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sim-hload.o \
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sim-engine.o \
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sim-engine.o \
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sim-stop.o \
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sim-stop.o \
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@ -118,7 +119,7 @@ getopt1.o: $(srcdir)/../../libiberty/getopt1.c
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../igen/igen:
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../igen/igen:
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cd ../igen && $(MAKE)
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cd ../igen && $(MAKE)
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IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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IGEN_TRACE= -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries
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IGEN_INSN=$(srcdir)/mips.igen
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IGEN_INSN=$(srcdir)/mips.igen
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IGEN_DC=$(srcdir)/mips.dc
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IGEN_DC=$(srcdir)/mips.dc
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M16_DC=$(srcdir)/m16.dc
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M16_DC=$(srcdir)/m16.dc
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@ -133,7 +134,8 @@ IGEN_INCLUDE=\
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$(start-sanitize-vr4320) \
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$(start-sanitize-vr4320) \
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$(srcdir)/vr4320.igen \
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$(srcdir)/vr4320.igen \
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$(end-sanitize-vr4320) \
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$(end-sanitize-vr4320) \
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$(srcdir)/m16.igen
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$(srcdir)/m16.igen \
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$(srcdir)/tx.igen
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SIM_IGEN_ALL = tmp-igen
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SIM_IGEN_ALL = tmp-igen
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@ -211,11 +213,11 @@ tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
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$(srcdir)/../../move-if-change tmp-irun.c irun.c
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$(srcdir)/../../move-if-change tmp-irun.c irun.c
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touch tmp-igen
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touch tmp-igen
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semantics.o: sim-main.h $(SIM_EXTRA_DEPS)
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semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
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engine.o: sim-main.h $(SIM_EXTRA_DEPS)
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engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
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support.o: sim-main.h $(SIM_EXTRA_DEPS)
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support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
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idecode.o: sim-main.h $(SIM_EXTRA_DEPS)
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idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
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itable.o: sim-main.h $(SIM_EXTRA_DEPS)
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itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
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@ -1491,7 +1491,7 @@ sim_link_links="${sim_link_links} targ-vals.def"
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default_sim_inline="-DDEFAULT_INLINE=0"
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default_sim_inline=""
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# Check whether --enable-sim-inline or --disable-sim-inline was given.
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# Check whether --enable-sim-inline or --disable-sim-inline was given.
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if test "${enable_sim_inline+set}" = set; then
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if test "${enable_sim_inline+set}" = set; then
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enableval="$enable_sim_inline"
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enableval="$enable_sim_inline"
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@ -1520,13 +1520,18 @@ if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
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echo "Setting inline flags = $sim_inline" 6>&1
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echo "Setting inline flags = $sim_inline" 6>&1
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fi
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fi
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else
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else
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if test "x$cross_compiling" = "xno"; then
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if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
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if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
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sim_inline="${default_sim_inline}"
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sim_inline="${default_sim_inline}"
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if test x"$silent" != x"yes"; then
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if test x"$silent" != x"yes"; then
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echo "Setting inline flags = $sim_inline" 6>&1
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echo "Setting inline flags = $sim_inline" 6>&1
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fi
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else
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sim_inline=""
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fi
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fi
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else
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else
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sim_inline=""
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sim_inline="-DDEFAULT_INLINE=0"
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fi
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fi
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fi
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fi
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@ -1594,14 +1599,14 @@ else
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if test "x$cross_compiling" = "xno"; then
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if test "x$cross_compiling" = "xno"; then
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echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
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echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
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echo "configure:1598: checking whether byte ordering is bigendian" >&5
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echo "configure:1603: checking whether byte ordering is bigendian" >&5
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if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
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if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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echo $ac_n "(cached) $ac_c" 1>&6
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else
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else
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ac_cv_c_bigendian=unknown
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ac_cv_c_bigendian=unknown
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# See if sys/param.h defines the BYTE_ORDER macro.
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# See if sys/param.h defines the BYTE_ORDER macro.
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cat > conftest.$ac_ext <<EOF
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cat > conftest.$ac_ext <<EOF
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#line 1605 "configure"
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#line 1610 "configure"
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#include "confdefs.h"
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#include "confdefs.h"
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#include <sys/types.h>
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/param.h>
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@ -1612,11 +1617,11 @@ int main() {
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#endif
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#endif
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; return 0; }
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; return 0; }
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EOF
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EOF
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if { (eval echo configure:1616: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
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if { (eval echo configure:1621: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
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rm -rf conftest*
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rm -rf conftest*
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# It does; now see whether it defined to BIG_ENDIAN or not.
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# It does; now see whether it defined to BIG_ENDIAN or not.
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cat > conftest.$ac_ext <<EOF
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cat > conftest.$ac_ext <<EOF
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#line 1620 "configure"
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#line 1625 "configure"
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#include "confdefs.h"
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#include "confdefs.h"
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#include <sys/types.h>
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/param.h>
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@ -1627,7 +1632,7 @@ int main() {
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#endif
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#endif
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; return 0; }
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; return 0; }
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EOF
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EOF
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if { (eval echo configure:1631: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
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if { (eval echo configure:1636: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
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rm -rf conftest*
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rm -rf conftest*
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ac_cv_c_bigendian=yes
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ac_cv_c_bigendian=yes
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else
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else
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@ -1647,7 +1652,7 @@ if test "$cross_compiling" = yes; then
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{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
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{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
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else
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else
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cat > conftest.$ac_ext <<EOF
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cat > conftest.$ac_ext <<EOF
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#line 1651 "configure"
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#line 1656 "configure"
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#include "confdefs.h"
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#include "confdefs.h"
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main () {
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main () {
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/* Are we little or big endian? From Harbison&Steele. */
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/* Are we little or big endian? From Harbison&Steele. */
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@ -1660,7 +1665,7 @@ main () {
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exit (u.c[sizeof (long) - 1] == 1);
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exit (u.c[sizeof (long) - 1] == 1);
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}
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}
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EOF
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EOF
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if { (eval echo configure:1664: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
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if { (eval echo configure:1669: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
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then
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then
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ac_cv_c_bigendian=no
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ac_cv_c_bigendian=no
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else
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else
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@ -2092,7 +2097,7 @@ esac
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# Uses ac_ vars as temps to allow command line to override cache and checks.
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# Uses ac_ vars as temps to allow command line to override cache and checks.
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# --without-x overrides everything else, but does not touch the cache.
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# --without-x overrides everything else, but does not touch the cache.
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echo $ac_n "checking for X""... $ac_c" 1>&6
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echo $ac_n "checking for X""... $ac_c" 1>&6
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echo "configure:2096: checking for X" >&5
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echo "configure:2101: checking for X" >&5
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# Check whether --with-x or --without-x was given.
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# Check whether --with-x or --without-x was given.
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if test "${with_x+set}" = set; then
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if test "${with_x+set}" = set; then
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# First, try using that file with no special directory specified.
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# First, try using that file with no special directory specified.
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cat > conftest.$ac_ext <<EOF
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cat > conftest.$ac_ext <<EOF
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#line 2158 "configure"
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#line 2163 "configure"
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#include "confdefs.h"
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#include "confdefs.h"
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#include <$x_direct_test_include>
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#include <$x_direct_test_include>
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EOF
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:2163: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:2168: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out`
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ac_err=`grep -v '^ *+' conftest.out`
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if test -z "$ac_err"; then
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if test -z "$ac_err"; then
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rm -rf conftest*
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rm -rf conftest*
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@ -2228,14 +2233,14 @@ if test "$ac_x_libraries" = NO; then
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ac_save_LIBS="$LIBS"
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ac_save_LIBS="$LIBS"
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LIBS="-l$x_direct_test_library $LIBS"
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LIBS="-l$x_direct_test_library $LIBS"
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cat > conftest.$ac_ext <<EOF
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cat > conftest.$ac_ext <<EOF
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#line 2232 "configure"
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#line 2237 "configure"
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#include "confdefs.h"
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#include "confdefs.h"
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int main() {
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int main() {
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${x_direct_test_function}()
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${x_direct_test_function}()
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; return 0; }
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; return 0; }
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EOF
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EOF
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if { (eval echo configure:2239: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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if { (eval echo configure:2244: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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rm -rf conftest*
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rm -rf conftest*
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LIBS="$ac_save_LIBS"
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LIBS="$ac_save_LIBS"
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# We can link X programs with no special library path.
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# We can link X programs with no special library path.
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do
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do
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ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
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ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
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echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
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echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
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echo "configure:2346: checking for $ac_hdr" >&5
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echo "configure:2351: checking for $ac_hdr" >&5
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if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
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if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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echo $ac_n "(cached) $ac_c" 1>&6
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else
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else
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cat > conftest.$ac_ext <<EOF
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cat > conftest.$ac_ext <<EOF
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#line 2351 "configure"
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#line 2356 "configure"
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#include "confdefs.h"
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#include "confdefs.h"
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#include <$ac_hdr>
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#include <$ac_hdr>
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EOF
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:2356: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:2361: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out`
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ac_err=`grep -v '^ *+' conftest.out`
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if test -z "$ac_err"; then
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if test -z "$ac_err"; then
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rm -rf conftest*
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rm -rf conftest*
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@ -2379,7 +2384,7 @@ fi
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done
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done
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echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
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echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
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echo "configure:2383: checking for fabs in -lm" >&5
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echo "configure:2388: checking for fabs in -lm" >&5
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ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
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ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
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if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
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if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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echo $ac_n "(cached) $ac_c" 1>&6
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@ -2387,7 +2392,7 @@ else
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ac_save_LIBS="$LIBS"
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ac_save_LIBS="$LIBS"
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LIBS="-lm $LIBS"
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LIBS="-lm $LIBS"
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cat > conftest.$ac_ext <<EOF
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cat > conftest.$ac_ext <<EOF
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#line 2391 "configure"
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#line 2396 "configure"
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#include "confdefs.h"
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#include "confdefs.h"
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/* Override any gcc2 internal prototype to avoid an error. */
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/* Override any gcc2 internal prototype to avoid an error. */
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/* We use char because int might match the return type of a gcc2
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/* We use char because int might match the return type of a gcc2
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@ -2398,7 +2403,7 @@ int main() {
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fabs()
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fabs()
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; return 0; }
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; return 0; }
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EOF
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EOF
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if { (eval echo configure:2402: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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if { (eval echo configure:2407: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
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rm -rf conftest*
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rm -rf conftest*
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eval "ac_cv_lib_$ac_lib_var=yes"
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eval "ac_cv_lib_$ac_lib_var=yes"
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else
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else
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@ -2428,12 +2433,12 @@ fi
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for ac_func in aint anint sqrt
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for ac_func in aint anint sqrt
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do
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do
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echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
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echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
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echo "configure:2432: checking for $ac_func" >&5
|
echo "configure:2437: checking for $ac_func" >&5
|
||||||
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
else
|
else
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 2437 "configure"
|
#line 2442 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
/* System header to define __stub macros and hopefully few prototypes,
|
/* System header to define __stub macros and hopefully few prototypes,
|
||||||
which can conflict with char $ac_func(); below. */
|
which can conflict with char $ac_func(); below. */
|
||||||
|
@ -2456,7 +2461,7 @@ $ac_func();
|
||||||
|
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:2460: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
if { (eval echo configure:2465: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
eval "ac_cv_func_$ac_func=yes"
|
eval "ac_cv_func_$ac_func=yes"
|
||||||
else
|
else
|
||||||
|
|
|
@ -6,7 +6,7 @@ AC_INIT(Makefile.in)
|
||||||
SIM_AC_COMMON
|
SIM_AC_COMMON
|
||||||
|
|
||||||
dnl Options available in this module
|
dnl Options available in this module
|
||||||
SIM_AC_OPTION_INLINE(0)
|
SIM_AC_OPTION_INLINE()
|
||||||
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
|
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
|
||||||
SIM_AC_OPTION_HOSTENDIAN
|
SIM_AC_OPTION_HOSTENDIAN
|
||||||
SIM_AC_OPTION_WARNINGS
|
SIM_AC_OPTION_WARNINGS
|
||||||
|
|
|
@ -43,6 +43,7 @@ code on the hardware.
|
||||||
#include "sky-vu.h"
|
#include "sky-vu.h"
|
||||||
#include "sky-vpe.h"
|
#include "sky-vpe.h"
|
||||||
#include "sky-libvpe.h"
|
#include "sky-libvpe.h"
|
||||||
|
#include "sky-pke.h"
|
||||||
#endif
|
#endif
|
||||||
/* end-sanitize-sky */
|
/* end-sanitize-sky */
|
||||||
|
|
||||||
|
@ -438,6 +439,10 @@ sim_open (kind, cb, abfd, argv)
|
||||||
cpu->register_widths[rn + NUM_R5900_REGS] = 32;
|
cpu->register_widths[rn + NUM_R5900_REGS] = 32;
|
||||||
cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
|
cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Finally the VIF registers */
|
||||||
|
for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
|
||||||
|
cpu->register_widths[rn + NUM_R5900_REGS] = 32;
|
||||||
#endif
|
#endif
|
||||||
/* end-sanitize-sky */
|
/* end-sanitize-sky */
|
||||||
}
|
}
|
||||||
|
@ -661,94 +666,105 @@ sim_store_register (sd,rn,memory,length)
|
||||||
#ifdef TARGET_SKY
|
#ifdef TARGET_SKY
|
||||||
if (rn >= NUM_R5900_REGS)
|
if (rn >= NUM_R5900_REGS)
|
||||||
{
|
{
|
||||||
int size = 4; /* Default register size */
|
|
||||||
|
|
||||||
rn = rn - NUM_R5900_REGS;
|
rn = rn - NUM_R5900_REGS;
|
||||||
|
|
||||||
if (rn < NUM_VU_INTEGER_REGS)
|
if( rn < NUM_VU_REGS )
|
||||||
size = write_vu_int_reg (&(vu0_device.state->regs), rn, memory);
|
|
||||||
else if( rn < NUM_VU_REGS )
|
|
||||||
{
|
{
|
||||||
if (rn >= FIRST_VEC_REG)
|
if (rn < NUM_VU_INTEGER_REGS)
|
||||||
|
return write_vu_int_reg (&(vu0_device.state->regs), rn, memory);
|
||||||
|
else if (rn >= FIRST_VEC_REG)
|
||||||
{
|
{
|
||||||
rn -= FIRST_VEC_REG;
|
rn -= FIRST_VEC_REG;
|
||||||
size = write_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn&3,
|
return write_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn&3,
|
||||||
memory);
|
memory);
|
||||||
}
|
}
|
||||||
else switch (rn - NUM_VU_INTEGER_REGS)
|
else switch (rn - NUM_VU_INTEGER_REGS)
|
||||||
{
|
{
|
||||||
case 0:
|
case 0:
|
||||||
size = write_vu_special_reg (vu0_device.state, VU_REG_CIA,
|
return write_vu_special_reg (vu0_device.state, VU_REG_CIA,
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
case 1:
|
case 1:
|
||||||
size = write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
|
return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
case 2: /* VU0 has no P register */
|
case 2: /* VU0 has no P register */
|
||||||
break;
|
return 4;
|
||||||
case 3:
|
case 3:
|
||||||
size = write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
|
return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
case 4:
|
case 4:
|
||||||
size = write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
|
return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
default:
|
default:
|
||||||
size = write_vu_acc_reg (&(vu0_device.state->regs),
|
return write_vu_acc_reg (&(vu0_device.state->regs),
|
||||||
rn - (NUM_VU_INTEGER_REGS + 5),
|
rn - (NUM_VU_INTEGER_REGS + 5),
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else {
|
|
||||||
rn = rn - NUM_VU_REGS;
|
|
||||||
|
|
||||||
if( rn < NUM_VU_INTEGER_REGS )
|
rn = rn - NUM_VU_REGS;
|
||||||
size = write_vu_int_reg (&(vu1_device.state->regs), rn, memory);
|
|
||||||
else if( rn < NUM_VU_REGS )
|
if (rn < NUM_VU_REGS)
|
||||||
{
|
{
|
||||||
if (rn >= FIRST_VEC_REG)
|
if (rn < NUM_VU_INTEGER_REGS)
|
||||||
{
|
return write_vu_int_reg (&(vu1_device.state->regs), rn, memory);
|
||||||
rn -= FIRST_VEC_REG;
|
else if (rn >= FIRST_VEC_REG)
|
||||||
size = write_vu_vec_reg (&(vu1_device.state->regs),
|
{
|
||||||
rn >> 2, rn & 3, memory);
|
rn -= FIRST_VEC_REG;
|
||||||
}
|
return write_vu_vec_reg (&(vu1_device.state->regs),
|
||||||
else switch (rn - NUM_VU_INTEGER_REGS)
|
rn >> 2, rn & 3, memory);
|
||||||
{
|
}
|
||||||
case 0:
|
else switch (rn - NUM_VU_INTEGER_REGS)
|
||||||
size = write_vu_special_reg (vu1_device.state, VU_REG_CIA,
|
{
|
||||||
memory);
|
case 0:
|
||||||
break;
|
return write_vu_special_reg (vu1_device.state, VU_REG_CIA,
|
||||||
case 1:
|
memory);
|
||||||
size = write_vu_misc_reg (&(vu1_device.state->regs),
|
case 1:
|
||||||
VU_REG_MR, memory);
|
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MR,
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
size = write_vu_misc_reg (&(vu1_device.state->regs),
|
|
||||||
VU_REG_MP, memory);
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
size = write_vu_misc_reg (&(vu1_device.state->regs),
|
|
||||||
VU_REG_MI, memory);
|
|
||||||
break;
|
|
||||||
case 4:
|
|
||||||
size = write_vu_misc_reg (&(vu1_device.state->regs),
|
|
||||||
VU_REG_MQ, memory);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
size = write_vu_acc_reg (&(vu1_device.state->regs),
|
|
||||||
rn - (NUM_VU_INTEGER_REGS + 5),
|
|
||||||
memory);
|
memory);
|
||||||
break;
|
case 2:
|
||||||
}
|
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MP,
|
||||||
}
|
memory);
|
||||||
else
|
case 3:
|
||||||
sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
|
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MI,
|
||||||
}
|
memory);
|
||||||
|
case 4:
|
||||||
|
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MQ,
|
||||||
|
memory);
|
||||||
|
default:
|
||||||
|
return write_vu_acc_reg (&(vu1_device.state->regs),
|
||||||
|
rn - (NUM_VU_INTEGER_REGS + 5),
|
||||||
|
memory);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
return size;
|
rn -= NUM_VU_REGS; /* VIF0 registers are next */
|
||||||
|
|
||||||
|
if (rn < NUM_VIF_REGS)
|
||||||
|
{
|
||||||
|
if (rn < NUM_VIF_REGS-1)
|
||||||
|
return write_pke_reg (&pke0_device, rn, memory);
|
||||||
|
else
|
||||||
|
{
|
||||||
|
sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
rn -= NUM_VIF_REGS; /* VIF1 registers are last */
|
||||||
|
|
||||||
|
if (rn < NUM_VIF_REGS)
|
||||||
|
{
|
||||||
|
if (rn < NUM_VIF_REGS-1)
|
||||||
|
return write_pke_reg (&pke1_device, rn, memory);
|
||||||
|
else
|
||||||
|
{
|
||||||
|
sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
/* end-sanitize-sky */
|
/* end-sanitize-sky */
|
||||||
|
@ -777,6 +793,8 @@ sim_store_register (sd,rn,memory,length)
|
||||||
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
|
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
|
||||||
return 8;
|
return 8;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int
|
int
|
||||||
|
@ -823,96 +841,97 @@ sim_fetch_register (sd,rn,memory,length)
|
||||||
#ifdef TARGET_SKY
|
#ifdef TARGET_SKY
|
||||||
if (rn >= NUM_R5900_REGS)
|
if (rn >= NUM_R5900_REGS)
|
||||||
{
|
{
|
||||||
int size = 4; /* default register width */
|
|
||||||
|
|
||||||
rn = rn - NUM_R5900_REGS;
|
rn = rn - NUM_R5900_REGS;
|
||||||
|
|
||||||
if (rn < NUM_VU_INTEGER_REGS)
|
if (rn < NUM_VU_REGS)
|
||||||
size = read_vu_int_reg (&(vu0_device.state->regs), rn, memory);
|
|
||||||
else if (rn < NUM_VU_REGS)
|
|
||||||
{
|
{
|
||||||
if (rn >= FIRST_VEC_REG)
|
if (rn < NUM_VU_INTEGER_REGS)
|
||||||
|
return read_vu_int_reg (&(vu0_device.state->regs), rn, memory);
|
||||||
|
else if (rn >= FIRST_VEC_REG)
|
||||||
{
|
{
|
||||||
rn -= FIRST_VEC_REG;
|
rn -= FIRST_VEC_REG;
|
||||||
size = read_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn & 3,
|
return read_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn & 3,
|
||||||
memory);
|
memory);
|
||||||
}
|
}
|
||||||
else switch (rn - NUM_VU_INTEGER_REGS)
|
else switch (rn - NUM_VU_INTEGER_REGS)
|
||||||
{
|
{
|
||||||
case 0:
|
case 0:
|
||||||
size = read_vu_special_reg (vu0_device.state, VU_REG_CIA,
|
return read_vu_special_reg(vu0_device.state, VU_REG_CIA, memory);
|
||||||
memory);
|
|
||||||
|
|
||||||
break;
|
|
||||||
case 1:
|
case 1:
|
||||||
size = read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
|
return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
case 2: /* VU0 has no P register */
|
case 2: /* VU0 has no P register */
|
||||||
break;
|
*((int *) memory) = 0;
|
||||||
|
return 4;
|
||||||
case 3:
|
case 3:
|
||||||
size = read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
|
return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
case 4:
|
case 4:
|
||||||
size = read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
|
return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
default:
|
default:
|
||||||
size = read_vu_acc_reg (&(vu0_device.state->regs),
|
return read_vu_acc_reg (&(vu0_device.state->regs),
|
||||||
rn - (NUM_VU_INTEGER_REGS + 5),
|
rn - (NUM_VU_INTEGER_REGS + 5),
|
||||||
memory);
|
memory);
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else
|
|
||||||
{
|
|
||||||
rn = rn - NUM_VU_REGS;
|
|
||||||
|
|
||||||
if (rn < NUM_VU_INTEGER_REGS)
|
|
||||||
size = read_vu_int_reg (&(vu1_device.state->regs), rn, memory);
|
|
||||||
else if (rn < NUM_VU_REGS)
|
|
||||||
{
|
|
||||||
if (rn >= FIRST_VEC_REG)
|
|
||||||
{
|
|
||||||
rn -= FIRST_VEC_REG;
|
|
||||||
size = read_vu_vec_reg (&(vu1_device.state->regs),
|
|
||||||
rn >> 2, rn & 3, memory);
|
|
||||||
}
|
|
||||||
else switch (rn - NUM_VU_INTEGER_REGS)
|
|
||||||
{
|
|
||||||
case 0:
|
|
||||||
size = read_vu_special_reg (vu1_device.state, VU_REG_CIA,
|
|
||||||
memory);
|
|
||||||
break;
|
|
||||||
case 1:
|
|
||||||
size = read_vu_misc_reg (&(vu1_device.state->regs),
|
|
||||||
VU_REG_MR, memory);
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
size = read_vu_misc_reg (&(vu1_device.state->regs),
|
|
||||||
VU_REG_MP, memory);
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
size = read_vu_misc_reg (&(vu1_device.state->regs),
|
|
||||||
VU_REG_MI, memory);
|
|
||||||
break;
|
|
||||||
case 4:
|
|
||||||
size = read_vu_misc_reg (&(vu1_device.state->regs),
|
|
||||||
VU_REG_MQ, memory);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
size = read_vu_acc_reg (&(vu1_device.state->regs),
|
|
||||||
rn - (NUM_VU_INTEGER_REGS + 5),
|
|
||||||
memory);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
|
|
||||||
}
|
|
||||||
|
|
||||||
return size;
|
rn -= NUM_VU_REGS; /* VU1 registers are next */
|
||||||
|
|
||||||
|
if (rn < NUM_VU_REGS)
|
||||||
|
{
|
||||||
|
if (rn < NUM_VU_INTEGER_REGS)
|
||||||
|
return read_vu_int_reg (&(vu1_device.state->regs), rn, memory);
|
||||||
|
else if (rn >= FIRST_VEC_REG)
|
||||||
|
{
|
||||||
|
rn -= FIRST_VEC_REG;
|
||||||
|
return read_vu_vec_reg (&(vu1_device.state->regs),
|
||||||
|
rn >> 2, rn & 3, memory);
|
||||||
|
}
|
||||||
|
else switch (rn - NUM_VU_INTEGER_REGS)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
return read_vu_special_reg(vu1_device.state, VU_REG_CIA, memory);
|
||||||
|
case 1:
|
||||||
|
return read_vu_misc_reg (&(vu1_device.state->regs),
|
||||||
|
VU_REG_MR, memory);
|
||||||
|
case 2:
|
||||||
|
return read_vu_misc_reg (&(vu1_device.state->regs),
|
||||||
|
VU_REG_MP, memory);
|
||||||
|
case 3:
|
||||||
|
return read_vu_misc_reg (&(vu1_device.state->regs),
|
||||||
|
VU_REG_MI, memory);
|
||||||
|
case 4:
|
||||||
|
return read_vu_misc_reg (&(vu1_device.state->regs),
|
||||||
|
VU_REG_MQ, memory);
|
||||||
|
default:
|
||||||
|
return read_vu_acc_reg (&(vu1_device.state->regs),
|
||||||
|
rn - (NUM_VU_INTEGER_REGS + 5),
|
||||||
|
memory);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
rn -= NUM_VU_REGS; /* VIF0 registers are next */
|
||||||
|
|
||||||
|
if (rn < NUM_VIF_REGS)
|
||||||
|
{
|
||||||
|
if (rn < NUM_VIF_REGS-1)
|
||||||
|
return read_pke_reg (&pke0_device, rn, memory);
|
||||||
|
else
|
||||||
|
return read_pke_pc (&pke0_device, memory);
|
||||||
|
}
|
||||||
|
|
||||||
|
rn -= NUM_VIF_REGS; /* VIF1 registers are last */
|
||||||
|
|
||||||
|
if (rn < NUM_VIF_REGS)
|
||||||
|
{
|
||||||
|
if (rn < NUM_VIF_REGS-1)
|
||||||
|
return read_pke_reg (&pke1_device, rn, memory);
|
||||||
|
else
|
||||||
|
return read_pke_pc (&pke1_device, memory);
|
||||||
|
}
|
||||||
|
|
||||||
|
sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
/* end-sanitize-sky */
|
/* end-sanitize-sky */
|
||||||
|
@ -942,6 +961,8 @@ sim_fetch_register (sd,rn,memory,length)
|
||||||
*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
|
*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
|
||||||
return 8;
|
return 8;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -1529,350 +1550,6 @@ ColdReset (SIM_DESC sd)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
|
|
||||||
(revision 3.1) */
|
|
||||||
/* Translate a virtual address to a physical address and cache
|
|
||||||
coherence algorithm describing the mechanism used to resolve the
|
|
||||||
memory reference. Given the virtual address vAddr, and whether the
|
|
||||||
reference is to Instructions ot Data (IorD), find the corresponding
|
|
||||||
physical address (pAddr) and the cache coherence algorithm (CCA)
|
|
||||||
used to resolve the reference. If the virtual address is in one of
|
|
||||||
the unmapped address spaces the physical address and the CCA are
|
|
||||||
determined directly by the virtual address. If the virtual address
|
|
||||||
is in one of the mapped address spaces then the TLB is used to
|
|
||||||
determine the physical address and access type; if the required
|
|
||||||
translation is not present in the TLB or the desired access is not
|
|
||||||
permitted the function fails and an exception is taken.
|
|
||||||
|
|
||||||
NOTE: Normally (RAW == 0), when address translation fails, this
|
|
||||||
function raises an exception and does not return. */
|
|
||||||
|
|
||||||
int
|
|
||||||
address_translation (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia,
|
|
||||||
address_word vAddr,
|
|
||||||
int IorD,
|
|
||||||
int LorS,
|
|
||||||
address_word *pAddr,
|
|
||||||
int *CCA,
|
|
||||||
int raw)
|
|
||||||
{
|
|
||||||
int res = -1; /* TRUE : Assume good return */
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Check that the address is valid for this memory model */
|
|
||||||
|
|
||||||
/* For a simple (flat) memory model, we simply pass virtual
|
|
||||||
addressess through (mostly) unchanged. */
|
|
||||||
vAddr &= 0xFFFFFFFF;
|
|
||||||
|
|
||||||
*pAddr = vAddr; /* default for isTARGET */
|
|
||||||
*CCA = Uncached; /* not used for isHOST */
|
|
||||||
|
|
||||||
return(res);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Description from page A-23 of the "MIPS IV Instruction Set" manual
|
|
||||||
(revision 3.1) */
|
|
||||||
/* Prefetch data from memory. Prefetch is an advisory instruction for
|
|
||||||
which an implementation specific action is taken. The action taken
|
|
||||||
may increase performance, but must not change the meaning of the
|
|
||||||
program, or alter architecturally-visible state. */
|
|
||||||
|
|
||||||
void
|
|
||||||
prefetch (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia,
|
|
||||||
int CCA,
|
|
||||||
address_word pAddr,
|
|
||||||
address_word vAddr,
|
|
||||||
int DATA,
|
|
||||||
int hint)
|
|
||||||
{
|
|
||||||
#ifdef DEBUG
|
|
||||||
sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
/* For our simple memory model we do nothing */
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
|
|
||||||
(revision 3.1) */
|
|
||||||
/* Load a value from memory. Use the cache and main memory as
|
|
||||||
specified in the Cache Coherence Algorithm (CCA) and the sort of
|
|
||||||
access (IorD) to find the contents of AccessLength memory bytes
|
|
||||||
starting at physical location pAddr. The data is returned in the
|
|
||||||
fixed width naturally-aligned memory element (MemElem). The
|
|
||||||
low-order two (or three) bits of the address and the AccessLength
|
|
||||||
indicate which of the bytes within MemElem needs to be given to the
|
|
||||||
processor. If the memory access type of the reference is uncached
|
|
||||||
then only the referenced bytes are read from memory and valid
|
|
||||||
within the memory element. If the access type is cached, and the
|
|
||||||
data is not present in cache, an implementation specific size and
|
|
||||||
alignment block of memory is read and loaded into the cache to
|
|
||||||
satisfy a load reference. At a minimum, the block is the entire
|
|
||||||
memory element. */
|
|
||||||
void
|
|
||||||
load_memory (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia,
|
|
||||||
uword64* memvalp,
|
|
||||||
uword64* memval1p,
|
|
||||||
int CCA,
|
|
||||||
unsigned int AccessLength,
|
|
||||||
address_word pAddr,
|
|
||||||
address_word vAddr,
|
|
||||||
int IorD)
|
|
||||||
{
|
|
||||||
uword64 value = 0;
|
|
||||||
uword64 value1 = 0;
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
#if defined(WARN_MEM)
|
|
||||||
if (CCA != uncached)
|
|
||||||
sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
|
|
||||||
#endif /* WARN_MEM */
|
|
||||||
|
|
||||||
/* If instruction fetch then we need to check that the two lo-order
|
|
||||||
bits are zero, otherwise raise a InstructionFetch exception: */
|
|
||||||
if ((IorD == isINSTRUCTION)
|
|
||||||
&& ((pAddr & 0x3) != 0)
|
|
||||||
&& (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
|
|
||||||
SignalExceptionInstructionFetch ();
|
|
||||||
|
|
||||||
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
|
|
||||||
{
|
|
||||||
/* In reality this should be a Bus Error */
|
|
||||||
sim_io_error (sd, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
|
|
||||||
AccessLength,
|
|
||||||
(LOADDRMASK + 1) << 3,
|
|
||||||
pr_addr (pAddr));
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(TRACE)
|
|
||||||
dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
|
|
||||||
#endif /* TRACE */
|
|
||||||
|
|
||||||
/* Read the specified number of bytes from memory. Adjust for
|
|
||||||
host/target byte ordering/ Align the least significant byte
|
|
||||||
read. */
|
|
||||||
|
|
||||||
switch (AccessLength)
|
|
||||||
{
|
|
||||||
case AccessLength_QUADWORD :
|
|
||||||
{
|
|
||||||
unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, read_map, pAddr);
|
|
||||||
value1 = VH8_16 (val);
|
|
||||||
value = VL8_16 (val);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case AccessLength_DOUBLEWORD :
|
|
||||||
value = sim_core_read_aligned_8 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
case AccessLength_SEPTIBYTE :
|
|
||||||
value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
case AccessLength_SEXTIBYTE :
|
|
||||||
value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
case AccessLength_QUINTIBYTE :
|
|
||||||
value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
case AccessLength_WORD :
|
|
||||||
value = sim_core_read_aligned_4 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
case AccessLength_TRIPLEBYTE :
|
|
||||||
value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
case AccessLength_HALFWORD :
|
|
||||||
value = sim_core_read_aligned_2 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
case AccessLength_BYTE :
|
|
||||||
value = sim_core_read_aligned_1 (cpu, NULL_CIA,
|
|
||||||
read_map, pAddr);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
abort ();
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
|
|
||||||
(int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
/* See also store_memory. Position data in correct byte lanes. */
|
|
||||||
if (AccessLength <= LOADDRMASK)
|
|
||||||
{
|
|
||||||
if (BigEndianMem)
|
|
||||||
/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
|
|
||||||
shifted to the most significant byte position. */
|
|
||||||
value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
|
|
||||||
else
|
|
||||||
/* For little endian target, byte (pAddr&LOADDRMASK == 0)
|
|
||||||
is already in the correct postition. */
|
|
||||||
value <<= ((pAddr & LOADDRMASK) * 8);
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
|
|
||||||
pr_uword64(value1),pr_uword64(value));
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
*memvalp = value;
|
|
||||||
if (memval1p) *memval1p = value1;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/* Description from page A-23 of the "MIPS IV Instruction Set" manual
|
|
||||||
(revision 3.1) */
|
|
||||||
/* Store a value to memory. The specified data is stored into the
|
|
||||||
physical location pAddr using the memory hierarchy (data caches and
|
|
||||||
main memory) as specified by the Cache Coherence Algorithm
|
|
||||||
(CCA). The MemElem contains the data for an aligned, fixed-width
|
|
||||||
memory element (word for 32-bit processors, doubleword for 64-bit
|
|
||||||
processors), though only the bytes that will actually be stored to
|
|
||||||
memory need to be valid. The low-order two (or three) bits of pAddr
|
|
||||||
and the AccessLength field indicates which of the bytes within the
|
|
||||||
MemElem data should actually be stored; only these bytes in memory
|
|
||||||
will be changed. */
|
|
||||||
|
|
||||||
void
|
|
||||||
store_memory (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia,
|
|
||||||
int CCA,
|
|
||||||
unsigned int AccessLength,
|
|
||||||
uword64 MemElem,
|
|
||||||
uword64 MemElem1, /* High order 64 bits */
|
|
||||||
address_word pAddr,
|
|
||||||
address_word vAddr)
|
|
||||||
{
|
|
||||||
#ifdef DEBUG
|
|
||||||
sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
#if defined(WARN_MEM)
|
|
||||||
if (CCA != uncached)
|
|
||||||
sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
|
|
||||||
#endif /* WARN_MEM */
|
|
||||||
|
|
||||||
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
|
|
||||||
sim_io_error (sd, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
|
|
||||||
AccessLength,
|
|
||||||
(LOADDRMASK + 1) << 3,
|
|
||||||
pr_addr(pAddr));
|
|
||||||
|
|
||||||
#if defined(TRACE)
|
|
||||||
dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
|
|
||||||
#endif /* TRACE */
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
/* See also load_memory. Position data in correct byte lanes. */
|
|
||||||
if (AccessLength <= LOADDRMASK)
|
|
||||||
{
|
|
||||||
if (BigEndianMem)
|
|
||||||
/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
|
|
||||||
shifted to the most significant byte position. */
|
|
||||||
MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
|
|
||||||
else
|
|
||||||
/* For little endian target, byte (pAddr&LOADDRMASK == 0)
|
|
||||||
is already in the correct postition. */
|
|
||||||
MemElem >>= ((pAddr & LOADDRMASK) * 8);
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
switch (AccessLength)
|
|
||||||
{
|
|
||||||
case AccessLength_QUADWORD :
|
|
||||||
{
|
|
||||||
unsigned_16 val = U16_8 (MemElem1, MemElem);
|
|
||||||
sim_core_write_aligned_16 (cpu, NULL_CIA, write_map, pAddr, val);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case AccessLength_DOUBLEWORD :
|
|
||||||
sim_core_write_aligned_8 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
case AccessLength_SEPTIBYTE :
|
|
||||||
sim_core_write_misaligned_7 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
case AccessLength_SEXTIBYTE :
|
|
||||||
sim_core_write_misaligned_6 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
case AccessLength_QUINTIBYTE :
|
|
||||||
sim_core_write_misaligned_5 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
case AccessLength_WORD :
|
|
||||||
sim_core_write_aligned_4 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
case AccessLength_TRIPLEBYTE :
|
|
||||||
sim_core_write_misaligned_3 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
case AccessLength_HALFWORD :
|
|
||||||
sim_core_write_aligned_2 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
case AccessLength_BYTE :
|
|
||||||
sim_core_write_aligned_1 (cpu, NULL_CIA,
|
|
||||||
write_map, pAddr, MemElem);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
abort ();
|
|
||||||
}
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
unsigned32
|
|
||||||
ifetch32 (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia,
|
|
||||||
address_word vaddr)
|
|
||||||
{
|
|
||||||
/* Copy the action of the LW instruction */
|
|
||||||
address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
|
|
||||||
address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
|
|
||||||
unsigned64 value;
|
|
||||||
address_word paddr;
|
|
||||||
unsigned32 instruction;
|
|
||||||
unsigned byte;
|
|
||||||
int cca;
|
|
||||||
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
|
|
||||||
paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
|
|
||||||
LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
|
|
||||||
byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
|
|
||||||
instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
|
|
||||||
return instruction;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
unsigned16
|
unsigned16
|
||||||
ifetch16 (SIM_DESC sd,
|
ifetch16 (SIM_DESC sd,
|
||||||
sim_cpu *cpu,
|
sim_cpu *cpu,
|
||||||
|
@ -1896,23 +1573,6 @@ ifetch16 (SIM_DESC sd,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
|
|
||||||
/* Order loads and stores to synchronise shared memory. Perform the
|
|
||||||
action necessary to make the effects of groups of synchronizable
|
|
||||||
loads and stores indicated by stype occur in the same order for all
|
|
||||||
processors. */
|
|
||||||
void
|
|
||||||
sync_operation (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia,
|
|
||||||
int stype)
|
|
||||||
{
|
|
||||||
#ifdef DEBUG
|
|
||||||
sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
|
|
||||||
#endif /* DEBUG */
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
|
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
|
||||||
/* Signal an exception condition. This will result in an exception
|
/* Signal an exception condition. This will result in an exception
|
||||||
that aborts the instruction. The instruction operation pseudocode
|
that aborts the instruction. The instruction operation pseudocode
|
||||||
|
@ -2167,82 +1827,6 @@ undefined_result(sd,cia)
|
||||||
}
|
}
|
||||||
#endif /* WARN_RESULT */
|
#endif /* WARN_RESULT */
|
||||||
|
|
||||||
void
|
|
||||||
cache_op (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia,
|
|
||||||
int op,
|
|
||||||
address_word pAddr,
|
|
||||||
address_word vAddr,
|
|
||||||
unsigned int instruction)
|
|
||||||
{
|
|
||||||
#if 1 /* stop warning message being displayed (we should really just remove the code) */
|
|
||||||
static int icache_warning = 1;
|
|
||||||
static int dcache_warning = 1;
|
|
||||||
#else
|
|
||||||
static int icache_warning = 0;
|
|
||||||
static int dcache_warning = 0;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* If CP0 is not useable (User or Supervisor mode) and the CP0
|
|
||||||
enable bit in the Status Register is clear - a coprocessor
|
|
||||||
unusable exception is taken. */
|
|
||||||
#if 0
|
|
||||||
sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
|
|
||||||
#endif
|
|
||||||
|
|
||||||
switch (op & 0x3) {
|
|
||||||
case 0: /* instruction cache */
|
|
||||||
switch (op >> 2) {
|
|
||||||
case 0: /* Index Invalidate */
|
|
||||||
case 1: /* Index Load Tag */
|
|
||||||
case 2: /* Index Store Tag */
|
|
||||||
case 4: /* Hit Invalidate */
|
|
||||||
case 5: /* Fill */
|
|
||||||
case 6: /* Hit Writeback */
|
|
||||||
if (!icache_warning)
|
|
||||||
{
|
|
||||||
sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
|
|
||||||
icache_warning = 1;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
SignalException(ReservedInstruction,instruction);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 1: /* data cache */
|
|
||||||
switch (op >> 2) {
|
|
||||||
case 0: /* Index Writeback Invalidate */
|
|
||||||
case 1: /* Index Load Tag */
|
|
||||||
case 2: /* Index Store Tag */
|
|
||||||
case 3: /* Create Dirty */
|
|
||||||
case 4: /* Hit Invalidate */
|
|
||||||
case 5: /* Hit Writeback Invalidate */
|
|
||||||
case 6: /* Hit Writeback */
|
|
||||||
if (!dcache_warning)
|
|
||||||
{
|
|
||||||
sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
|
|
||||||
dcache_warning = 1;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
SignalException(ReservedInstruction,instruction);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
default: /* unrecognised cache ID */
|
|
||||||
SignalException(ReservedInstruction,instruction);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-- FPU support routines ---------------------------------------------------*/
|
/*-- FPU support routines ---------------------------------------------------*/
|
||||||
|
|
||||||
/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
|
/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
|
||||||
|
@ -4093,72 +3677,6 @@ pr_uword64(addr)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void
|
|
||||||
pending_tick (SIM_DESC sd,
|
|
||||||
sim_cpu *cpu,
|
|
||||||
address_word cia)
|
|
||||||
{
|
|
||||||
if (PENDING_TRACE)
|
|
||||||
sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
|
|
||||||
if (PENDING_OUT != PENDING_IN)
|
|
||||||
{
|
|
||||||
int loop;
|
|
||||||
int index = PENDING_OUT;
|
|
||||||
int total = PENDING_TOTAL;
|
|
||||||
if (PENDING_TOTAL == 0)
|
|
||||||
sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
|
|
||||||
for (loop = 0; (loop < total); loop++)
|
|
||||||
{
|
|
||||||
if (PENDING_SLOT_DEST[index] != NULL)
|
|
||||||
{
|
|
||||||
PENDING_SLOT_DELAY[index] -= 1;
|
|
||||||
if (PENDING_SLOT_DELAY[index] == 0)
|
|
||||||
{
|
|
||||||
if (PENDING_SLOT_BIT[index] >= 0)
|
|
||||||
switch (PENDING_SLOT_SIZE[index])
|
|
||||||
{
|
|
||||||
case 32:
|
|
||||||
if (PENDING_SLOT_VALUE[index])
|
|
||||||
*(unsigned32*)PENDING_SLOT_DEST[index] |=
|
|
||||||
BIT32 (PENDING_SLOT_BIT[index]);
|
|
||||||
else
|
|
||||||
*(unsigned32*)PENDING_SLOT_DEST[index] &=
|
|
||||||
BIT32 (PENDING_SLOT_BIT[index]);
|
|
||||||
break;
|
|
||||||
case 64:
|
|
||||||
if (PENDING_SLOT_VALUE[index])
|
|
||||||
*(unsigned64*)PENDING_SLOT_DEST[index] |=
|
|
||||||
BIT64 (PENDING_SLOT_BIT[index]);
|
|
||||||
else
|
|
||||||
*(unsigned64*)PENDING_SLOT_DEST[index] &=
|
|
||||||
BIT64 (PENDING_SLOT_BIT[index]);
|
|
||||||
break;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
switch (PENDING_SLOT_SIZE[index])
|
|
||||||
{
|
|
||||||
case 32:
|
|
||||||
*(unsigned32*)PENDING_SLOT_DEST[index] =
|
|
||||||
PENDING_SLOT_VALUE[index];
|
|
||||||
break;
|
|
||||||
case 64:
|
|
||||||
*(unsigned64*)PENDING_SLOT_DEST[index] =
|
|
||||||
PENDING_SLOT_VALUE[index];
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (PENDING_OUT == index)
|
|
||||||
{
|
|
||||||
PENDING_SLOT_DEST[index] = NULL;
|
|
||||||
PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
|
|
||||||
PENDING_TOTAL--;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
index = (index + 1) % PSLOTS;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
||||||
/*> EOF interp.c <*/
|
/*> EOF interp.c <*/
|
||||||
|
|
|
@ -0,0 +1,542 @@
|
||||||
|
/* Simulator for the MIPS architecture.
|
||||||
|
|
||||||
|
This file is part of the MIPS sim
|
||||||
|
|
||||||
|
THIS SOFTWARE IS NOT COPYRIGHTED
|
||||||
|
|
||||||
|
Cygnus offers the following for use in the public domain. Cygnus
|
||||||
|
makes no warranty with regard to the software or it's performance
|
||||||
|
and the user accepts the software "AS IS" with all faults.
|
||||||
|
|
||||||
|
CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
|
||||||
|
THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||||
|
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
||||||
|
|
||||||
|
$Revision$
|
||||||
|
$Date$
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef SIM_MAIN_C
|
||||||
|
#define SIM_MAIN_C
|
||||||
|
|
||||||
|
#include "sim-main.h"
|
||||||
|
|
||||||
|
#if !(WITH_IGEN)
|
||||||
|
#define SIM_MANIFESTS
|
||||||
|
#include "oengine.c"
|
||||||
|
#undef SIM_MANIFESTS
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------*/
|
||||||
|
/*-- simulator engine -------------------------------------------------------*/
|
||||||
|
/*---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
|
||||||
|
(revision 3.1) */
|
||||||
|
/* Translate a virtual address to a physical address and cache
|
||||||
|
coherence algorithm describing the mechanism used to resolve the
|
||||||
|
memory reference. Given the virtual address vAddr, and whether the
|
||||||
|
reference is to Instructions ot Data (IorD), find the corresponding
|
||||||
|
physical address (pAddr) and the cache coherence algorithm (CCA)
|
||||||
|
used to resolve the reference. If the virtual address is in one of
|
||||||
|
the unmapped address spaces the physical address and the CCA are
|
||||||
|
determined directly by the virtual address. If the virtual address
|
||||||
|
is in one of the mapped address spaces then the TLB is used to
|
||||||
|
determine the physical address and access type; if the required
|
||||||
|
translation is not present in the TLB or the desired access is not
|
||||||
|
permitted the function fails and an exception is taken.
|
||||||
|
|
||||||
|
NOTE: Normally (RAW == 0), when address translation fails, this
|
||||||
|
function raises an exception and does not return. */
|
||||||
|
|
||||||
|
INLINE_SIM_MAIN (int)
|
||||||
|
address_translation (SIM_DESC sd,
|
||||||
|
sim_cpu *cpu,
|
||||||
|
address_word cia,
|
||||||
|
address_word vAddr,
|
||||||
|
int IorD,
|
||||||
|
int LorS,
|
||||||
|
address_word *pAddr,
|
||||||
|
int *CCA,
|
||||||
|
int raw)
|
||||||
|
{
|
||||||
|
int res = -1; /* TRUE : Assume good return */
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check that the address is valid for this memory model */
|
||||||
|
|
||||||
|
/* For a simple (flat) memory model, we simply pass virtual
|
||||||
|
addressess through (mostly) unchanged. */
|
||||||
|
vAddr &= 0xFFFFFFFF;
|
||||||
|
|
||||||
|
*pAddr = vAddr; /* default for isTARGET */
|
||||||
|
*CCA = Uncached; /* not used for isHOST */
|
||||||
|
|
||||||
|
return(res);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Description from page A-23 of the "MIPS IV Instruction Set" manual
|
||||||
|
(revision 3.1) */
|
||||||
|
/* Prefetch data from memory. Prefetch is an advisory instruction for
|
||||||
|
which an implementation specific action is taken. The action taken
|
||||||
|
may increase performance, but must not change the meaning of the
|
||||||
|
program, or alter architecturally-visible state. */
|
||||||
|
|
||||||
|
INLINE_SIM_MAIN (void)
|
||||||
|
prefetch (SIM_DESC sd,
|
||||||
|
sim_cpu *cpu,
|
||||||
|
address_word cia,
|
||||||
|
int CCA,
|
||||||
|
address_word pAddr,
|
||||||
|
address_word vAddr,
|
||||||
|
int DATA,
|
||||||
|
int hint)
|
||||||
|
{
|
||||||
|
#ifdef DEBUG
|
||||||
|
sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
|
||||||
|
#endif /* DEBUG */
|
||||||
|
|
||||||
|
/* For our simple memory model we do nothing */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
|
||||||
|
(revision 3.1) */
|
||||||
|
/* Load a value from memory. Use the cache and main memory as
|
||||||
|
specified in the Cache Coherence Algorithm (CCA) and the sort of
|
||||||
|
access (IorD) to find the contents of AccessLength memory bytes
|
||||||
|
starting at physical location pAddr. The data is returned in the
|
||||||
|
fixed width naturally-aligned memory element (MemElem). The
|
||||||
|
low-order two (or three) bits of the address and the AccessLength
|
||||||
|
indicate which of the bytes within MemElem needs to be given to the
|
||||||
|
processor. If the memory access type of the reference is uncached
|
||||||
|
then only the referenced bytes are read from memory and valid
|
||||||
|
within the memory element. If the access type is cached, and the
|
||||||
|
data is not present in cache, an implementation specific size and
|
||||||
|
alignment block of memory is read and loaded into the cache to
|
||||||
|
satisfy a load reference. At a minimum, the block is the entire
|
||||||
|
memory element. */
|
||||||
|
INLINE_SIM_MAIN (void)
|
||||||
|
load_memory (SIM_DESC SD,
|
||||||
|
sim_cpu *CPU,
|
||||||
|
address_word cia,
|
||||||
|
uword64* memvalp,
|
||||||
|
uword64* memval1p,
|
||||||
|
int CCA,
|
||||||
|
unsigned int AccessLength,
|
||||||
|
address_word pAddr,
|
||||||
|
address_word vAddr,
|
||||||
|
int IorD)
|
||||||
|
{
|
||||||
|
uword64 value = 0;
|
||||||
|
uword64 value1 = 0;
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
|
||||||
|
#endif /* DEBUG */
|
||||||
|
|
||||||
|
#if defined(WARN_MEM)
|
||||||
|
if (CCA != uncached)
|
||||||
|
sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
|
||||||
|
#endif /* WARN_MEM */
|
||||||
|
|
||||||
|
/* If instruction fetch then we need to check that the two lo-order
|
||||||
|
bits are zero, otherwise raise a InstructionFetch exception: */
|
||||||
|
if ((IorD == isINSTRUCTION)
|
||||||
|
&& ((pAddr & 0x3) != 0)
|
||||||
|
&& (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
|
||||||
|
SignalExceptionInstructionFetch ();
|
||||||
|
|
||||||
|
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
|
||||||
|
{
|
||||||
|
/* In reality this should be a Bus Error */
|
||||||
|
sim_io_error (SD, "LOAD AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
|
||||||
|
AccessLength,
|
||||||
|
(LOADDRMASK + 1) << 3,
|
||||||
|
pr_addr (pAddr));
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(TRACE)
|
||||||
|
dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
|
||||||
|
#endif /* TRACE */
|
||||||
|
|
||||||
|
/* Read the specified number of bytes from memory. Adjust for
|
||||||
|
host/target byte ordering/ Align the least significant byte
|
||||||
|
read. */
|
||||||
|
|
||||||
|
switch (AccessLength)
|
||||||
|
{
|
||||||
|
case AccessLength_QUADWORD :
|
||||||
|
{
|
||||||
|
unsigned_16 val = sim_core_read_aligned_16 (CPU, NULL_CIA, read_map, pAddr);
|
||||||
|
value1 = VH8_16 (val);
|
||||||
|
value = VL8_16 (val);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case AccessLength_DOUBLEWORD :
|
||||||
|
value = sim_core_read_aligned_8 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
case AccessLength_SEPTIBYTE :
|
||||||
|
value = sim_core_read_misaligned_7 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
case AccessLength_SEXTIBYTE :
|
||||||
|
value = sim_core_read_misaligned_6 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
case AccessLength_QUINTIBYTE :
|
||||||
|
value = sim_core_read_misaligned_5 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
case AccessLength_WORD :
|
||||||
|
value = sim_core_read_aligned_4 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
case AccessLength_TRIPLEBYTE :
|
||||||
|
value = sim_core_read_misaligned_3 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
case AccessLength_HALFWORD :
|
||||||
|
value = sim_core_read_aligned_2 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
case AccessLength_BYTE :
|
||||||
|
value = sim_core_read_aligned_1 (CPU, NULL_CIA,
|
||||||
|
read_map, pAddr);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
abort ();
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
|
||||||
|
(int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
|
||||||
|
#endif /* DEBUG */
|
||||||
|
|
||||||
|
/* See also store_memory. Position data in correct byte lanes. */
|
||||||
|
if (AccessLength <= LOADDRMASK)
|
||||||
|
{
|
||||||
|
if (BigEndianMem)
|
||||||
|
/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
|
||||||
|
shifted to the most significant byte position. */
|
||||||
|
value <<= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
|
||||||
|
else
|
||||||
|
/* For little endian target, byte (pAddr&LOADDRMASK == 0)
|
||||||
|
is already in the correct postition. */
|
||||||
|
value <<= ((pAddr & LOADDRMASK) * 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
|
||||||
|
pr_uword64(value1),pr_uword64(value));
|
||||||
|
#endif /* DEBUG */
|
||||||
|
|
||||||
|
*memvalp = value;
|
||||||
|
if (memval1p) *memval1p = value1;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Description from page A-23 of the "MIPS IV Instruction Set" manual
|
||||||
|
(revision 3.1) */
|
||||||
|
/* Store a value to memory. The specified data is stored into the
|
||||||
|
physical location pAddr using the memory hierarchy (data caches and
|
||||||
|
main memory) as specified by the Cache Coherence Algorithm
|
||||||
|
(CCA). The MemElem contains the data for an aligned, fixed-width
|
||||||
|
memory element (word for 32-bit processors, doubleword for 64-bit
|
||||||
|
processors), though only the bytes that will actually be stored to
|
||||||
|
memory need to be valid. The low-order two (or three) bits of pAddr
|
||||||
|
and the AccessLength field indicates which of the bytes within the
|
||||||
|
MemElem data should actually be stored; only these bytes in memory
|
||||||
|
will be changed. */
|
||||||
|
|
||||||
|
INLINE_SIM_MAIN (void)
|
||||||
|
store_memory (SIM_DESC SD,
|
||||||
|
sim_cpu *CPU,
|
||||||
|
address_word cia,
|
||||||
|
int CCA,
|
||||||
|
unsigned int AccessLength,
|
||||||
|
uword64 MemElem,
|
||||||
|
uword64 MemElem1, /* High order 64 bits */
|
||||||
|
address_word pAddr,
|
||||||
|
address_word vAddr)
|
||||||
|
{
|
||||||
|
#ifdef DEBUG
|
||||||
|
sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
|
||||||
|
#endif /* DEBUG */
|
||||||
|
|
||||||
|
#if defined(WARN_MEM)
|
||||||
|
if (CCA != uncached)
|
||||||
|
sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
|
||||||
|
#endif /* WARN_MEM */
|
||||||
|
|
||||||
|
if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
|
||||||
|
sim_io_error (SD, "STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s\n",
|
||||||
|
AccessLength,
|
||||||
|
(LOADDRMASK + 1) << 3,
|
||||||
|
pr_addr(pAddr));
|
||||||
|
|
||||||
|
#if defined(TRACE)
|
||||||
|
dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
|
||||||
|
#endif /* TRACE */
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
|
||||||
|
#endif /* DEBUG */
|
||||||
|
|
||||||
|
/* See also load_memory. Position data in correct byte lanes. */
|
||||||
|
if (AccessLength <= LOADDRMASK)
|
||||||
|
{
|
||||||
|
if (BigEndianMem)
|
||||||
|
/* for big endian target, byte (pAddr&LOADDRMASK == 0) is
|
||||||
|
shifted to the most significant byte position. */
|
||||||
|
MemElem >>= (((LOADDRMASK - (pAddr & LOADDRMASK)) - AccessLength) * 8);
|
||||||
|
else
|
||||||
|
/* For little endian target, byte (pAddr&LOADDRMASK == 0)
|
||||||
|
is already in the correct postition. */
|
||||||
|
MemElem >>= ((pAddr & LOADDRMASK) * 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
|
||||||
|
#endif /* DEBUG */
|
||||||
|
|
||||||
|
switch (AccessLength)
|
||||||
|
{
|
||||||
|
case AccessLength_QUADWORD :
|
||||||
|
{
|
||||||
|
unsigned_16 val = U16_8 (MemElem1, MemElem);
|
||||||
|
sim_core_write_aligned_16 (CPU, NULL_CIA, write_map, pAddr, val);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case AccessLength_DOUBLEWORD :
|
||||||
|
sim_core_write_aligned_8 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
case AccessLength_SEPTIBYTE :
|
||||||
|
sim_core_write_misaligned_7 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
case AccessLength_SEXTIBYTE :
|
||||||
|
sim_core_write_misaligned_6 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
case AccessLength_QUINTIBYTE :
|
||||||
|
sim_core_write_misaligned_5 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
case AccessLength_WORD :
|
||||||
|
sim_core_write_aligned_4 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
case AccessLength_TRIPLEBYTE :
|
||||||
|
sim_core_write_misaligned_3 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
case AccessLength_HALFWORD :
|
||||||
|
sim_core_write_aligned_2 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
case AccessLength_BYTE :
|
||||||
|
sim_core_write_aligned_1 (CPU, NULL_CIA,
|
||||||
|
write_map, pAddr, MemElem);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
abort ();
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
INLINE_SIM_MAIN (unsigned32)
|
||||||
|
ifetch32 (SIM_DESC SD,
|
||||||
|
sim_cpu *CPU,
|
||||||
|
address_word cia,
|
||||||
|
address_word vaddr)
|
||||||
|
{
|
||||||
|
/* Copy the action of the LW instruction */
|
||||||
|
address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
|
||||||
|
address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
|
||||||
|
unsigned64 value;
|
||||||
|
address_word paddr;
|
||||||
|
unsigned32 instruction;
|
||||||
|
unsigned byte;
|
||||||
|
int cca;
|
||||||
|
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
|
||||||
|
paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
|
||||||
|
LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
|
||||||
|
byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
|
||||||
|
instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
|
||||||
|
return instruction;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
|
||||||
|
/* Order loads and stores to synchronise shared memory. Perform the
|
||||||
|
action necessary to make the effects of groups of synchronizable
|
||||||
|
loads and stores indicated by stype occur in the same order for all
|
||||||
|
processors. */
|
||||||
|
INLINE_SIM_MAIN (void)
|
||||||
|
sync_operation (SIM_DESC sd,
|
||||||
|
sim_cpu *cpu,
|
||||||
|
address_word cia,
|
||||||
|
int stype)
|
||||||
|
{
|
||||||
|
#ifdef DEBUG
|
||||||
|
sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
|
||||||
|
#endif /* DEBUG */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
INLINE_SIM_MAIN (void)
|
||||||
|
cache_op (SIM_DESC SD,
|
||||||
|
sim_cpu *CPU,
|
||||||
|
address_word cia,
|
||||||
|
int op,
|
||||||
|
address_word pAddr,
|
||||||
|
address_word vAddr,
|
||||||
|
unsigned int instruction)
|
||||||
|
{
|
||||||
|
#if 1 /* stop warning message being displayed (we should really just remove the code) */
|
||||||
|
static int icache_warning = 1;
|
||||||
|
static int dcache_warning = 1;
|
||||||
|
#else
|
||||||
|
static int icache_warning = 0;
|
||||||
|
static int dcache_warning = 0;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* If CP0 is not useable (User or Supervisor mode) and the CP0
|
||||||
|
enable bit in the Status Register is clear - a coprocessor
|
||||||
|
unusable exception is taken. */
|
||||||
|
#if 0
|
||||||
|
sim_io_printf(SD,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
switch (op & 0x3) {
|
||||||
|
case 0: /* instruction cache */
|
||||||
|
switch (op >> 2) {
|
||||||
|
case 0: /* Index Invalidate */
|
||||||
|
case 1: /* Index Load Tag */
|
||||||
|
case 2: /* Index Store Tag */
|
||||||
|
case 4: /* Hit Invalidate */
|
||||||
|
case 5: /* Fill */
|
||||||
|
case 6: /* Hit Writeback */
|
||||||
|
if (!icache_warning)
|
||||||
|
{
|
||||||
|
sim_io_eprintf(SD,"Instruction CACHE operation %d to be coded\n",(op >> 2));
|
||||||
|
icache_warning = 1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
SignalException(ReservedInstruction,instruction);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1: /* data cache */
|
||||||
|
switch (op >> 2) {
|
||||||
|
case 0: /* Index Writeback Invalidate */
|
||||||
|
case 1: /* Index Load Tag */
|
||||||
|
case 2: /* Index Store Tag */
|
||||||
|
case 3: /* Create Dirty */
|
||||||
|
case 4: /* Hit Invalidate */
|
||||||
|
case 5: /* Hit Writeback Invalidate */
|
||||||
|
case 6: /* Hit Writeback */
|
||||||
|
if (!dcache_warning)
|
||||||
|
{
|
||||||
|
sim_io_eprintf(SD,"Data CACHE operation %d to be coded\n",(op >> 2));
|
||||||
|
dcache_warning = 1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
SignalException(ReservedInstruction,instruction);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default: /* unrecognised cache ID */
|
||||||
|
SignalException(ReservedInstruction,instruction);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
INLINE_SIM_MAIN (void)
|
||||||
|
pending_tick (SIM_DESC SD,
|
||||||
|
sim_cpu *CPU,
|
||||||
|
address_word cia)
|
||||||
|
{
|
||||||
|
if (PENDING_TRACE)
|
||||||
|
sim_io_printf (SD, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
|
||||||
|
if (PENDING_OUT != PENDING_IN)
|
||||||
|
{
|
||||||
|
int loop;
|
||||||
|
int index = PENDING_OUT;
|
||||||
|
int total = PENDING_TOTAL;
|
||||||
|
if (PENDING_TOTAL == 0)
|
||||||
|
sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
|
||||||
|
for (loop = 0; (loop < total); loop++)
|
||||||
|
{
|
||||||
|
if (PENDING_SLOT_DEST[index] != NULL)
|
||||||
|
{
|
||||||
|
PENDING_SLOT_DELAY[index] -= 1;
|
||||||
|
if (PENDING_SLOT_DELAY[index] == 0)
|
||||||
|
{
|
||||||
|
if (PENDING_SLOT_BIT[index] >= 0)
|
||||||
|
switch (PENDING_SLOT_SIZE[index])
|
||||||
|
{
|
||||||
|
case 32:
|
||||||
|
if (PENDING_SLOT_VALUE[index])
|
||||||
|
*(unsigned32*)PENDING_SLOT_DEST[index] |=
|
||||||
|
BIT32 (PENDING_SLOT_BIT[index]);
|
||||||
|
else
|
||||||
|
*(unsigned32*)PENDING_SLOT_DEST[index] &=
|
||||||
|
BIT32 (PENDING_SLOT_BIT[index]);
|
||||||
|
break;
|
||||||
|
case 64:
|
||||||
|
if (PENDING_SLOT_VALUE[index])
|
||||||
|
*(unsigned64*)PENDING_SLOT_DEST[index] |=
|
||||||
|
BIT64 (PENDING_SLOT_BIT[index]);
|
||||||
|
else
|
||||||
|
*(unsigned64*)PENDING_SLOT_DEST[index] &=
|
||||||
|
BIT64 (PENDING_SLOT_BIT[index]);
|
||||||
|
break;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
switch (PENDING_SLOT_SIZE[index])
|
||||||
|
{
|
||||||
|
case 32:
|
||||||
|
*(unsigned32*)PENDING_SLOT_DEST[index] =
|
||||||
|
PENDING_SLOT_VALUE[index];
|
||||||
|
break;
|
||||||
|
case 64:
|
||||||
|
*(unsigned64*)PENDING_SLOT_DEST[index] =
|
||||||
|
PENDING_SLOT_VALUE[index];
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (PENDING_OUT == index)
|
||||||
|
{
|
||||||
|
PENDING_SLOT_DEST[index] = NULL;
|
||||||
|
PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
|
||||||
|
PENDING_TOTAL--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
index = (index + 1) % PSLOTS;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
|
@ -516,11 +516,13 @@ struct _sim_cpu {
|
||||||
#define NUM_VU_REGS 153
|
#define NUM_VU_REGS 153
|
||||||
#define NUM_VU_INTEGER_REGS 16
|
#define NUM_VU_INTEGER_REGS 16
|
||||||
|
|
||||||
|
#define NUM_VIF_REGS 25
|
||||||
|
|
||||||
#define FIRST_VEC_REG 25
|
#define FIRST_VEC_REG 25
|
||||||
#define NUM_R5900_REGS 128
|
#define NUM_R5900_REGS 128
|
||||||
|
|
||||||
#undef NUM_REGS
|
#undef NUM_REGS
|
||||||
#define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS))
|
#define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
|
||||||
#endif /* no tm-txvu.h */
|
#endif /* no tm-txvu.h */
|
||||||
#endif
|
#endif
|
||||||
/* end-sanitize-sky */
|
/* end-sanitize-sky */
|
||||||
|
@ -831,31 +833,31 @@ decode_coproc (SD, CPU, cia, (instruction))
|
||||||
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
|
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
int address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
|
||||||
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
||||||
address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
|
address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
|
||||||
|
|
||||||
void load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
|
||||||
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
||||||
load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
|
load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
|
||||||
|
|
||||||
void store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
|
||||||
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
||||||
store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
|
store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
|
||||||
|
|
||||||
void cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
||||||
#define CacheOp(op,pAddr,vAddr,instruction) \
|
#define CacheOp(op,pAddr,vAddr,instruction) \
|
||||||
cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
||||||
|
|
||||||
void sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
|
INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
|
||||||
#define SyncOperation(stype) \
|
#define SyncOperation(stype) \
|
||||||
sync_operation (SD, CPU, cia, (stype))
|
sync_operation (SD, CPU, cia, (stype))
|
||||||
|
|
||||||
void prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
||||||
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
|
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
|
||||||
prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
|
prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
|
||||||
|
|
||||||
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
||||||
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
|
#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
|
||||||
unsigned16 ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
unsigned16 ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
|
||||||
#define IMEM16(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
|
#define IMEM16(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
|
||||||
|
@ -864,6 +866,14 @@ unsigned16 ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, addres
|
||||||
void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
|
void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
|
||||||
FILE *tracefh;
|
FILE *tracefh;
|
||||||
|
|
||||||
void pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
|
INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
|
||||||
|
|
||||||
|
char* pr_addr PARAMS ((SIM_ADDR addr));
|
||||||
|
char* pr_uword64 PARAMS ((uword64 addr));
|
||||||
|
|
||||||
|
|
||||||
|
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
|
||||||
|
#include "sim-main.c"
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -1512,13 +1512,18 @@ if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
|
||||||
echo "Setting inline flags = $sim_inline" 6>&1
|
echo "Setting inline flags = $sim_inline" 6>&1
|
||||||
fi
|
fi
|
||||||
else
|
else
|
||||||
|
|
||||||
|
if test "x$cross_compiling" = "xno"; then
|
||||||
if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
|
if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
|
||||||
sim_inline="${default_sim_inline}"
|
sim_inline="${default_sim_inline}"
|
||||||
if test x"$silent" != x"yes"; then
|
if test x"$silent" != x"yes"; then
|
||||||
echo "Setting inline flags = $sim_inline" 6>&1
|
echo "Setting inline flags = $sim_inline" 6>&1
|
||||||
|
fi
|
||||||
|
else
|
||||||
|
sim_inline=""
|
||||||
fi
|
fi
|
||||||
else
|
else
|
||||||
sim_inline=""
|
sim_inline="-DDEFAULT_INLINE=0"
|
||||||
fi
|
fi
|
||||||
fi
|
fi
|
||||||
|
|
||||||
|
@ -1632,14 +1637,14 @@ else
|
||||||
|
|
||||||
if test "x$cross_compiling" = "xno"; then
|
if test "x$cross_compiling" = "xno"; then
|
||||||
echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
|
echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
|
||||||
echo "configure:1636: checking whether byte ordering is bigendian" >&5
|
echo "configure:1641: checking whether byte ordering is bigendian" >&5
|
||||||
if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
else
|
else
|
||||||
ac_cv_c_bigendian=unknown
|
ac_cv_c_bigendian=unknown
|
||||||
# See if sys/param.h defines the BYTE_ORDER macro.
|
# See if sys/param.h defines the BYTE_ORDER macro.
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1643 "configure"
|
#line 1648 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
#include <sys/types.h>
|
#include <sys/types.h>
|
||||||
#include <sys/param.h>
|
#include <sys/param.h>
|
||||||
|
@ -1650,11 +1655,11 @@ int main() {
|
||||||
#endif
|
#endif
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:1654: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
if { (eval echo configure:1659: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
# It does; now see whether it defined to BIG_ENDIAN or not.
|
# It does; now see whether it defined to BIG_ENDIAN or not.
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1658 "configure"
|
#line 1663 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
#include <sys/types.h>
|
#include <sys/types.h>
|
||||||
#include <sys/param.h>
|
#include <sys/param.h>
|
||||||
|
@ -1665,7 +1670,7 @@ int main() {
|
||||||
#endif
|
#endif
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:1669: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
if { (eval echo configure:1674: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
ac_cv_c_bigendian=yes
|
ac_cv_c_bigendian=yes
|
||||||
else
|
else
|
||||||
|
@ -1685,7 +1690,7 @@ if test "$cross_compiling" = yes; then
|
||||||
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
|
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
|
||||||
else
|
else
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1689 "configure"
|
#line 1694 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
main () {
|
main () {
|
||||||
/* Are we little or big endian? From Harbison&Steele. */
|
/* Are we little or big endian? From Harbison&Steele. */
|
||||||
|
@ -1698,7 +1703,7 @@ main () {
|
||||||
exit (u.c[sizeof (long) - 1] == 1);
|
exit (u.c[sizeof (long) - 1] == 1);
|
||||||
}
|
}
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:1702: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
|
if { (eval echo configure:1707: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
|
||||||
then
|
then
|
||||||
ac_cv_c_bigendian=no
|
ac_cv_c_bigendian=no
|
||||||
else
|
else
|
||||||
|
@ -1829,17 +1834,17 @@ for ac_hdr in stdlib.h unistd.h string.h strings.h
|
||||||
do
|
do
|
||||||
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
|
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
|
||||||
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
|
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
|
||||||
echo "configure:1833: checking for $ac_hdr" >&5
|
echo "configure:1838: checking for $ac_hdr" >&5
|
||||||
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
else
|
else
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1838 "configure"
|
#line 1843 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
#include <$ac_hdr>
|
#include <$ac_hdr>
|
||||||
EOF
|
EOF
|
||||||
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
|
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
|
||||||
{ (eval echo configure:1843: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
{ (eval echo configure:1848: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
||||||
ac_err=`grep -v '^ *+' conftest.out`
|
ac_err=`grep -v '^ *+' conftest.out`
|
||||||
if test -z "$ac_err"; then
|
if test -z "$ac_err"; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
|
@ -1868,12 +1873,12 @@ done
|
||||||
for ac_func in getpid kill
|
for ac_func in getpid kill
|
||||||
do
|
do
|
||||||
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
|
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
|
||||||
echo "configure:1872: checking for $ac_func" >&5
|
echo "configure:1877: checking for $ac_func" >&5
|
||||||
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
else
|
else
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1877 "configure"
|
#line 1882 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
/* System header to define __stub macros and hopefully few prototypes,
|
/* System header to define __stub macros and hopefully few prototypes,
|
||||||
which can conflict with char $ac_func(); below. */
|
which can conflict with char $ac_func(); below. */
|
||||||
|
@ -1896,7 +1901,7 @@ $ac_func();
|
||||||
|
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:1900: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
if { (eval echo configure:1905: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
eval "ac_cv_func_$ac_func=yes"
|
eval "ac_cv_func_$ac_func=yes"
|
||||||
else
|
else
|
||||||
|
|
|
@ -1514,13 +1514,18 @@ if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
|
||||||
echo "Setting inline flags = $sim_inline" 6>&1
|
echo "Setting inline flags = $sim_inline" 6>&1
|
||||||
fi
|
fi
|
||||||
else
|
else
|
||||||
|
|
||||||
|
if test "x$cross_compiling" = "xno"; then
|
||||||
if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
|
if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
|
||||||
sim_inline="${default_sim_inline}"
|
sim_inline="${default_sim_inline}"
|
||||||
if test x"$silent" != x"yes"; then
|
if test x"$silent" != x"yes"; then
|
||||||
echo "Setting inline flags = $sim_inline" 6>&1
|
echo "Setting inline flags = $sim_inline" 6>&1
|
||||||
|
fi
|
||||||
|
else
|
||||||
|
sim_inline=""
|
||||||
fi
|
fi
|
||||||
else
|
else
|
||||||
sim_inline=""
|
sim_inline="-DDEFAULT_INLINE=0"
|
||||||
fi
|
fi
|
||||||
fi
|
fi
|
||||||
|
|
||||||
|
@ -1588,14 +1593,14 @@ else
|
||||||
|
|
||||||
if test "x$cross_compiling" = "xno"; then
|
if test "x$cross_compiling" = "xno"; then
|
||||||
echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
|
echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
|
||||||
echo "configure:1592: checking whether byte ordering is bigendian" >&5
|
echo "configure:1597: checking whether byte ordering is bigendian" >&5
|
||||||
if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
else
|
else
|
||||||
ac_cv_c_bigendian=unknown
|
ac_cv_c_bigendian=unknown
|
||||||
# See if sys/param.h defines the BYTE_ORDER macro.
|
# See if sys/param.h defines the BYTE_ORDER macro.
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1599 "configure"
|
#line 1604 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
#include <sys/types.h>
|
#include <sys/types.h>
|
||||||
#include <sys/param.h>
|
#include <sys/param.h>
|
||||||
|
@ -1606,11 +1611,11 @@ int main() {
|
||||||
#endif
|
#endif
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:1610: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
if { (eval echo configure:1615: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
# It does; now see whether it defined to BIG_ENDIAN or not.
|
# It does; now see whether it defined to BIG_ENDIAN or not.
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1614 "configure"
|
#line 1619 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
#include <sys/types.h>
|
#include <sys/types.h>
|
||||||
#include <sys/param.h>
|
#include <sys/param.h>
|
||||||
|
@ -1621,7 +1626,7 @@ int main() {
|
||||||
#endif
|
#endif
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:1625: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
if { (eval echo configure:1630: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
ac_cv_c_bigendian=yes
|
ac_cv_c_bigendian=yes
|
||||||
else
|
else
|
||||||
|
@ -1641,7 +1646,7 @@ if test "$cross_compiling" = yes; then
|
||||||
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
|
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
|
||||||
else
|
else
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 1645 "configure"
|
#line 1650 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
main () {
|
main () {
|
||||||
/* Are we little or big endian? From Harbison&Steele. */
|
/* Are we little or big endian? From Harbison&Steele. */
|
||||||
|
@ -1654,7 +1659,7 @@ main () {
|
||||||
exit (u.c[sizeof (long) - 1] == 1);
|
exit (u.c[sizeof (long) - 1] == 1);
|
||||||
}
|
}
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:1658: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
|
if { (eval echo configure:1663: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null
|
||||||
then
|
then
|
||||||
ac_cv_c_bigendian=no
|
ac_cv_c_bigendian=no
|
||||||
else
|
else
|
||||||
|
@ -2010,17 +2015,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h
|
||||||
do
|
do
|
||||||
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
|
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
|
||||||
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
|
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
|
||||||
echo "configure:2014: checking for $ac_hdr" >&5
|
echo "configure:2019: checking for $ac_hdr" >&5
|
||||||
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
else
|
else
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 2019 "configure"
|
#line 2024 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
#include <$ac_hdr>
|
#include <$ac_hdr>
|
||||||
EOF
|
EOF
|
||||||
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
|
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
|
||||||
{ (eval echo configure:2024: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
{ (eval echo configure:2029: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
|
||||||
ac_err=`grep -v '^ *+' conftest.out`
|
ac_err=`grep -v '^ *+' conftest.out`
|
||||||
if test -z "$ac_err"; then
|
if test -z "$ac_err"; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
|
@ -2047,7 +2052,7 @@ fi
|
||||||
done
|
done
|
||||||
|
|
||||||
echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
|
echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
|
||||||
echo "configure:2051: checking for fabs in -lm" >&5
|
echo "configure:2056: checking for fabs in -lm" >&5
|
||||||
ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
|
ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
|
||||||
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
|
@ -2055,7 +2060,7 @@ else
|
||||||
ac_save_LIBS="$LIBS"
|
ac_save_LIBS="$LIBS"
|
||||||
LIBS="-lm $LIBS"
|
LIBS="-lm $LIBS"
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 2059 "configure"
|
#line 2064 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
/* Override any gcc2 internal prototype to avoid an error. */
|
/* Override any gcc2 internal prototype to avoid an error. */
|
||||||
/* We use char because int might match the return type of a gcc2
|
/* We use char because int might match the return type of a gcc2
|
||||||
|
@ -2066,7 +2071,7 @@ int main() {
|
||||||
fabs()
|
fabs()
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:2070: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
if { (eval echo configure:2075: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
eval "ac_cv_lib_$ac_lib_var=yes"
|
eval "ac_cv_lib_$ac_lib_var=yes"
|
||||||
else
|
else
|
||||||
|
@ -2096,12 +2101,12 @@ fi
|
||||||
for ac_func in aint anint sqrt
|
for ac_func in aint anint sqrt
|
||||||
do
|
do
|
||||||
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
|
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
|
||||||
echo "configure:2100: checking for $ac_func" >&5
|
echo "configure:2105: checking for $ac_func" >&5
|
||||||
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
|
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
|
||||||
echo $ac_n "(cached) $ac_c" 1>&6
|
echo $ac_n "(cached) $ac_c" 1>&6
|
||||||
else
|
else
|
||||||
cat > conftest.$ac_ext <<EOF
|
cat > conftest.$ac_ext <<EOF
|
||||||
#line 2105 "configure"
|
#line 2110 "configure"
|
||||||
#include "confdefs.h"
|
#include "confdefs.h"
|
||||||
/* System header to define __stub macros and hopefully few prototypes,
|
/* System header to define __stub macros and hopefully few prototypes,
|
||||||
which can conflict with char $ac_func(); below. */
|
which can conflict with char $ac_func(); below. */
|
||||||
|
@ -2124,7 +2129,7 @@ $ac_func();
|
||||||
|
|
||||||
; return 0; }
|
; return 0; }
|
||||||
EOF
|
EOF
|
||||||
if { (eval echo configure:2128: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
if { (eval echo configure:2133: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
|
||||||
rm -rf conftest*
|
rm -rf conftest*
|
||||||
eval "ac_cv_func_$ac_func=yes"
|
eval "ac_cv_func_$ac_func=yes"
|
||||||
else
|
else
|
||||||
|
|
Loading…
Reference in New Issue