sim: mn10300: convert to sim-cpu

Make cpu allocation fully dynamic so we can leverage the common
sim-cpu and its APIs.

sim/mn10300/ChangeLog

@@ -1,3 +1,15 @@
+2015-04-13  Mike Frysinger  <vapier@gentoo.org>
+
+	* Makefile.in (MN10300_OBJS): Add sim-cpu.o.
+	* interp.c (mn10300_pc_get, mn10300_pc_set): New functions.
+	(sim_open): Declare new local var i.  Call sim_cpu_alloc_all.
+	Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
+	(sim_pc_get): Delete.
+	* sim-main.h (null_cia, NULL_CIA): Delete.
+	(SIM_CPU): Define.
+	(struct sim_state): Change cpu to an array of pointers.
+	(STATE_CPU): Drop & and handle WITH_SMP.
+
 2015-04-06  Mike Frysinger  <vapier@gentoo.org>
 
 	* Makefile.in (SIM_OBJS): Delete sim-engine.o and sim-hrw.o.

sim/mn10300/Makefile.in

@@ -21,6 +21,7 @@ MN10300_OBJS = \
 	itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \
 	$(SIM_NEW_COMMON_OBJS) \
 	op_utils.o \
+	sim-cpu.o \
 	sim-hload.o \
 	sim-resume.o \
 	sim-reason.o \

sim/mn10300/interp.c

@@ -84,6 +84,18 @@ static const OPTION mn10300_options[] =
 /* For compatibility */
 SIM_DESC simulator;
 
+static sim_cia
+mn10300_pc_get (sim_cpu *cpu)
+{
+  return PC;
+}
+
+static void
+mn10300_pc_set (sim_cpu *cpu, sim_cia pc)
+{
+  PC = pc;
+}
+
 /* These default values correspond to expected usage for the chip.  */
 
 SIM_DESC
@@ -92,11 +104,16 @@ sim_open (SIM_OPEN_KIND kind,
 	  struct bfd *abfd,
 	  char **argv)
 {
+  int i;
   SIM_DESC sd = sim_state_alloc (kind, cb);
   mn10300_callback = cb;
 
   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 
+  /* The cpu data is kept in a separately allocated chunk of memory.  */
+  if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
+    return 0;
+
   /* for compatibility */
   simulator = sd;
 
@@ -297,6 +314,15 @@ sim_open (SIM_OPEN_KIND kind,
 /*   STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */
 /* 			     | PSW_CY | PSW_OV | PSW_S | PSW_Z); */
 
+  /* CPU specific initialization.  */
+  for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+    {
+      SIM_CPU *cpu = STATE_CPU (sd, i);
+
+      CPU_PC_FETCH (cpu) = mn10300_pc_get;
+      CPU_PC_STORE (cpu) = mn10300_pc_set;
+    }
+
   return sd;
 }
 
@@ -396,12 +422,6 @@ sim_store_register (SIM_DESC sd,
   return length;
 }
 
-sim_cia
-sim_pc_get (sim_cpu *cpu)
-{
-  return PC;
-}
-
 void
 mn10300_core_signal (SIM_DESC sd,
 		     sim_cpu *cpu,

sim/mn10300/sim-main.h

@@ -43,8 +43,8 @@
 #include "idecode.h"
 
 typedef instruction_address sim_cia;
-static const sim_cia null_cia = {0}; /* Dummy */
+typedef struct _sim_cpu SIM_CPU;
-#define NULL_CIA null_cia
+
 /* FIXME: Perhaps igen should generate access macros for
    `instruction_address' that we could use.  */
 /*#define CIA_ADDR(cia) ((cia).ip) doesn't work for mn10300*/
@@ -85,8 +85,12 @@ struct _sim_cpu {
 struct sim_state {
 
   /* the processors proper */
-  sim_cpu cpu;
+  sim_cpu *cpu[MAX_NR_PROCESSORS];
-#define STATE_CPU(sd, n) (&(sd)->cpu)
+#if (WITH_SMP)
+#define STATE_CPU(sd,n) ((sd)->cpu[n])
+#else
+#define STATE_CPU(sd,n) ((sd)->cpu[0])
+#endif
 
   /* The base class.  */
   sim_state_base base;