gas/
2008-02-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (inoutportreg): New. (process_immext): New. (md_assemble): Use it. (update_imm): Use imm16 and imm32s. (i386_att_operand): Use inoutportreg. opcodes/ 2008-02-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG. * i386-init.h: Regenerated.
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H.J. Lu
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@ -1,3 +1,11 @@
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2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (inoutportreg): New.
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(process_immext): New.
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(md_assemble): Use it.
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(update_imm): Use imm16 and imm32s.
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(i386_att_operand): Use inoutportreg.
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2008-02-14 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (operand_type_all_zero): New.
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@ -1258,6 +1258,8 @@ operand_type_xor (i386_operand_type x, i386_operand_type y)
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static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
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static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
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static const i386_operand_type control = OPERAND_TYPE_CONTROL;
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static const i386_operand_type inoutportreg
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= OPERAND_TYPE_INOUTPORTREG;
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static const i386_operand_type reg16_inoutportreg
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= OPERAND_TYPE_REG16_INOUTPORTREG;
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static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
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@ -2393,13 +2395,57 @@ intel_float_operand (const char *mnemonic)
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return 1;
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}
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static void
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process_immext (void)
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{
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expressionS *exp;
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if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
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{
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/* SSE3 Instructions have the fixed operands with an opcode
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suffix which is coded in the same place as an 8-bit immediate
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field would be. Here we check those operands and remove them
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afterwards. */
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unsigned int x;
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for (x = 0; x < i.operands; x++)
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if (i.op[x].regs->reg_num != x)
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as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
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register_prefix,
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i.op[x].regs->reg_name,
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x + 1,
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i.tm.name); i.operands = 0;
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}
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/* These AMD 3DNow! and SSE2 Instructions have an opcode suffix
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which is coded in the same place as an 8-bit immediate field
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would be. Here we fake an 8-bit immediate operand from the
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opcode suffix stored in tm.extension_opcode.
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SSE5 also uses this encoding, for some of its 3 argument
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instructions. */
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assert (i.imm_operands == 0
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&& (i.operands <= 2
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|| (i.tm.cpu_flags.bitfield.cpusse5
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&& i.operands <= 3)));
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exp = &im_expressions[i.imm_operands++];
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i.op[i.operands].imms = exp;
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i.types[i.operands] = imm8;
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i.operands++;
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exp->X_op = O_constant;
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exp->X_add_number = i.tm.extension_opcode;
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i.tm.extension_opcode = None;
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}
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/* This is the guts of the machine-dependent assembler. LINE points to a
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machine dependent instruction. This function is supposed to emit
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the frags/bytes it assembles to. */
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void
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md_assemble (line)
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char *line;
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md_assemble (char *line)
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{
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unsigned int j;
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char mnemonic[MAX_MNEM_SIZE];
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@ -2509,48 +2555,7 @@ md_assemble (line)
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i.reg_operands--;
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if (i.tm.opcode_modifier.immext)
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{
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expressionS *exp;
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if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
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{
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/* Streaming SIMD extensions 3 Instructions have the fixed
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operands with an opcode suffix which is coded in the same
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place as an 8-bit immediate field would be. Here we check
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those operands and remove them afterwards. */
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unsigned int x;
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for (x = 0; x < i.operands; x++)
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if (i.op[x].regs->reg_num != x)
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as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
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register_prefix,
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i.op[x].regs->reg_name,
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x + 1,
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i.tm.name);
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i.operands = 0;
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}
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/* These AMD 3DNow! and Intel Katmai New Instructions have an
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opcode suffix which is coded in the same place as an 8-bit
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immediate field would be. Here we fake an 8-bit immediate
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operand from the opcode suffix stored in tm.extension_opcode.
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SSE5 also uses this encoding, for some of its 3 argument
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instructions. */
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assert (i.imm_operands == 0
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&& (i.operands <= 2
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|| (i.tm.cpu_flags.bitfield.cpusse5
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&& i.operands <= 3)));
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exp = &im_expressions[i.imm_operands++];
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i.op[i.operands].imms = exp;
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operand_type_set (&i.types[i.operands], 0);
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i.types[i.operands].bitfield.imm8 = 1;
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i.operands++;
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exp->X_op = O_constant;
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exp->X_add_number = i.tm.extension_opcode;
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i.tm.extension_opcode = None;
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}
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process_immext ();
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/* For insns with operands there are more diddles to do to the opcode. */
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if (i.operands)
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@ -4123,11 +4128,10 @@ update_imm (unsigned int j)
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|| operand_type_equal (&overlap, &imm16_32)
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|| operand_type_equal (&overlap, &imm16_32s))
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{
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operand_type_set (&overlap, 0);
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if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
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overlap.bitfield.imm16 = 1;
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overlap = imm16;
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else
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overlap.bitfield.imm32s = 1;
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overlap = imm32s;
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}
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if (!operand_type_equal (&overlap, &imm8)
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&& !operand_type_equal (&overlap, &imm8s)
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@ -6603,8 +6607,7 @@ i386_att_operand (char *operand_string)
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&& i.seg[i.mem_operands] == 0
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&& !operand_type_check (i.types[this_operand], disp))
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{
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operand_type_set (&i.types[this_operand], 0);
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i.types[this_operand].bitfield.inoutportreg = 1;
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i.types[this_operand] = inoutportreg;
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return 1;
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}
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@ -1,3 +1,8 @@
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2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
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* i386-init.h: Regenerated.
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2008-02-14 Nick Clifton <nickc@redhat.com>
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PR binutils/5524
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@ -188,6 +188,8 @@ static initializer operand_type_init [] =
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"Reg32|Acc|Dword" },
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{ "OPERAND_TYPE_ACC64",
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"Reg64|Acc|Qword" },
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{ "OPERAND_TYPE_INOUTPORTREG",
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"InOutPortReg" },
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{ "OPERAND_TYPE_REG16_INOUTPORTREG",
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"Reg16|InOutPortReg" },
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{ "OPERAND_TYPE_DISP16_32",
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@ -341,6 +341,11 @@
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0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
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0, 0, 0 } }
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#define OPERAND_TYPE_INOUTPORTREG \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0 } }
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#define OPERAND_TYPE_REG16_INOUTPORTREG \
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{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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