From 65f2205d609d9c38e1a7f009d2c6833aecfb83eb Mon Sep 17 00:00:00 2001 From: Matthew Wahab Date: Mon, 14 Dec 2015 17:25:35 +0000 Subject: [PATCH] [AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers. ARMv8.2 adds 16-bit floating point operations as an optional extension to the floating point and Adv.SIMD support. The FP16 additions to the scalar pairwise group introduce a new vector type. This patch reworks code in the assembler to allow the addition of the new type. The new vector type requires the addtion of a new operand qualifier to the enum aarch64_opnd_qualifier which is defined include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_. The correctness of the GAS utility function tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and ordering of this group. In particular, it makes assumptions about the positions of the members of the group that are not true if a qualifier for type 2H is added before the qualifier for 4H. This patch reworks the function to weaken its assumptions, making it calculate positions in the group from the type (B, H, S, D, Q) and register width. gas/ 2015-12-14 Matthew Wahab * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand qualifier from per-type base and offet. Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1 --- gas/ChangeLog | 5 +++++ gas/config/tc-aarch64.c | 36 ++++++++++++++++++++++++++++++------ 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 28e89840c4..17fa42e700 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2015-12-14 Matthew Wahab + + * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand + qualifier from per-type base and offet. + 2015-12-14 Jan Beulich * dw2gencfi.c (dot_cfi_label): Free "name". diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2685ae8ea9..0e47189172 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4671,6 +4671,14 @@ vectype_to_qualifier (const struct neon_type_el *vectype) /* Element size in bytes indexed by neon_el_type. */ const unsigned char ele_size[5] = {1, 2, 4, 8, 16}; + const unsigned int ele_base [5] = + { + AARCH64_OPND_QLF_V_8B, + AARCH64_OPND_QLF_V_4H, + AARCH64_OPND_QLF_V_2S, + AARCH64_OPND_QLF_V_1D, + AARCH64_OPND_QLF_V_1Q + }; if (!vectype->defined || vectype->type == NT_invtype) goto vectype_conversion_fail; @@ -4685,14 +4693,30 @@ vectype_to_qualifier (const struct neon_type_el *vectype) /* Vector register. */ int reg_size = ele_size[vectype->type] * vectype->width; unsigned offset; + unsigned shift; if (reg_size != 16 && reg_size != 8) goto vectype_conversion_fail; - /* The conversion is calculated based on the relation of the order of - qualifiers to the vector element size and vector register size. */ - offset = (vectype->type == NT_q) - ? 8 : (vectype->type << 1) + (reg_size >> 4); - gas_assert (offset <= 8); - return AARCH64_OPND_QLF_V_8B + offset; + + /* The conversion is by calculating the offset from the base operand + qualifier for the vector type. The operand qualifiers are regular + enough that the offset can established by shifting the vector width by + a vector-type dependent amount. */ + shift = 0; + if (vectype->type == NT_b) + shift = 4; + else if (vectype->type == NT_h) + shift = 3; + else if (vectype->type == NT_s) + shift = 2; + else if (vectype->type >= NT_d) + shift = 1; + else + gas_assert (0); + + offset = ele_base [vectype->type] + (vectype->width >> shift); + gas_assert (AARCH64_OPND_QLF_V_8B <= offset + && offset <= AARCH64_OPND_QLF_V_1Q); + return offset; } vectype_conversion_fail: