gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVE
As explained in the PR, the addition of MVE makes the parser strip 't' and 'e' as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with lt and le conditions to be initially parsed as vaddl and vsubl. This means the operand parsing for these must allow for the same operands as the scalar vadd and vsub. I had forgotten to do this and this patch remedies that oversight. gas/ChangeLog: 2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 25660 * config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ. (parse_operands): Handle new operand codes. (do_neon_dyadic_long): Make shape check accept the scalar variants. (asm_opcode_insns): Fix operand codes for vaddl and vsubl. * testsuite/gas/arm/mve-vaddsub-it.s: New test. * testsuite/gas/arm/mve-vaddsub-it.d: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.s: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.l: New test. * testsuite/gas/arm/mve-vaddsub-it-bad.d: New test. * testsuite/gas/arm/nomve-vaddsub-it.d: New test.
This commit is contained in:
Andre Vieira
parent
015ec493d8
commit
66d1f7cc12
@ -1,3 +1,17 @@
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2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
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PR 25660
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* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
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(parse_operands): Handle new operand codes.
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(do_neon_dyadic_long): Make shape check accept the scalar variants.
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(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
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* testsuite/gas/arm/mve-vaddsub-it.s: New test.
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* testsuite/gas/arm/mve-vaddsub-it.d: New test.
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* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
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* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
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* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
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* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
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2020-03-11 H.J. Lu <hongjiu.lu@intel.com>
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* NEWS: Mention x86 assembler options for CVE-2020-0551.
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@ -7072,6 +7072,8 @@ enum operand_parse_code
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OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
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OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
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*/
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OP_RNSDMQR, /* Neon single or double precision, MVE vector or ARM register.
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*/
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OP_RNQ, /* Neon quad precision register */
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OP_RNQMQ, /* Neon quad or MVE vector register. */
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OP_RVSD, /* VFP single or double precision register */
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@ -7225,6 +7227,8 @@ enum operand_parse_code
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OP_oRNSDQ, /* Optional single, double or quad precision vector register */
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OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
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register. */
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OP_oRNSDMQ, /* Optional single, double register or MVE vector
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register. */
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OP_oSHll, /* LSL immediate */
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OP_oSHar, /* ASR immediate */
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OP_oSHllar, /* LSL or ASR immediate */
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@ -7421,6 +7425,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
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case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
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case OP_oRND:
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case OP_RNSDMQR:
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po_reg_or_goto (REG_TYPE_VFS, try_rndmqr);
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break;
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try_rndmqr:
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case OP_RNDMQR:
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po_reg_or_goto (REG_TYPE_RN, try_rndmq);
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break;
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@ -7486,6 +7494,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_RVSD_COND:
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po_reg_or_goto (REG_TYPE_VFSD, try_cond);
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break;
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case OP_oRNSDMQ:
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case OP_RNSDMQ:
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po_reg_or_goto (REG_TYPE_NSD, try_mq2);
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break;
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@ -19599,7 +19608,7 @@ neon_mixed_length (struct neon_type_el et, unsigned size)
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static void
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do_neon_dyadic_long (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
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enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL);
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if (rs == NS_QDD)
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{
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if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
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@ -26542,8 +26551,8 @@ static const struct asm_opcode insns[] =
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#define ARM_VARIANT & fpu_neon_ext_v1
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mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
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mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
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mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
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mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
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mnUF(vaddl, _vaddl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
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mnUF(vsubl, _vsubl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
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mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
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mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
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mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
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6
gas/testsuite/gas/arm/mve-vaddsub-it-bad.d
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6
gas/testsuite/gas/arm/mve-vaddsub-it-bad.d
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@ -0,0 +1,6 @@
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#name: Bad MVE vadd/vsub instructions in IT blocks
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vaddsub-it-bad.l
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.*: +file format .*arm.*
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7
gas/testsuite/gas/arm/mve-vaddsub-it-bad.l
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7
gas/testsuite/gas/arm/mve-vaddsub-it-bad.l
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@ -0,0 +1,7 @@
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[^:]*: Assembler messages:
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[^:]*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
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[^:]*:5: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
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[^:]*:7: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
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[^:]*:8: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
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[^:]*:10: Error: selected FPU does not support instruction -- `vaddl.s8 q0,d1,d2'
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[^:]*:11: Error: selected FPU does not support instruction -- `vsubl.s8 q0,d1,d2'
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11
gas/testsuite/gas/arm/mve-vaddsub-it-bad.s
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11
gas/testsuite/gas/arm/mve-vaddsub-it-bad.s
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@ -0,0 +1,11 @@
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.syntax unified
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.text
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itt le
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vaddle.f16 s3, s5, s7
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vsuble.f16 s7, s4, s6
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itt lt
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vaddlt.f16 s0, s5, s7
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vsublt.f16 s7, s4, s6
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vaddl.s8 q0, d1, d2
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vsubl.s8 q0, d1, d2
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23
gas/testsuite/gas/arm/mve-vaddsub-it.d
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23
gas/testsuite/gas/arm/mve-vaddsub-it.d
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@ -0,0 +1,23 @@
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# name: Armv8.1-M Mainline vadd/vsub instructions in it blocks (with MVE)
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# as: -march=armv8.1-m.main+mve.fp+fp.dp
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# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
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.*: +file format .*arm.*
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Disassembly of section .text:
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[^>]*> bfdc itt le
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[^>]*> ee72 1aa3 vaddle.f32 s3, s5, s7
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[^>]*> ee34 7b06 vaddle.f64 d7, d4, d6
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[^>]*> bfbc itt lt
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[^>]*> ee72 1aa3 vaddlt.f32 s3, s5, s7
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[^>]*> ee34 7b06 vaddlt.f64 d7, d4, d6
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[^>]*> bfdc itt le
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[^>]*> ee72 1ae3 vsuble.f32 s3, s5, s7
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[^>]*> ee34 7b46 vsuble.f64 d7, d4, d6
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[^>]*> bfbc itt lt
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[^>]*> ee72 1ae3 vsublt.f32 s3, s5, s7
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[^>]*> ee34 7b46 vsublt.f64 d7, d4, d6
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[^>]*> bfdc itt le
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[^>]*> ee30 0a06 vaddle.f32 s0, s0, s12
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[^>]*> ee30 0b41 vsuble.f64 d0, d0, d1
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#...
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17
gas/testsuite/gas/arm/mve-vaddsub-it.s
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17
gas/testsuite/gas/arm/mve-vaddsub-it.s
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@ -0,0 +1,17 @@
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.syntax unified
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.text
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itt le
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vaddle.f32 s3, s5, s7
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vaddle.f64 d7, d4, d6
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itt lt
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vaddlt.f32 s3, s5, s7
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vaddlt.f64 d7, d4, d6
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itt le
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vsuble.f32 s3, s5, s7
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vsuble.f64 d7, d4, d6
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itt lt
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vsublt.f32 s3, s5, s7
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vsublt.f64 d7, d4, d6
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itt le
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vaddle.f32 s0, s12
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vsuble.f64 d0, d1
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24
gas/testsuite/gas/arm/nomve-vaddsub-it.d
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24
gas/testsuite/gas/arm/nomve-vaddsub-it.d
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@ -0,0 +1,24 @@
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# name: Armv8.1-M Mainline vadd/vsub instructions in it blocks (without MVE)
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# as: -march=armv8.1-m.main+fp.dp
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# source: mve-vaddsub-it.s
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# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
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.*: +file format .*arm.*
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Disassembly of section .text:
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[^>]*> bfdc itt le
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[^>]*> ee72 1aa3 vaddle.f32 s3, s5, s7
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[^>]*> ee34 7b06 vaddle.f64 d7, d4, d6
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[^>]*> bfbc itt lt
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[^>]*> ee72 1aa3 vaddlt.f32 s3, s5, s7
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[^>]*> ee34 7b06 vaddlt.f64 d7, d4, d6
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[^>]*> bfdc itt le
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[^>]*> ee72 1ae3 vsuble.f32 s3, s5, s7
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[^>]*> ee34 7b46 vsuble.f64 d7, d4, d6
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[^>]*> bfbc itt lt
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[^>]*> ee72 1ae3 vsublt.f32 s3, s5, s7
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[^>]*> ee34 7b46 vsublt.f64 d7, d4, d6
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[^>]*> bfdc itt le
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[^>]*> ee30 0a06 vaddle.f32 s0, s0, s12
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[^>]*> ee30 0b41 vsuble.f64 d0, d0, d1
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#...
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