[PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (thumb32_opcodes): Add new instructions. (enum mve_instructions): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
This commit is contained in:
Andre Vieira
parent
d052b9b7cb
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66dcaa5d55
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@ -1,3 +1,14 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (thumb32_opcodes): Add new instructions.
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(enum mve_instructions): Likewise.
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(is_mve_encoding_conflict): Handle new instructions.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_size): Likewise.
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(print_insn_mve): Likewise.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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@ -208,6 +208,21 @@ enum mve_instructions
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MVE_VSHRN,
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MVE_VSLI,
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MVE_VSRI,
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MVE_VADC,
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MVE_VABAV,
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MVE_VABD_FP,
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MVE_VABD_VEC,
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MVE_VABS_FP,
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MVE_VABS_VEC,
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MVE_VADD_FP_T1,
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MVE_VADD_FP_T2,
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MVE_VADD_VEC_T1,
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MVE_VADD_VEC_T2,
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MVE_VSBC,
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MVE_VSUB_FP_T1,
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MVE_VSUB_FP_T2,
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MVE_VSUB_VEC_T1,
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MVE_VSUB_VEC_T2,
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MVE_NONE
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};
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@ -1990,6 +2005,7 @@ static const struct opcode32 neon_opcodes[] =
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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UNPREDICTABLE
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%<bitfield>s print size for vector predicate & non VMOV instructions
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%<bitfield>I print carry flag or not
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%<bitfield>i print immediate for vstr/vldr reg +/- imm
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%<bitfield>h print high half of 64-bit destination reg
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%<bitfield>k print immediate for vector conversion instruction
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@ -2063,6 +2079,56 @@ static const struct mopcode32 mve_opcodes[] =
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0xef100150, 0xffb11f51,
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"vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VABAV. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VABAV,
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0xee800f01, 0xefc10f51,
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"vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
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/* Vector VABD floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VABD_FP,
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0xff200d40, 0xffa11f51,
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"vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VABD. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VABD_VEC,
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0xef000740, 0xef811f51,
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"vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VABS floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VABS_FP,
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0xFFB10740, 0xFFB31FD1,
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"vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VABS. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VABS_VEC,
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0xffb10340, 0xffb31fd1,
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"vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
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/* Vector VADD floating point T1. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VADD_FP_T1,
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0xef000d40, 0xffa11f51,
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"vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VADD floating point T2. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VADD_FP_T2,
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0xee300f40, 0xefb11f70,
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"vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VADD T1. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VADD_VEC_T1,
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0xef000840, 0xff811f51,
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"vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VADD T2. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VADD_VEC_T2,
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0xee010f40, 0xff811f70,
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"vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VADDLV. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VADDLV,
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@ -2075,6 +2141,12 @@ static const struct mopcode32 mve_opcodes[] =
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0xeef10f00, 0xeff31fd1,
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"vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
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/* Vector VADC. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VADC,
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0xee300f00, 0xffb10f51,
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"vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VCADD floating point. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VCADD_FP,
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@ -2785,6 +2857,12 @@ static const struct mopcode32 mve_opcodes[] =
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0xfe800fc1, 0xffa00fd1,
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"vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
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/* Vector VSBC. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSBC,
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0xfe300f00, 0xffb10f51,
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"vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VSHL T2 Variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSHL_T2,
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@ -2905,6 +2983,30 @@ static const struct mopcode32 mve_opcodes[] =
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0xec001f00, 0xfe101f80,
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"vstrw%v.32\t%13-15,22Q, %d"},
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/* Vector VSUB floating point T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VSUB_FP_T1,
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0xef200d40, 0xffa11f51,
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"vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VSUB floating point T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE_FP),
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MVE_VSUB_FP_T2,
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0xee301f40, 0xefb11f70,
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"vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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/* Vector VSUB T1 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSUB_VEC_T1,
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0xff000840, 0xff811f51,
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"vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
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/* Vector VSUB T2 variant. */
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_VSUB_VEC_T2,
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0xee011f40, 0xff811f70,
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"vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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{ARM_FEATURE_CORE_LOW (0),
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MVE_NONE,
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0x00000000, 0x00000000, 0}
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@ -4927,6 +5029,9 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_VADD_VEC_T2:
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case MVE_VSUB_VEC_T2:
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case MVE_VABAV:
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case MVE_VQRSHL_T1:
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case MVE_VQSHL_T4:
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case MVE_VRSHL_T1:
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@ -5102,6 +5207,9 @@ is_mve_encoding_conflict (unsigned long given,
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return FALSE;
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default:
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case MVE_VADD_FP_T1:
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case MVE_VADD_FP_T2:
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case MVE_VADD_VEC_T1:
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return FALSE;
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}
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@ -5202,6 +5310,9 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VABD_VEC:
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case MVE_VADD_VEC_T1:
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case MVE_VSUB_VEC_T1:
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case MVE_VQDMULH_T1:
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case MVE_VQRDMULH_T2:
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case MVE_VRHADD:
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@ -5377,6 +5488,7 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VABS_FP:
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case MVE_VCVT_BETWEEN_FP_INT:
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case MVE_VCVT_FROM_FP_TO_INT:
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{
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@ -5529,6 +5641,15 @@ is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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else
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return FALSE;
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case MVE_VABS_VEC:
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if (arm_decode_field (given, 18, 19) == 3)
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{
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*undefined_code = UNDEF_SIZE_3;
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return TRUE;
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}
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else
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return FALSE;
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default:
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return FALSE;
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}
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@ -5588,6 +5709,10 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VADD_FP_T2:
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case MVE_VSUB_FP_T2:
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case MVE_VADD_VEC_T2:
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case MVE_VSUB_VEC_T2:
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case MVE_VQRSHL_T2:
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case MVE_VQSHL_T1:
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case MVE_VRSHL_T2:
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@ -5793,6 +5918,7 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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return FALSE;
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}
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case MVE_VABAV:
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case MVE_VMOV_HFP_TO_GP:
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case MVE_VMOV_GP_TO_VEC_LANE:
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case MVE_VMOV_VEC_LANE_TO_GP:
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@ -6647,6 +6773,12 @@ print_mve_size (struct disassemble_info *info,
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switch (matched_insn)
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{
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case MVE_VABAV:
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case MVE_VABD_VEC:
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case MVE_VABS_FP:
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case MVE_VABS_VEC:
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case MVE_VADD_VEC_T1:
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case MVE_VADD_VEC_T2:
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case MVE_VADDV:
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case MVE_VCADD_VEC:
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case MVE_VCMP_VEC_T1:
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@ -6709,12 +6841,19 @@ print_mve_size (struct disassemble_info *info,
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case MVE_VSTRW_SCATTER_T3:
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case MVE_VSTRB_T1:
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case MVE_VSTRH_T2:
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case MVE_VSUB_VEC_T1:
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case MVE_VSUB_VEC_T2:
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if (size <= 3)
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func (stream, "%s", mve_vec_sizename[size]);
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else
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func (stream, "<undef size>");
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break;
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case MVE_VABD_FP:
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case MVE_VADD_FP_T1:
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case MVE_VADD_FP_T2:
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case MVE_VSUB_FP_T1:
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case MVE_VSUB_FP_T2:
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case MVE_VCMP_FP_T1:
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case MVE_VCMP_FP_T2:
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case MVE_VFMA_FP_SCALAR:
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@ -8519,6 +8658,10 @@ print_insn_mve (struct disassemble_info *info, long given)
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value,
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insn->mve_op);
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break;
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case 'I':
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if (value == 1)
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func (stream, "i");
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break;
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case 'A':
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if (value == 1)
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func (stream, "a");
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