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Power10 string operations

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opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
	vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
gas/
	* testsuite/gas/ppc/stringop.d,
	* testsuite/gas/ppc/stringop.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
This commit is contained in:
Alan Modra 2020-05-11 09:46:45 +09:30
parent 4f3e9537c4
commit 66ef5847c3
6 changed files with 54 additions and 0 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
2020-05-11 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/stringop.d,
* testsuite/gas/ppc/stringop.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/set_bool.d,

1
gas/testsuite/gas/ppc/ppc.exp
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@ -142,3 +142,4 @@ run_dump_test "maskmanip"
run_dump_test "genpcv"
run_dump_test "bitmanip"
run_dump_test "set_bool"
run_dump_test "stringop"

20
gas/testsuite/gas/ppc/stringop.d Normal file
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@ -0,0 +1,20 @@
#as: -mpower10
#objdump: -dr -Mpower10
#name: string operations
.*
Disassembly of section \.text:
0+0 <_start>:
.*: (10 01 08 0d|0d 08 01 10) vstribr v0,v1
.*: (10 41 1c 0d|0d 1c 41 10) vstribr. v2,v3
.*: (10 80 28 0d|0d 28 80 10) vstribl v4,v5
.*: (10 c0 3c 0d|0d 3c c0 10) vstribl. v6,v7
.*: (11 03 48 0d|0d 48 03 11) vstrihr v8,v9
.*: (11 43 5c 0d|0d 5c 43 11) vstrihr. v10,v11
.*: (11 82 68 0d|0d 68 82 11) vstrihl v12,v13
.*: (11 c2 7c 0d|0d 7c c2 11) vstrihl. v14,v15
.*: (12 11 91 8d|8d 91 11 12) vclrlb v16,v17,r18
.*: (12 74 a9 cd|cd a9 74 12) vclrrb v19,v20,r21

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gas/testsuite/gas/ppc/stringop.s Normal file
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@ -0,0 +1,12 @@
.text
_start:
vstribr 0,1
vstribr. 2,3
vstribl 4,5
vstribl. 6,7
vstrihr 8,9
vstrihr. 10,11
vstrihl 12,13
vstrihl. 14,15
vclrlb 16,17,18
vclrrb 19,20,21

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2020-05-11 Alan Modra <amodra@gmail.com>
* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2020-05-11 Peter Bergner <bergner@linux.ibm.com>
* ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New

10
opcodes/ppc-opc.c
View File

@ -4118,6 +4118,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vstribl", VXVA(4,13,0), VXVA_MASK, POWER10, 0, {VD, VB}},
{"vstribr", VXVA(4,13,1), VXVA_MASK, POWER10, 0, {VD, VB}},
{"vstrihl", VXVA(4,13,2), VXVA_MASK, POWER10, 0, {VD, VB}},
{"vstrihr", VXVA(4,13,3), VXVA_MASK, POWER10, 0, {VD, VB}},
{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}},
@ -4293,6 +4297,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vclrlb", VX (4, 397), VX_MASK, POWER10, 0, {VD, VA, RB}},
{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}},
{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
@ -4306,6 +4311,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
{"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}},
{"vclrrb", VX (4, 461), VX_MASK, POWER10, 0, {VD, VA, RB}},
{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vinsd", VX (4, 463), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}},
{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
@ -4654,6 +4660,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
{"vstribl.", VXVA(4,1037,0), VXVA_MASK, POWER10, 0, {VD, VB}},
{"vstribr.", VXVA(4,1037,1), VXVA_MASK, POWER10, 0, {VD, VB}},
{"vstrihl.", VXVA(4,1037,2), VXVA_MASK, POWER10, 0, {VD, VB}},
{"vstrihr.", VXVA(4,1037,3), VXVA_MASK, POWER10, 0, {VD, VB}},
{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},