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Remove i370 support

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include/
	* elf/i370.h: Delete.
	* opcode/i370.h: Delete.
bfd/
	* Makefile.am: Remove i370 support.
	* archures.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* cpu-i370.c: Delete.
	* elf32-i370.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* Makefile.am: Remove i370 support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* i370-dis.c: Delete.
	* i370-opc.c: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
binutils/
	* readelf.c: Remove i370 support.
	* testsuite/binutils-all/objdump.exp: Likewise.
gas/
	* Makefile.am: Remove i370 support.
	* app.c: Likewise.
	* config/obj-elf.c: Likewise.
	* configure.tgt: Likewise.
	* doc/Makefile.am: Likewise.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Likewise.
	* testsuite/gas/elf/warn-2.s: Likewise.
	* testsuite/gas/lns/lns.exp: Likewise.
	* config/tc-i370.c: Delete.
	* config/tc-i370.h: Delete.
	* doc/c-i370.texi: Delete.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
ld/
	* Makefile.am: Remove i370 support.
	* configure.tgt: Likewise.
	* testsuite/ld-elf/compressed1d.d: Likewise.
	* testsuite/ld-elf/group8a.d: Likewise.
	* testsuite/ld-elf/group8b.d: Likewise.
	* testsuite/ld-elf/group9a.d: Likewise.
	* testsuite/ld-elf/group9b.d: Likewise.
	* testsuite/ld-elf/merge.d: Likewise.
	* testsuite/ld-elf/pr12851.d: Likewise.
	* testsuite/ld-elf/pr12975.d: Likewise.
	* testsuite/ld-elf/pr13177.d: Likewise.
	* testsuite/ld-elf/pr13195.d: Likewise.
	* testsuite/ld-elf/pr17615.d: Likewise.
	* testsuite/ld-elf/pr21562a.d: Likewise.
	* testsuite/ld-elf/pr21562b.d: Likewise.
	* testsuite/ld-elf/pr21562c.d: Likewise.
	* testsuite/ld-elf/pr21562d.d: Likewise.
	* testsuite/ld-elf/pr21562i.d: Likewise.
	* testsuite/ld-elf/pr21562j.d: Likewise.
	* testsuite/ld-elf/pr21562k.d: Likewise.
	* testsuite/ld-elf/pr21562l.d: Likewise.
	* testsuite/ld-elf/pr21562m.d: Likewise.
	* testsuite/ld-elf/pr21562n.d: Likewise.
	* testsuite/ld-elf/pr22677.d: Likewise.
	* testsuite/lib/ld-lib.exp: Likewise.
	* emulparams/elf32i370.sh: Delete.
	* scripttempl/elfi370.sc: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
This commit is contained in:
Alan Modra 2018-04-16 15:21:56 +09:30
parent e82aa7944d
commit 6793974daa
74 changed files with 112 additions and 6201 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
bfd/ChangeLog
View File

@ -1,3 +1,17 @@
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove i370 support.
* archures.c: Likewise.
* config.bfd: Likewise.
* configure.ac: Likewise.
* targets.c: Likewise.
* cpu-i370.c: Delete.
* elf32-i370.c: Delete.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove h8500 support.

4
bfd/Makefile.am
View File

@ -108,7 +108,6 @@ ALL_MACHINES = \
cpu-ft32.lo \
cpu-h8300.lo \
cpu-hppa.lo \
cpu-i370.lo \
cpu-i386.lo \
cpu-iamcu.lo \
cpu-l1om.lo \
@ -195,7 +194,6 @@ ALL_MACHINES_CFILES = \
cpu-ft32.c \
cpu-h8300.c \
cpu-hppa.c \
cpu-i370.c \
cpu-i386.c \
cpu-iamcu.c \
cpu-l1om.c \
@ -332,7 +330,6 @@ BFD32_BACKENDS = \
elf32-gen.lo \
elf32-h8300.lo \
elf32-hppa.lo \
elf32-i370.lo \
elf32-i386.lo \
elfxx-x86.lo \
elf32-ip2k.lo \
@ -514,7 +511,6 @@ BFD32_BACKENDS_CFILES = \
elf32-gen.c \
elf32-h8300.c \
elf32-hppa.c \
elf32-i370.c \
elf32-i386.c \
elfxx-x86.c \
elf32-ip2k.c \

6
bfd/Makefile.in
View File

@ -441,7 +441,6 @@ ALL_MACHINES = \
cpu-ft32.lo \
cpu-h8300.lo \
cpu-hppa.lo \
cpu-i370.lo \
cpu-i386.lo \
cpu-iamcu.lo \
cpu-l1om.lo \
@ -528,7 +527,6 @@ ALL_MACHINES_CFILES = \
cpu-ft32.c \
cpu-h8300.c \
cpu-hppa.c \
cpu-i370.c \
cpu-i386.c \
cpu-iamcu.c \
cpu-l1om.c \
@ -666,7 +664,6 @@ BFD32_BACKENDS = \
elf32-gen.lo \
elf32-h8300.lo \
elf32-hppa.lo \
elf32-i370.lo \
elf32-i386.lo \
elfxx-x86.lo \
elf32-ip2k.lo \
@ -848,7 +845,6 @@ BFD32_BACKENDS_CFILES = \
elf32-gen.c \
elf32-h8300.c \
elf32-hppa.c \
elf32-i370.c \
elf32-i386.c \
elfxx-x86.c \
elf32-ip2k.c \
@ -1351,7 +1347,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ft32.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-h8300.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-hppa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i370.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i386.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ia64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-iamcu.Plo@am__quote@
@ -1452,7 +1447,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-gen.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-h8300.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-hppa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i370.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i386.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ia64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ip2k.Plo@am__quote@

3
bfd/archures.c
View File

@ -218,7 +218,6 @@ DESCRIPTION
.#define bfd_mach_i386_iamcu (bfd_mach_i386_i386 | bfd_mach_iamcu)
.#define bfd_mach_i386_iamcu_intel_syntax (bfd_mach_i386_iamcu | bfd_mach_i386_intel_syntax)
. bfd_arch_we32k, {* AT&T WE32xxx. *}
. bfd_arch_i370, {* IBM 360/370 Mainframes. *}
. bfd_arch_romp, {* IBM ROMP PC/RT. *}
. bfd_arch_convex, {* Convex. *}
. bfd_arch_m88k, {* Motorola 88xxx. *}
@ -578,7 +577,6 @@ extern const bfd_arch_info_type bfd_fr30_arch;
extern const bfd_arch_info_type bfd_frv_arch;
extern const bfd_arch_info_type bfd_h8300_arch;
extern const bfd_arch_info_type bfd_hppa_arch;
extern const bfd_arch_info_type bfd_i370_arch;
extern const bfd_arch_info_type bfd_i386_arch;
extern const bfd_arch_info_type bfd_iamcu_arch;
extern const bfd_arch_info_type bfd_ia64_arch;
@ -670,7 +668,6 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
&bfd_frv_arch,
&bfd_h8300_arch,
&bfd_hppa_arch,
&bfd_i370_arch,
&bfd_i386_arch,
&bfd_iamcu_arch,
&bfd_ia64_arch,

1
bfd/bfd-in2.h
View File

@ -2093,7 +2093,6 @@ enum bfd_architecture
#define bfd_mach_i386_iamcu (bfd_mach_i386_i386 | bfd_mach_iamcu)
#define bfd_mach_i386_iamcu_intel_syntax (bfd_mach_i386_iamcu | bfd_mach_i386_intel_syntax)
bfd_arch_we32k, /* AT&T WE32xxx. */
bfd_arch_i370, /* IBM 360/370 Mainframes. */
bfd_arch_romp, /* IBM ROMP PC/RT. */
bfd_arch_convex, /* Convex. */
bfd_arch_m88k, /* Motorola 88xxx. */

8
bfd/config.bfd
View File

@ -107,7 +107,6 @@ case $targ in
vax-*-bsd* | vax-*-ultrix* | \
we32k-*-* | \
w65-*-* | \
i370-* | \
sh5*-*-* | sh64*-*-* | \
null)
if test "x$enable_obsolete" != xyes; then
@ -133,6 +132,7 @@ case $targ in
h8300*-*-coff | \
h8500*-*-coff | \
hppa*-*-rtems* | \
i370-* | \
i860-*-* | \
i960-*-* | \
m68*-*-lynxos* | \
@ -169,7 +169,6 @@ dlx*) targ_archs=bfd_dlx_arch ;;
fido*) targ_archs=bfd_m68k_arch ;;
hppa*) targ_archs=bfd_hppa_arch ;;
i[3-7]86) targ_archs=bfd_i386_arch ;;
i370) targ_archs=bfd_i370_arch ;;
ia16) targ_archs=bfd_i386_arch ;;
lm32) targ_archs=bfd_lm32_arch ;;
m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch bfd_m9s12x_arch bfd_m9s12xg_arch" ;;
@ -604,11 +603,6 @@ case "${targ}" in
targ_selvecs=hppa_elf32_vec
;;
i370-*-*)
targ_defvec=i370_elf32_vec
targ_selvecs="i370_elf32_vec"
;;
i[3-7]86-*-sco3.2v5*coff)
targ_defvec=i386_coff_vec
targ_selvecs=i386_elf32_vec

6
bfd/configure vendored
View File

@ -14400,7 +14400,6 @@ do
hppa_elf64_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
hppa_elf64_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
hppa_som_vec) tb="$tb som.lo" ;;
i370_elf32_vec) tb="$tb elf32-i370.lo elf32.lo $elf" ;;
i386_aout_vec) tb="$tb i386aout.lo aout32.lo" ;;
i386_aout_bsd_vec) tb="$tb i386bsd.lo aout32.lo" ;;
i386_aout_dynix_vec) tb="$tb i386dynix.lo aout32.lo" ;;
@ -14820,11 +14819,6 @@ if test "${target}" = "${host}"; then
COREFILE=netbsd-core.lo
;;
i370-*-*)
COREFILE=trad-core.lo
TRAD_HEADER='"hosts/i370linux.h"'
;;
i[3-7]86-sequent-bsd*)
COREFILE=trad-core.lo
TRAD_HEADER='"hosts/symmetry.h"'

6
bfd/configure.ac
View File

@ -477,7 +477,6 @@ do
hppa_elf64_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
hppa_elf64_linux_vec) tb="$tb elf64-hppa.lo elf64.lo $elf"; target_size=64 ;;
hppa_som_vec) tb="$tb som.lo" ;;
i370_elf32_vec) tb="$tb elf32-i370.lo elf32.lo $elf" ;;
i386_aout_vec) tb="$tb i386aout.lo aout32.lo" ;;
i386_aout_bsd_vec) tb="$tb i386bsd.lo aout32.lo" ;;
i386_aout_dynix_vec) tb="$tb i386dynix.lo aout32.lo" ;;
@ -882,11 +881,6 @@ if test "${target}" = "${host}"; then
COREFILE=netbsd-core.lo
;;
i370-*-*)
COREFILE=trad-core.lo
TRAD_HEADER='"hosts/i370linux.h"'
;;
changequote(,)dnl
i[3-7]86-sequent-bsd*)
changequote([,])dnl

77
bfd/cpu-i370.c
View File

@ -1,77 +0,0 @@
/* BFD i370 CPU definition
Copyright (C) 1994-2018 Free Software Foundation, Inc.
Contributed by Ian Lance Taylor, Cygnus Support.
Hacked by Linas Vepstas <linas@linas.org> in 1998, 1999
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
static const bfd_arch_info_type arch_info_struct[] =
{
/* Hack alert: old old machines are really 16 and 24 bit arch ... */
{
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_i370,
360, /* For the 360. */
"i370",
"i370:360",
3,
FALSE, /* Not the default. */
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
&arch_info_struct[1]
},
{
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_i370,
370, /* For the 370. */
"i370",
"i370:370",
3,
FALSE, /* Not the default. */
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
0
},
};
const bfd_arch_info_type bfd_i370_arch =
{
32, /* 32 bits in a word. */
32, /* 32 bits in an address. */
8, /* 8 bits in a byte. */
bfd_arch_i370,
0, /* For the 360/370 common architecture. */
"i370",
"i370:common",
3,
TRUE, /* The default. */
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
& arch_info_struct[0]
};

1404
bfd/elf32-i370.c
View File

File diff suppressed because it is too large Load Diff

2
bfd/po/SRC-POTFILES.in
View File

@ -74,7 +74,6 @@ cpu-frv.c
cpu-ft32.c
cpu-h8300.c
cpu-hppa.c
cpu-i370.c
cpu-i386.c
cpu-ia64.c
cpu-iamcu.c
@ -179,7 +178,6 @@ elf32-gen.c
elf32-h8300.c
elf32-hppa.c
elf32-hppa.h
elf32-i370.c
elf32-i386.c
elf32-ip2k.c
elf32-iq2000.c

3
bfd/targets.c
View File

@ -655,7 +655,6 @@ extern const bfd_target hppa_elf32_nbsd_vec;
extern const bfd_target hppa_elf64_vec;
extern const bfd_target hppa_elf64_linux_vec;
extern const bfd_target hppa_som_vec;
extern const bfd_target i370_elf32_vec;
extern const bfd_target i386_aout_vec;
extern const bfd_target i386_aout_bsd_vec;
extern const bfd_target i386_aout_dynix_vec;
@ -1067,8 +1066,6 @@ static const bfd_target * const _bfd_target_vector[] =
#endif
&hppa_som_vec,
&i370_elf32_vec,
&i386_aout_vec,
&i386_aout_bsd_vec,
#if 0

5
binutils/ChangeLog
View File

@ -1,3 +1,8 @@
2018-04-16 Alan Modra <amodra@gmail.com>
* readelf.c: Remove i370 support.
* testsuite/binutils-all/objdump.exp: Likewise.
2018-04-16 Alan Modra <amodra@gmail.com>
* testsuite/binutils-all/objcopy.exp: Remove h8500 support.

7
binutils/readelf.c
View File

@ -108,7 +108,6 @@
#include "elf/h8.h"
#include "elf/hppa.h"
#include "elf/i386.h"
#include "elf/i370.h"
#include "elf/ia64.h"
#include "elf/ip2k.h"
#include "elf/lm32.h"
@ -1426,10 +1425,6 @@ dump_relocations (Filedata * filedata,
rtype = elf_x86_64_reloc_type (type);
break;
case EM_S370:
rtype = i370_reloc_type (type);
break;
case EM_S390_OLD:
case EM_S390:
rtype = elf_s390_reloc_type (type);
@ -12298,8 +12293,6 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
return reloc_type == 1; /* R_RL78_DIR32. */
case EM_RX:
return reloc_type == 1; /* R_RX_DIR32. */
case EM_S370:
return reloc_type == 1; /* R_I370_ADDR31. */
case EM_S390_OLD:
case EM_S390:
return reloc_type == 4; /* R_S390_32. */

1
binutils/testsuite/binutils-all/objdump.exp
View File

@ -278,7 +278,6 @@ if { ![is_elf_format] } then {
if { ![is_elf_format]
|| [istarget "hppa64*-*-hpux*"]
|| [istarget "i370-*-*"]
|| [istarget "ia64*-*-*"]
|| [istarget "mcore-*-*"]
|| [istarget "moxie-*-*"]

18
gas/ChangeLog
View File

@ -1,3 +1,21 @@
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove i370 support.
* app.c: Likewise.
* config/obj-elf.c: Likewise.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Likewise.
* testsuite/gas/elf/warn-2.s: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* config/tc-i370.c: Delete.
* config/tc-i370.h: Delete.
* doc/c-i370.texi: Delete.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
2018-04-16 Alan Modra <amodra@gmail.com>
* config/obj-coff.h: Remove h8500 support.

2
gas/Makefile.am
View File

@ -148,7 +148,6 @@ TARGET_CPU_CFILES = \
config/tc-h8300.c \
config/tc-hppa.c \
config/tc-ia64.c \
config/tc-i370.c \
config/tc-i386.c \
config/tc-ip2k.c \
config/tc-iq2000.c \
@ -223,7 +222,6 @@ TARGET_CPU_HFILES = \
config/tc-h8300.h \
config/tc-hppa.h \
config/tc-ia64.h \
config/tc-i370.h \
config/tc-i386.h \
config/tc-ip2k.h \
config/tc-iq2000.h \

17
gas/Makefile.in
View File

@ -444,7 +444,6 @@ TARGET_CPU_CFILES = \
config/tc-h8300.c \
config/tc-hppa.c \
config/tc-ia64.c \
config/tc-i370.c \
config/tc-i386.c \
config/tc-ip2k.c \
config/tc-iq2000.c \
@ -519,7 +518,6 @@ TARGET_CPU_HFILES = \
config/tc-h8300.h \
config/tc-hppa.h \
config/tc-ia64.h \
config/tc-i370.h \
config/tc-i386.h \
config/tc-ip2k.h \
config/tc-iq2000.h \
@ -875,7 +873,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ft32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-h8300.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-hppa.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-i370.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-i386.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ia64.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ip2k.Po@am__quote@
@ -1220,20 +1217,6 @@ tc-ia64.obj: config/tc-ia64.c
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ia64.obj `if test -f 'config/tc-ia64.c'; then $(CYGPATH_W) 'config/tc-ia64.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ia64.c'; fi`
tc-i370.o: config/tc-i370.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-i370.o -MD -MP -MF $(DEPDIR)/tc-i370.Tpo -c -o tc-i370.o `test -f 'config/tc-i370.c' || echo '$(srcdir)/'`config/tc-i370.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-i370.Tpo $(DEPDIR)/tc-i370.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-i370.c' object='tc-i370.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-i370.o `test -f 'config/tc-i370.c' || echo '$(srcdir)/'`config/tc-i370.c
tc-i370.obj: config/tc-i370.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-i370.obj -MD -MP -MF $(DEPDIR)/tc-i370.Tpo -c -o tc-i370.obj `if test -f 'config/tc-i370.c'; then $(CYGPATH_W) 'config/tc-i370.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-i370.c'; fi`
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-i370.Tpo $(DEPDIR)/tc-i370.Po
@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-i370.c' object='tc-i370.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-i370.obj `if test -f 'config/tc-i370.c'; then $(CYGPATH_W) 'config/tc-i370.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-i370.c'; fi`
tc-i386.o: config/tc-i386.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-i386.o -MD -MP -MF $(DEPDIR)/tc-i386.Tpo -c -o tc-i386.o `test -f 'config/tc-i386.c' || echo '$(srcdir)/'`config/tc-i386.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-i386.Tpo $(DEPDIR)/tc-i386.Po

3
gas/app.c
View File

@ -120,8 +120,7 @@ do_scrub_begin (int m68k_mri ATTRIBUTE_UNUSED)
{
lex['"'] = LEX_IS_STRINGQUOTE;
#if ! defined (TC_HPPA) && ! defined (TC_I370)
/* I370 uses single-quotes to delimit integer, float constants. */
#if ! defined (TC_HPPA)
lex['\''] = LEX_IS_ONECHAR_QUOTE;
#endif

6
gas/config/obj-elf.c
View File

@ -48,10 +48,6 @@
#include "elf/ppc.h"
#endif
#ifdef TC_I370
#include "elf/i370.h"
#endif
#ifdef TC_I386
#include "elf/x86-64.h"
#endif
@ -1019,7 +1015,6 @@ obj_elf_section (int push)
subsegT new_subsection = -1;
unsigned int info = 0;
#ifndef TC_I370
if (flag_mri)
{
char mri_type;
@ -1039,7 +1034,6 @@ obj_elf_section (int push)
return;
}
#endif /* ! defined (TC_I370) */
name = obj_elf_section_name ();
if (name == NULL)

2669
gas/config/tc-i370.c
View File

File diff suppressed because it is too large Load Diff

63
gas/config/tc-i370.h
View File

@ -1,63 +0,0 @@
/* tc-i370.h -- Header file for tc-i370.c.
Copyright (C) 1994-2018 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#define TC_I370
struct fix;
/* Set the endianness we are using. Default to big endian. */
#ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 1
#endif
/* The target BFD architecture. */
#define TARGET_ARCH (i370_arch ())
extern enum bfd_architecture i370_arch (void);
/* Whether or not the target is big endian. */
extern int target_big_endian;
/* The target BFD format. */
#define TARGET_FORMAT ("elf32-i370")
/* Permit temporary numeric labels. */
#define LOCAL_LABELS_FB 1
/* $ is used to refer to the current location. */
/* #define DOLLAR_DOT */
/* foo-. gets turned into PC relative relocs. */
#define DIFF_EXPR_OK
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
/* We don't need to handle .word strangely. */
#define WORKING_DOT_WORD
/* Call md_pcrel_from_section, not md_pcrel_from. */
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
extern long md_pcrel_from_section (struct fix *, segT);
#define md_operand(x)
#define tc_comment_chars i370_comment_chars
extern const char *i370_comment_chars;

2
gas/configure.tgt
View File

@ -217,8 +217,6 @@ case ${generic_target} in
h8300-*-elf) fmt=elf ;;
h8300-*-linux*) fmt=elf em=linux ;;
i370-*-elf* | i370-*-linux*) fmt=elf ;;
i386-ibm-aix*) fmt=coff em=i386aix ;;
i386-sequent-bsd*) fmt=aout em=dynix ;;
i386-*-beospe*) fmt=coff em=pe ;;

1
gas/doc/Makefile.am
View File

@ -58,7 +58,6 @@ CPU_DOCS = \
c-epiphany.texi \
c-h8300.texi \
c-hppa.texi \
c-i370.texi \
c-i386.texi \
c-ip2k.texi \
c-lm32.texi \

1
gas/doc/Makefile.in
View File

@ -333,7 +333,6 @@ CPU_DOCS = \
c-epiphany.texi \
c-h8300.texi \
c-hppa.texi \
c-i370.texi \
c-i386.texi \
c-ip2k.texi \
c-lm32.texi \

7
gas/doc/as.texinfo
View File

@ -7532,9 +7532,6 @@ subject, see the hardware manufacturer's manual.
@ifset HPPA
* HPPA-Dependent:: HPPA Dependent Features
@end ifset
@ifset I370
* ESA/390-Dependent:: IBM ESA/390 Dependent Features
@end ifset
@ifset I80386
* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features
@end ifset
@ -7739,10 +7736,6 @@ family.
@include c-hppa.texi
@end ifset
@ifset I370
@include c-i370.texi
@end ifset
@ifset I80386
@include c-i386.texi
@end ifset

200
gas/doc/c-i370.texi
View File

@ -1,200 +0,0 @@
@c Copyright (C) 2000-2018 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node ESA/390-Dependent
@chapter ESA/390 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter ESA/390 Dependent Features
@end ifclear
@cindex i370 support
@cindex ESA/390 support
@menu
* ESA/390 Notes:: Notes
* ESA/390 Options:: Options
* ESA/390 Syntax:: Syntax
* ESA/390 Floating Point:: Floating Point
* ESA/390 Directives:: ESA/390 Machine Directives
* ESA/390 Opcodes:: Opcodes
@end menu
@node ESA/390 Notes
@section Notes
The ESA/390 @code{@value{AS}} port is currently intended to be a back-end
for the @sc{gnu} @sc{cc} compiler. It is not HLASM compatible, although
it does support a subset of some of the HLASM directives. The only
supported binary file format is ELF; none of the usual MVS/VM/OE/USS
object file formats, such as ESD or XSD, are supported.
When used with the @sc{gnu} @sc{cc} compiler, the ESA/390 @code{@value{AS}}
will produce correct, fully relocated, functional binaries, and has been
used to compile and execute large projects. However, many aspects should
still be considered experimental; these include shared library support,
dynamically loadable objects, and any relocation other than the 31-bit
relocation.
@node ESA/390 Options
@section Options
@code{@value{AS}} has no machine-dependent command-line options for the ESA/390.
@cindex ESA/390 Syntax
@node ESA/390 Syntax
@section Syntax
The opcode/operand syntax follows the ESA/390 Principles of Operation
manual; assembler directives and general syntax are loosely based on the
prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
are @emph{not} supported for the most part, with the exception of those
described herein.
A leading dot in front of directives is optional, and the case of
directives is ignored; thus for example, .using and USING have the same
effect.
A colon may immediately follow a label definition. This is
simply for compatibility with how most assembly language programmers
write code.
@samp{#} is the line comment character.
@samp{;} can be used instead of a newline to separate statements.
Since @samp{$} has no special meaning, you may use it in symbol names.
Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6.
By using these symbolic names, @code{@value{AS}} can detect simple
syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca
for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
for r3 and rpgt or r.pgt for r4.
@samp{*} is the current location counter. Unlike @samp{.} it is always
relative to the last USING directive. Note that this means that
expressions cannot use multiplication, as any occurrence of @samp{*}
will be interpreted as a location counter.
All labels are relative to the last USING. Thus, branches to a label
always imply the use of base+displacement.
Many of the usual forms of address constants / address literals
are supported. Thus,
@example
.using *,r3
L r15,=A(some_routine)
LM r6,r7,=V(some_longlong_extern)
A r1,=F'12'
AH r0,=H'42'
ME r6,=E'3.1416'
MD r6,=D'3.14159265358979'
O r6,=XL4'cacad0d0'
.ltorg
@end example
should all behave as expected: that is, an entry in the literal
pool will be created (or reused if it already exists), and the
instruction operands will be the displacement into the literal pool
using the current base register (as last declared with the @code{.using}
directive).
@node ESA/390 Floating Point
@section Floating Point
@cindex floating point, ESA/390 (@sc{ieee})
@cindex ESA/390 floating point (@sc{ieee})
The assembler generates only @sc{ieee} floating-point numbers. The older
floating point formats are not supported.
@node ESA/390 Directives
@section ESA/390 Assembler Directives
@code{@value{AS}} for the ESA/390 supports all of the standard ELF/SVR4
assembler directives that are documented in the main part of this
documentation. Several additional directives are supported in order
to implement the ESA/390 addressing model. The most important of these
are @code{.using} and @code{.ltorg}
@cindex ESA/390-only directives
These are the additional directives in @code{@value{AS}} for the ESA/390:
@table @code
@item .dc
A small subset of the usual DC directive is supported.
@item .drop @var{regno}
Stop using @var{regno} as the base register. The @var{regno} must
have been previously declared with a @code{.using} directive in the
same section as the current section.
@item .ebcdic @var{string}
Emit the EBCDIC equivalent of the indicated string. The emitted string
will be null terminated. Note that the directives @code{.string} etc. emit
ascii strings by default.
@item EQU
The standard HLASM-style EQU directive is not supported; however, the
standard @code{@value{AS}} directive .equ can be used to the same effect.
@item .ltorg
Dump the literal pool accumulated so far; begin a new literal pool.
The literal pool will be written in the current section; in order to
generate correct assembly, a @code{.using} must have been previously
specified in the same section.
@item .using @var{expr},@var{regno}
Use @var{regno} as the base register for all subsequent RX, RS, and SS form
instructions. The @var{expr} will be evaluated to obtain the base address;
usually, @var{expr} will merely be @samp{*}.
This assembler allows two @code{.using} directives to be simultaneously
outstanding, one in the @code{.text} section, and one in another section
(typically, the @code{.data} section). This feature allows
dynamically loaded objects to be implemented in a relatively
straightforward way. A @code{.using} directive must always be specified
in the @code{.text} section; this will specify the base register that
will be used for branches in the @code{.text} section. A second
@code{.using} may be specified in another section; this will specify
the base register that is used for non-label address literals.
When a second @code{.using} is specified, then the subsequent
@code{.ltorg} must be put in the same section; otherwise an error will
result.
Thus, for example, the following code uses @code{r3} to address branch
targets and @code{r4} to address the literal pool, which has been written
to the @code{.data} section. The is, the constants @code{=A(some_routine)},
@code{=H'42'} and @code{=E'3.1416'} will all appear in the @code{.data}
section.
@example
.data
.using LITPOOL,r4
.text
BASR r3,0
.using *,r3
B START
.long LITPOOL
START:
L r4,4(,r3)
L r15,=A(some_routine)
LTR r15,r15
BNE LABEL
AH r0,=H'42'
LABEL:
ME r6,=E'3.1416'
.data
LITPOOL:
.ltorg
@end example
Note that this dual-@code{.using} directive semantics extends
and is not compatible with HLASM semantics. Note that this assembler
directive does not support the full range of HLASM semantics.
@end table
@node ESA/390 Opcodes
@section Opcodes
For detailed information on the ESA/390 machine instruction set, see
@cite{ESA/390 Principles of Operation} (IBM Publication Number DZ9AR004).

2
gas/po/POTFILES.in
View File

@ -72,8 +72,6 @@ config/tc-h8300.c
config/tc-h8300.h
config/tc-hppa.c
config/tc-hppa.h
config/tc-i370.c
config/tc-i370.h
config/tc-i386.c
config/tc-i386.h
config/tc-ia64.c

3
gas/testsuite/gas/all/gas.exp
View File

@ -465,9 +465,6 @@ case $target_triplet in {
{ "mmix-*-*" } {
set nop_type 5
}
{ "i370-*-*" } {
set nop_type 3
}
{ "or1k*-*-*" } {
set nop_type 2
}

7
gas/testsuite/gas/elf/warn-2.s
View File

@ -2,7 +2,6 @@
;# { dg-options "--gdwarf2 --defsym nop_type=0" }
;# { dg-options "--gdwarf2 --defsym nop_type=1" { target ia64-*-* } }
;# { dg-options "--gdwarf2 --defsym nop_type=2" { target or1k*-*-* } }
;# { dg-options "--gdwarf2 --defsym nop_type=3" { target i370-*-* } }
.offset 40
@ -11,13 +10,9 @@
.else
.ifeq nop_type - 2
l.nop 0
.else
.ifeq nop_type - 3
nopr 1
.else
nop
.endif
.endif
.endif
;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* v850*-*-* } 0 }
;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail v850*-*-* } 0 }

5
gas/testsuite/gas/lns/lns.exp
View File

@ -24,10 +24,7 @@ run_dump_test "lns-duplicate"
# ??? Won't work on targets that don't have a bare "nop" insn.
# Perhaps we could arrange for an include file or something that
# defined a macro...
if {
![istarget i370-*-*]
&& ![istarget s390*-*-*]
} {
if { ![istarget s390*-*-*] } {
# Use alternate file for targets using DW_LNS_fixed_advance_pc opcodes.
if { [istarget am3*-*-*]
|| [istarget avr*-*-*]

5
include/ChangeLog
View File

@ -1,3 +1,8 @@
2018-04-16 Alan Modra <amodra@gmail.com>
* elf/i370.h: Delete.
* opcode/i370.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* coff/h8500.h: Delete.

61
include/elf/i370.h
View File

@ -1,61 +0,0 @@
/* i370 ELF support for BFD.
Copyright (C) 2000-2018 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* This file holds definitions specific to the i370 ELF ABI. Note
that most of this is not actually implemented by BFD. */
#ifndef _ELF_I370_H
#define _ELF_I370_H
#include "elf/reloc-macros.h"
/* Processor specific section headers, sh_type field */
#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \
entries in this section \
based on the address \
specified in the associated \
symbol table entry. */
#define EF_I370_RELOCATABLE 0x00010000 /* i370 -mrelocatable flag */
#define EF_I370_RELOCATABLE_LIB 0x00008000 /* i370 -mrelocatable-lib flag */
/* i370 relocations
Note that there is really just one relocation that we currently
support (and only one that we seem to need, at the moment), and
that is the 31-bit address relocation. Note that the 370/390
only supports a 31-bit (2GB) address space. */
START_RELOC_NUMBERS (i370_reloc_type)
RELOC_NUMBER (R_I370_NONE, 0)
RELOC_NUMBER (R_I370_ADDR31, 1)
RELOC_NUMBER (R_I370_ADDR32, 2)
RELOC_NUMBER (R_I370_ADDR16, 3)
RELOC_NUMBER (R_I370_REL31, 4)
RELOC_NUMBER (R_I370_REL32, 5)
RELOC_NUMBER (R_I370_ADDR12, 6)
RELOC_NUMBER (R_I370_REL12, 7)
RELOC_NUMBER (R_I370_ADDR8, 8)
RELOC_NUMBER (R_I370_REL8, 9)
RELOC_NUMBER (R_I370_COPY, 10)
RELOC_NUMBER (R_I370_RELATIVE, 11)
END_RELOC_NUMBERS (R_I370_max)
#endif /* _ELF_I370_H */

266
include/opcode/i370.h
View File

@ -1,266 +0,0 @@
/* i370.h -- Header file for S/390 opcode table
Copyright (C) 1994-2018 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef I370_H
#define I370_H
/* The opcode table is an array of struct i370_opcode. */
typedef union
{
unsigned int i[2];
unsigned short s[4];
unsigned char b[8];
} i370_insn_t;
struct i370_opcode
{
/* The opcode name. */
const char *name;
/* the length of the instruction */
char len;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
i370_insn_t opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
i370_insn_t mask;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
are listed below. */
unsigned long flags;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct i370_opcode i370_opcodes[];
extern const int i370_num_opcodes;
/* Values defined for the flags field of a struct i370_opcode. */
/* Opcode is defined for the original 360 architecture. */
#define I370_OPCODE_360 (0x01)
/* Opcode is defined for the 370 architecture. */
#define I370_OPCODE_370 (0x02)
/* Opcode is defined for the 370-XA architecture. */
#define I370_OPCODE_370_XA (0x04)
/* Opcode is defined for the ESA/370 architecture. */
#define I370_OPCODE_ESA370 (0x08)
/* Opcode is defined for the ESA/390 architecture. */
#define I370_OPCODE_ESA390 (0x10)
/* Opcode is defined for the ESA/390 w/ BFP facility. */
#define I370_OPCODE_ESA390_BF (0x20)
/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */
#define I370_OPCODE_ESA390_BS (0x40)
/* Opcode is defined for the ESA/390 w/ checksum facility. */
#define I370_OPCODE_ESA390_CK (0x80)
/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */
#define I370_OPCODE_ESA390_CM (0x100)
/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */
#define I370_OPCODE_ESA390_FX (0x200)
/* Opcode is defined for the ESA/390 w/ HFP facility. */
#define I370_OPCODE_ESA390_HX (0x400)
/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */
#define I370_OPCODE_ESA390_IR (0x800)
/* Opcode is defined for the ESA/390 w/ move-inverse facility. */
#define I370_OPCODE_ESA390_MI (0x1000)
/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */
#define I370_OPCODE_ESA390_PC (0x2000)
/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */
#define I370_OPCODE_ESA390_PL (0x4000)
/* Opcode is defined for the ESA/390 w/ square-root facility. */
#define I370_OPCODE_ESA390_QR (0x8000)
/* Opcode is defined for the ESA/390 w/ resume-program facility. */
#define I370_OPCODE_ESA390_RP (0x10000)
/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */
#define I370_OPCODE_ESA390_SA (0x20000)
/* Opcode is defined for the ESA/390 w/ subspace group facility. */
#define I370_OPCODE_ESA390_SG (0x40000)
/* Opcode is defined for the ESA/390 w/ string facility. */
#define I370_OPCODE_ESA390_SR (0x80000)
/* Opcode is defined for the ESA/390 w/ trap facility. */
#define I370_OPCODE_ESA390_TR (0x100000)
#define I370_OPCODE_ESA390_SUPERSET (0x1fffff)
/* The operands table is an array of struct i370_operand. */
struct i370_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & ((1 << o->bits) - 1)) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
i370_insn_t (*insert)
(i370_insn_t instruction, long op, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & I370_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(i is the instruction, o is a pointer to this structure, and op
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) (i370_insn_t instruction, int *invalid);
/* One bit syntax flags. */
unsigned long flags;
/* name -- handy for debugging, otherwise pointless */
char * name;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the i370_opcodes table. */
extern const struct i370_operand i370_operands[];
/* Values defined for the flags field of a struct i370_operand. */
/* This operand should be wrapped in parentheses rather than
separated from the previous by a comma. This is used for S, RS and
SS form instructions which want their operands to look like
reg,displacement(basereg) */
#define I370_OPERAND_SBASE (0x01)
/* This operand is a base register. It may or may not appear next
to an index register, i.e. either of the two forms
reg,displacement(basereg)
reg,displacement(index,basereg) */
#define I370_OPERAND_BASE (0x02)
/* This pair of operands should be wrapped in parentheses rather than
separated from the last by a comma. This is used for the RX form
instructions which want their operands to look like
reg,displacement(index,basereg) */
#define I370_OPERAND_INDEX (0x04)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
#define I370_OPERAND_GPR (0x08)
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
#define I370_OPERAND_FPR (0x10)
/* This operand is a displacement. */
#define I370_OPERAND_RELATIVE (0x20)
/* This operand is a length, such as that in SS form instructions. */
#define I370_OPERAND_LENGTH (0x40)
/* This operand is optional, and is zero if omitted. This is used for
the optional B2 field in the shift-left, shift-right instructions. The
assembler must count the number of operands remaining on the line,
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
print this operand out only if it is not zero. */
#define I370_OPERAND_OPTIONAL (0x80)
/* Define some misc macros. We keep them with the operands table
for simplicity. The macro table is an array of struct i370_macro. */
struct i370_macro
{
/* The macro name. */
const char *name;
/* The number of operands the macro takes. */
unsigned int operands;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The values are the
same as those for the struct i370_opcode flags field. */
unsigned long flags;
/* A format string to turn the macro into a normal instruction.
Each %N in the string is replaced with operand number N (zero
based). */
const char *format;
};
extern const struct i370_macro i370_macros[];
extern const int i370_num_macros;
#endif /* I370_H */

32
ld/ChangeLog
View File

@ -1,3 +1,35 @@
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove i370 support.
* configure.tgt: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* emulparams/elf32i370.sh: Delete.
* scripttempl/elfi370.sc: Delete.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove h8500 support.

4
ld/Makefile.am
View File

@ -241,7 +241,6 @@ ALL_EMULATION_SOURCES = \
eelf32frv.c \
eelf32frvfd.c \
eelf32ft32.c \
eelf32i370.c \
eelf32ip2k.c \
eelf32iq10.c \
eelf32iq2000.c \
@ -1097,9 +1096,6 @@ eelf32frvfd.c: $(srcdir)/emulparams/elf32frvfd.sh \
eelf32ft32.c: $(srcdir)/emulparams/elf32ft32.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS}
eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}

5
ld/Makefile.in
View File

@ -610,7 +610,6 @@ ALL_EMULATION_SOURCES = \
eelf32frv.c \
eelf32frvfd.c \
eelf32ft32.c \
eelf32i370.c \
eelf32ip2k.c \
eelf32iq10.c \
eelf32iq2000.c \
@ -1212,7 +1211,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frv.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32frvfd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ft32.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32i370.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ip2k.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32iq10.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32iq2000.Po@am__quote@
@ -2639,9 +2637,6 @@ eelf32frvfd.c: $(srcdir)/emulparams/elf32frvfd.sh \
eelf32ft32.c: $(srcdir)/emulparams/elf32ft32.sh \
$(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS}
eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}

2
ld/configure.tgt
View File

@ -232,8 +232,6 @@ hppa*-*-lites*) targ_emul=hppaelf ;;
hppa*-*-netbsd*) targ_emul=hppanbsd ;;
hppa*-*-openbsd*) targ_emul=hppaobsd
;;
i370-*-elf* | i370-*-linux-*) targ_emul=elf32i370
;;
i[3-7]86-*-nto-qnx*) targ_emul=i386nto ;;
i[3-7]86-*-vsta) targ_emul=vsta ;;
i[3-7]86-*-go32) targ_emul=i386go32 ;;

8
ld/emulparams/elf32i370.sh
View File

@ -1,8 +0,0 @@
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
SCRIPT_NAME=elfi370
OUTPUT_FORMAT="elf32-i370"
TEXT_START_ADDR=0x01800000
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
ARCH=i370
MACHINE=

1
ld/po/BLD-POTFILES.in
View File

@ -112,7 +112,6 @@ eelf32fr30.c
eelf32frv.c
eelf32frvfd.c
eelf32ft32.c
eelf32i370.c
eelf32ip2k.c
eelf32iq10.c
eelf32iq2000.c

206
ld/scripttempl/elfi370.sc
View File

@ -1,206 +0,0 @@
# Copyright (C) 2014-2018 Free Software Foundation, Inc.
#
# Copying and distribution of this file, with or without modification,
# are permitted in any medium without royalty provided the copyright
# notice and this notice are preserved.
#
# This is just a raw copy of elfppc.sc and has not been otherwise modified
#
# Unusual variables checked by this code:
# NOP - four byte opcode for no-op (defaults to 0)
# DATA_ADDR - if end-of-text-plus-one-page isn't right for data start
# OTHER_READONLY_SECTIONS - other than .text .init .rodata ...
# (e.g., .PARISC.milli)
# OTHER_READWRITE_SECTIONS - other than .data .bss .ctors .sdata ...
# (e.g., .PARISC.global)
# ATTRS_SECTIONS - at the end
# OTHER_SECTIONS - at the end
# EXECUTABLE_SYMBOLS - symbols that must be defined for an
# executable (e.g., _DYNAMIC_LINK)
# TEXT_START_SYMBOLS - symbols that appear at the start of the
# .text section.
# DATA_START_SYMBOLS - symbols that appear at the start of the
# .data section.
# OTHER_BSS_SYMBOLS - symbols that appear at the start of the
# .bss section besides __bss_start.
#
# When adding sections, do note that the names of some sections are used
# when specifying the start address of the next.
test -z "$ENTRY" && ENTRY=_start
test -z "${BIG_OUTPUT_FORMAT}" && BIG_OUTPUT_FORMAT=${OUTPUT_FORMAT}
test -z "${LITTLE_OUTPUT_FORMAT}" && LITTLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
test -z "$ATTRS_SECTIONS" && ATTRS_SECTIONS=".gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }"
test "$LD_FLAG" = "N" && DATA_ADDR=.
SBSS2=".sbss2 ${RELOCATING-0} : { *(.sbss2) }"
SDATA2=".sdata2 ${RELOCATING-0} : { *(.sdata2) }"
INTERP=".interp ${RELOCATING-0} : { *(.interp) }"
PLT=".plt ${RELOCATING-0} : { *(.plt) }"
cat <<EOF
/* Copyright (C) 2014-2018 Free Software Foundation, Inc.
Copying and distribution of this script, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. */
OUTPUT_FORMAT("${OUTPUT_FORMAT}", "${BIG_OUTPUT_FORMAT}",
"${LITTLE_OUTPUT_FORMAT}")
OUTPUT_ARCH(${ARCH})
${RELOCATING+ENTRY(${ENTRY})}
${RELOCATING+${LIB_SEARCH_DIRS}}
${RELOCATING+/* Do we need any of these for elf?
__DYNAMIC = 0; ${STACKZERO+${STACKZERO}} ${SHLIB_PATH+${SHLIB_PATH}} */}
${RELOCATING+${EXECUTABLE_SYMBOLS}}
${RELOCATING- /* For some reason, the Solaris linker makes bad executables
if gld -r is used and the intermediate file has sections starting
at non-zero addresses. Could be a Solaris ld bug, could be a GNU ld
bug. But for now assigning the zero vmas works. */}
${RELOCATING+PROVIDE (__stack = 0);}
SECTIONS
{
/* Read-only sections, merged into text segment: */
${CREATE_SHLIB-${RELOCATING+. = ${TEXT_START_ADDR} + SIZEOF_HEADERS;}}
${CREATE_SHLIB+${RELOCATING+. = SIZEOF_HEADERS;}}
${CREATE_SHLIB-${INTERP}}
.hash ${RELOCATING-0} : { *(.hash) }
.dynsym ${RELOCATING-0} : { *(.dynsym) }
.dynstr ${RELOCATING-0} : { *(.dynstr) }
.gnu.version ${RELOCATING-0} : { *(.gnu.version) }
.gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) }
.gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) }
.rela.text ${RELOCATING-0} :
{ *(.rela.text) *(.rela.gnu.linkonce.t*) }
.rela.data ${RELOCATING-0} :
{ *(.rela.data) *(.rela.gnu.linkonce.d*) }
.rela.rodata ${RELOCATING-0} :
{ *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
.rela.got ${RELOCATING-0} : { *(.rela.got) }
.rela.got1 ${RELOCATING-0} : { *(.rela.got1) }
.rela.got2 ${RELOCATING-0} : { *(.rela.got2) }
.rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }
.rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }
.rela.init ${RELOCATING-0} : { *(.rela.init) }
.rela.fini ${RELOCATING-0} : { *(.rela.fini) }
.rela.bss ${RELOCATING-0} : { *(.rela.bss) }
.rela.plt ${RELOCATING-0} : { *(.rela.plt) }
.rela.sdata ${RELOCATING-0} : { *(.rela.sdata) }
.rela.sbss ${RELOCATING-0} : { *(.rela.sbss) }
.rela.sdata2 ${RELOCATING-0} : { *(.rela.sdata2) }
.rela.sbss2 ${RELOCATING-0} : { *(.rela.sbss2) }
.text ${RELOCATING-0} :
{
${RELOCATING+${TEXT_START_SYMBOLS}}
*(.text)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.gnu.linkonce.t*)
} =${NOP-0}
.init ${RELOCATING-0} : { *(.init) } =${NOP-0}
.fini ${RELOCATING-0} : { *(.fini) } =${NOP-0}
.rodata ${RELOCATING-0} : { *(.rodata) *(.gnu.linkonce.r*) }
.rodata1 ${RELOCATING-0} : { *(.rodata1) }
${RELOCATING+_etext = .;}
${RELOCATING+PROVIDE (etext = .);}
${CREATE_SHLIB-${SDATA2}}
${CREATE_SHLIB-${SBSS2}}
${OTHER_READONLY_SECTIONS}
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. It would
be more correct to do this:
${RELOCATING+. = ${DATA_ADDR-ALIGN(${MAXPAGESIZE}) + (ALIGN(8) & (${MAXPAGESIZE} - 1))};}
The current expression does not correctly handle the case of a
text segment ending precisely at the end of a page; it causes the
data segment to skip a page. The above expression does not have
this problem, but it will currently (2/95) cause BFD to allocate
a single segment, combining both text and data, for this case.
This will prevent the text segment from being shared among
multiple executions of the program; I think that is more
important than losing a page of the virtual address space (note
that no actual memory is lost; the page which is skipped can not
be referenced). */
${RELOCATING+. = ${DATA_ADDR- ALIGN(8) + ${MAXPAGESIZE}};}
.data ${RELOCATING-0} :
{
${RELOCATING+${DATA_START_SYMBOLS}}
*(.data)
*(.gnu.linkonce.d*)
${CONSTRUCTING+CONSTRUCTORS}
}
.data1 ${RELOCATING-0} : { *(.data1) }
${OTHER_READWRITE_SECTIONS}
.got1 ${RELOCATING-0} : { *(.got1) }
.dynamic ${RELOCATING-0} : { *(.dynamic) }
/* Put .ctors and .dtors next to the .got2 section, so that the pointers
get relocated with -mrelocatable. Also put in the .fixup pointers.
The current compiler no longer needs this, but keep it around for 2.7.2 */
${RELOCATING+PROVIDE (_GOT2_START_ = .);}
.got2 ${RELOCATING-0} : { *(.got2) }
${RELOCATING+PROVIDE (__CTOR_LIST__ = .);}
.ctors ${RELOCATING-0} : { *(.ctors) }
${RELOCATING+PROVIDE (__CTOR_END__ = .);}
${RELOCATING+PROVIDE (__DTOR_LIST__ = .);}
.dtors ${RELOCATING-0} : { *(.dtors) }
${RELOCATING+PROVIDE (__DTOR_END__ = .);}
${RELOCATING+PROVIDE (_FIXUP_START_ = .);}
.fixup ${RELOCATING-0} : { *(.fixup) }
${RELOCATING+PROVIDE (_FIXUP_END_ = .);}
${RELOCATING+PROVIDE (_GOT2_END_ = .);}
${RELOCATING+PROVIDE (_GOT_START_ = .);}
.got ${RELOCATING-0} : { *(.got) }
.got.plt ${RELOCATING-0} : { *(.got.plt) }
${CREATE_SHLIB+${SDATA2}}
${CREATE_SHLIB+${SBSS2}}
${RELOCATING+PROVIDE (_GOT_END_ = .);}
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata ${RELOCATING-0} : { *(.sdata) }
${RELOCATING+_edata = .;}
${RELOCATING+PROVIDE (edata = .);}
.sbss ${RELOCATING-0} :
{
${RELOCATING+PROVIDE (__sbss_start = .);}
*(.sbss)
*(.scommon)
*(.dynsbss)
${RELOCATING+PROVIDE (__sbss_end = .);}
}
${PLT}
.bss ${RELOCATING-0} :
{
${RELOCATING+${OTHER_BSS_SYMBOLS}}
${RELOCATING+PROVIDE (__bss_start = .);}
*(.dynbss)
*(.bss)
*(COMMON)
}
${RELOCATING+_end = . ;}
${RELOCATING+PROVIDE (end = .);}
/* These are needed for ELF backends which have not yet been
converted to the new style linker. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
EOF
. $srcdir/scripttempl/DWARF.sc
cat <<EOF
${ATTRS_SECTIONS}
${OTHER_SECTIONS}
}
EOF

2
ld/testsuite/ld-elf/compressed1d.d
View File

@ -2,7 +2,7 @@
#as: --compress-debug-sections=none
#ld: -r --compress-debug-sections=zlib-gnu
#readelf: -SW
#notarget: d30v-*-* dlx-*-* fr30-*-* frv-*-* ft32-*-* i370-*-* iq2000-*-* mn10200-*-* moxie-*-* msp430-*-* mt-*-* or1k-*-* pj-*-* riscv*-*-*
#notarget: d30v-*-* dlx-*-* fr30-*-* frv-*-* ft32-*-* iq2000-*-* mn10200-*-* moxie-*-* msp430-*-* mt-*-* or1k-*-* pj-*-* riscv*-*-*
# Not all ELF targets use the elf.em emulation...
# RISC-V has linker relaxations that delete code, so text label subtractions
# do not get resolved at assembly time, which results in a compressed section.

2
ld/testsuite/ld-elf/group8a.d
View File

@ -2,7 +2,7 @@
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
#notarget: d30v-*-* dlx-*-* pj*-*-* pru-*-*
#notarget: hppa64-*-* i370-*-* ia64-*-* mep-*-* mn10200-*-*
#notarget: hppa64-*-* ia64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
# cr16 and crx use non-standard scripts with memory regions, which don't play

2
ld/testsuite/ld-elf/group8b.d
View File

@ -2,7 +2,7 @@
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
#xfail: d30v-*-* dlx-*-* pj*-*-* pru-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
# cr16 and crx use non-standard scripts with memory regions, which don't play

2
ld/testsuite/ld-elf/group9a.d
View File

@ -2,7 +2,7 @@
#ld: -r --gc-sections --entry foo
#readelf: -g --wide
#xfail: d30v-*-* dlx-*-* pj*-*-* pru-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
# cr16 and crx use non-standard scripts with memory regions, which don't play

2
ld/testsuite/ld-elf/group9b.d
View File

@ -2,7 +2,7 @@
#ld: -r --gc-sections --entry bar
#readelf: -g --wide
#xfail: d30v-*-* dlx-*-* pj*-*-* pru-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
# cr16 and crx use non-standard scripts with memory regions, which don't play

2
ld/testsuite/ld-elf/merge.d
View File

@ -3,7 +3,7 @@
#objdump: -s
#xfail: "bfin-*-*" "cr16-*-*" "cris*-*-*" "crx-*-*" "d10v-*-*" "d30v-*-*"
#xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*64*-*-*" "h8300-*-*" "score-*-*"
#xfail: "i370-*-*" "ip2k-*-*" "iq2000-*-*" "lm32-*-*"
#xfail: "ip2k-*-*" "iq2000-*-*" "lm32-*-*"
#xfail: "mcore-*-*" "mn102*-*-*" "ms1-*-*" "mep-*-*" "m68hc11-*-*" "nios2-*-*"
#xfail: "or32-*-*" "pj-*-*" "tic6x-*-*" "vax-*-*" "xstormy16-*-*"
#xfail: "xtensa*-*-*" "metag-*-*" "ft32-*-*" "pru-*-*"

2
ld/testsuite/ld-elf/pr12851.d
View File

@ -3,7 +3,7 @@
#ld: --gc-sections
#readelf: -s --wide
#xfail: d30v-*-* dlx-*-* pj*-*-* pru-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr12975.d
View File

@ -2,7 +2,7 @@
#readelf: -s --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#failif

2
ld/testsuite/ld-elf/pr13177.d
View File

@ -3,7 +3,7 @@
#readelf: -s -D --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#failif

2
ld/testsuite/ld-elf/pr13195.d
View File

@ -2,7 +2,7 @@
#readelf: -s --wide -D
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr17615.d
View File

@ -2,7 +2,7 @@
#readelf: -S --wide --dyn-syms
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562a.d
View File

@ -2,7 +2,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562b.d
View File

@ -2,7 +2,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562c.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562d.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562i.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562j.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562k.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562l.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562m.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr21562n.d
View File

@ -3,7 +3,7 @@
#readelf: -s -S --wide
#target: *-*-linux* *-*-gnu*
#xfail: d30v-*-* dlx-*-* pj*-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
# generic linker targets don't support --gc-sections, nor do a bunch of others
#...

2
ld/testsuite/ld-elf/pr22677.d
View File

@ -1,7 +1,7 @@
#ld: -r --gc-sections -u foo
#readelf: -S --wide
#xfail: d30v-*-* dlx-*-* pj*-*-* pru-*-*
#xfail: hppa64-*-* i370-*-* mep-*-* mn10200-*-*
#xfail: hppa64-*-* mep-*-* mn10200-*-*
#xfail: cr16-*-* crx-*-* msp430-*-*
# msp430 puts the init_array and fini_array inside the .rodata section.
# generic linker targets don't support --gc-sections, nor do a bunch of

1
ld/testsuite/lib/ld-lib.exp
View File

@ -1779,7 +1779,6 @@ proc check_gc_sections_available { } {
|| [istarget pru*-*-*]
|| [istarget alpha-*-*]
|| [istarget hppa*64-*-*]
|| [istarget i370-*-*]
|| [istarget ia64-*-*]
|| [istarget mep-*-*]
|| [istarget mn10200-*-*] } {

12
opcodes/ChangeLog
View File

@ -1,3 +1,15 @@
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove i370 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* i370-dis.c: Delete.
* i370-opc.c: Delete.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
2018-04-16 Alan Modra <amodra@gmail.com>
* Makefile.am: Remove h8500 support.

2
opcodes/Makefile.am
View File

@ -138,8 +138,6 @@ TARGET_LIBOPCODES_CFILES = \
ft32-opc.c \
h8300-dis.c \
hppa-dis.c \
i370-dis.c \
i370-opc.c \
i386-dis.c \
i386-opc.c \
ia64-dis.c \

4
opcodes/Makefile.in
View File

@ -440,8 +440,6 @@ TARGET_LIBOPCODES_CFILES = \
ft32-opc.c \
h8300-dis.c \
hppa-dis.c \
i370-dis.c \
i370-opc.c \
i386-dis.c \
i386-opc.c \
ia64-dis.c \
@ -846,8 +844,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ft32-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/h8300-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hppa-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i370-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i370-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i386-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i386-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ia64-dis.Plo@am__quote@

1
opcodes/configure vendored
View File

@ -12646,7 +12646,6 @@ if test x${all_targets} = xfalse ; then
bfd_moxie_arch) ta="$ta moxie-dis.lo moxie-opc.lo" ;;
bfd_h8300_arch) ta="$ta h8300-dis.lo" ;;
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;;
bfd_i386_arch|bfd_iamcu_arch|bfd_l1om_arch|bfd_k1om_arch)
ta="$ta i386-dis.lo i386-opc.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;

1
opcodes/configure.ac
View File

@ -270,7 +270,6 @@ if test x${all_targets} = xfalse ; then
bfd_moxie_arch) ta="$ta moxie-dis.lo moxie-opc.lo" ;;
bfd_h8300_arch) ta="$ta h8300-dis.lo" ;;
bfd_hppa_arch) ta="$ta hppa-dis.lo" ;;
bfd_i370_arch) ta="$ta i370-dis.lo i370-opc.lo" ;;
bfd_i386_arch|bfd_iamcu_arch|bfd_l1om_arch|bfd_k1om_arch)
ta="$ta i386-dis.lo i386-opc.lo" ;;
bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;;

6
opcodes/disassemble.c
View File

@ -42,7 +42,6 @@
#define ARCH_ft32
#define ARCH_h8300
#define ARCH_hppa
#define ARCH_i370
#define ARCH_i386
#define ARCH_ia64
#define ARCH_ip2k
@ -201,11 +200,6 @@ disassembler (enum bfd_architecture a,
disassemble = print_insn_hppa;
break;
#endif
#ifdef ARCH_i370
case bfd_arch_i370:
disassemble = print_insn_i370;
break;
#endif
#ifdef ARCH_i386
case bfd_arch_i386:
case bfd_arch_iamcu:

1
opcodes/disassemble.h
View File

@ -43,7 +43,6 @@ extern int print_insn_h8300 (bfd_vma, disassemble_info *);
extern int print_insn_h8300h (bfd_vma, disassemble_info *);
extern int print_insn_h8300s (bfd_vma, disassemble_info *);
extern int print_insn_hppa (bfd_vma, disassemble_info *);
extern int print_insn_i370 (bfd_vma, disassemble_info *);
extern int print_insn_i386 (bfd_vma, disassemble_info *);
extern int print_insn_i386_att (bfd_vma, disassemble_info *);
extern int print_insn_i386_intel (bfd_vma, disassemble_info *);

161
opcodes/i370-dis.c
View File

@ -1,161 +0,0 @@
/* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions
Copyright (C) 1994-2018 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org>
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include <stdio.h>
#include "disassemble.h"
#include "opcode/i370.h"
/* This file provides several disassembler functions, all of which use
the disassembler interface defined in dis-asm.h. */
int
print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info)
{
bfd_byte buffer[8];
int status;
i370_insn_t insn;
const struct i370_opcode *opcode;
const struct i370_opcode *opcode_end;
status = (*info->read_memory_func) (memaddr, buffer, 6, info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
/* Cast the bytes into the insn (in a host-endian indep way). */
insn.i[0] = (buffer[0] << 24) & 0xff000000;
insn.i[0] |= (buffer[1] << 16) & 0xff0000;
insn.i[0] |= (buffer[2] << 8) & 0xff00;
insn.i[0] |= buffer[3] & 0xff;
insn.i[1] = (buffer[4] << 24) & 0xff000000;
insn.i[1] |= (buffer[5] << 16) & 0xff0000;
/* Find the first match in the opcode table. We could speed this up
a bit by doing a binary search on the major opcode. */
opcode_end = i370_opcodes + i370_num_opcodes;
for (opcode = i370_opcodes; opcode < opcode_end; opcode++)
{
const unsigned char *opindex;
const struct i370_operand *operand;
i370_insn_t masked;
int invalid;
/* Mask off operands, and look for a match ... */
masked = insn;
if (2 == opcode->len)
{
masked.i[0] >>= 16;
masked.i[0] &= 0xffff;
}
masked.i[0] &= opcode->mask.i[0];
if (masked.i[0] != opcode->opcode.i[0])
continue;
if (6 == opcode->len)
{
masked.i[1] &= opcode->mask.i[1];
if (masked.i[1] != opcode->opcode.i[1])
continue;
}
/* Found a match. adjust a tad. */
if (2 == opcode->len)
{
insn.i[0] >>= 16;
insn.i[0] &= 0xffff;
}
/* Make two passes over the operands. First see if any of them
have extraction functions, and, if they do, make sure the
instruction is valid. */
invalid = 0;
for (opindex = opcode->operands; *opindex != 0; opindex++)
{
operand = i370_operands + *opindex;
if (operand->extract)
(*operand->extract) (insn, &invalid);
}
if (invalid)
continue;
/* The instruction is valid. */
(*info->fprintf_func) (info->stream, "%s", opcode->name);
if (opcode->operands[0] != 0)
(*info->fprintf_func) (info->stream, "\t");
/* Now extract and print the operands. */
for (opindex = opcode->operands; *opindex != 0; opindex++)
{
long value;
operand = i370_operands + *opindex;
/* Extract the value from the instruction. */
if (operand->extract)
value = (*operand->extract) (insn, (int *) NULL);
else
value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);
/* Print the operand as directed by the flags. */
if ((operand->flags & I370_OPERAND_OPTIONAL) != 0)
{
if (value)
(*info->fprintf_func) (info->stream, "(r%ld)", value);
}
else if ((operand->flags & I370_OPERAND_SBASE) != 0)
{
(*info->fprintf_func) (info->stream, "(r%ld)", value);
}
else if ((operand->flags & I370_OPERAND_INDEX) != 0)
{
if (value)
(*info->fprintf_func) (info->stream, "(r%ld,", value);
else
(*info->fprintf_func) (info->stream, "(,");
}
else if ((operand->flags & I370_OPERAND_LENGTH) != 0)
{
(*info->fprintf_func) (info->stream, "(%ld,", value);
}
else if ((operand->flags & I370_OPERAND_BASE) != 0)
(*info->fprintf_func) (info->stream, "r%ld)", value);
else if ((operand->flags & I370_OPERAND_GPR) != 0)
(*info->fprintf_func) (info->stream, "r%ld,", value);
else if ((operand->flags & I370_OPERAND_FPR) != 0)
(*info->fprintf_func) (info->stream, "f%ld,", value);
else if ((operand->flags & I370_OPERAND_RELATIVE) != 0)
(*info->fprintf_func) (info->stream, "%ld", value);
else
(*info->fprintf_func) (info->stream, " %ld, ", value);
}
return opcode->len;
}
/* We could not find a match. */
(*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]);
return 2;
}

935
opcodes/i370-opc.c
View File

@ -1,935 +0,0 @@
/* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
Copyright (C) 1994-2018 Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#include "sysdep.h"
#include <stdio.h>
#include "opcode/i370.h"
/* This file holds the i370 opcode table. The opcode table
includes almost all of the extended instruction mnemonics. This
permits the disassembler to use them, and simplifies the assembler
logic, at the cost of increasing the table size. The table is
strictly constant data, so the compiler should be able to put it in
the .text section.
This file also holds the operand table. All knowledge about
inserting operands into instructions and vice-versa is kept in this
file. */
/* The functions used to insert and extract complicated operands. */
static i370_insn_t
insert_ss_b2 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
}
static i370_insn_t
insert_ss_d2 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xfff) << 16;
return insn;
}
static i370_insn_t
insert_rxf_r3 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
{
insn.i[1] |= (value & 0xf) << 28;
return insn;
}
static long
extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>28) & 0xf;
}
static long
extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>16) & 0xfff;
}
static long
extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
{
return (insn.i[1] >>28) & 0xf;
}
/* The operands table.
The fields are bits, shift, insert, extract, flags, name.
The types:
I370_OPERAND_GPR register, must name a register, must be present
I370_OPERAND_RELATIVE displacement or legnth field, must be present
I370_OPERAND_BASE base register; if present, must name a register
if absent, should take value of zero
I370_OPERAND_INDEX index register; if present, must name a register
if absent, should take value of zero
I370_OPERAND_OPTIONAL other optional operand (usuall reg?). */
const struct i370_operand i370_operands[] =
{
/* The zero index is used to indicate the end of the list of
operands. */
#define UNUSED 0
{ 0, 0, 0, 0, 0, "unused" },
/* The R1 register field in an RR form instruction. */
#define RR_R1 (UNUSED + 1)
#define RR_R1_MASK (0xf << 4)
{ 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" },
/* The R2 register field in an RR form instruction. */
#define RR_R2 (RR_R1 + 1)
#define RR_R2_MASK (0xf)
{ 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" },
/* The I field in an RR form SVC-style instruction. */
#define RR_I (RR_R2 + 1)
#define RR_I_MASK (0xff)
{ 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" },
/* The R1 register field in an RRE form instruction. */
#define RRE_R1 (RR_I + 1)
#define RRE_R1_MASK (0xf << 4)
{ 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" },
/* The R2 register field in an RRE form instruction. */
#define RRE_R2 (RRE_R1 + 1)
#define RRE_R2_MASK (0xf)
{ 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" },
/* The R1 register field in an RRF form instruction. */
#define RRF_R1 (RRE_R2 + 1)
#define RRF_R1_MASK (0xf << 4)
{ 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" },
/* The R2 register field in an RRF form instruction. */
#define RRF_R2 (RRF_R1 + 1)
#define RRF_R2_MASK (0xf)
{ 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" },
/* The R3 register field in an RRF form instruction. */
#define RRF_R3 (RRF_R2 + 1)
#define RRF_R3_MASK (0xf << 12)
{ 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" },
/* The R1 register field in an RX or RS form instruction. */
#define RX_R1 (RRF_R3 + 1)
#define RX_R1_MASK (0xf << 20)
{ 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" },
/* The X2 index field in an RX form instruction. */
#define RX_X2 (RX_R1 + 1)
#define RX_X2_MASK (0xf << 16)
{ 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"},
/* The B2 base field in an RX form instruction. */
#define RX_B2 (RX_X2 + 1)
#define RX_B2_MASK (0xf << 12)
{ 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"},
/* The D2 displacement field in an RX form instruction. */
#define RX_D2 (RX_B2 + 1)
#define RX_D2_MASK (0xfff)
{ 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"},
/* The R3 register field in an RXF form instruction. */
#define RXF_R3 (RX_D2 + 1)
#define RXF_R3_MASK (0xf << 12)
{ 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" },
/* The D2 displacement field in an RS form instruction. */
#define RS_D2 (RXF_R3 + 1)
#define RS_D2_MASK (0xfff)
{ 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},
/* The R3 register field in an RS form instruction. */
#define RS_R3 (RS_D2 + 1)
#define RS_R3_MASK (0xf << 16)
{ 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },
/* The B2 base field in an RS form instruction. */
#define RS_B2 (RS_R3 + 1)
#define RS_B2_MASK (0xf << 12)
{ 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},
/* The optional B2 base field in an RS form instruction. */
/* Note that this field will almost always be absent */
#define RS_B2_OPT (RS_B2 + 1)
#define RS_B2_OPT_MASK (0xf << 12)
{ 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},
/* The R1 register field in an RSI form instruction. */
#define RSI_R1 (RS_B2_OPT + 1)
#define RSI_R1_MASK (0xf << 20)
{ 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" },
/* The R3 register field in an RSI form instruction. */
#define RSI_R3 (RSI_R1 + 1)
#define RSI_R3_MASK (0xf << 16)
{ 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" },
/* The I2 immediate field in an RSI form instruction. */
#define RSI_I2 (RSI_R3 + 1)
#define RSI_I2_MASK (0xffff)
{ 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" },
/* The R1 register field in an RI form instruction. */
#define RI_R1 (RSI_I2 + 1)
#define RI_R1_MASK (0xf << 20)
{ 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" },
/* The I2 immediate field in an RI form instruction. */
#define RI_I2 (RI_R1 + 1)
#define RI_I2_MASK (0xffff)
{ 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" },
/* The I2 index field in an SI form instruction. */
#define SI_I2 (RI_I2 + 1)
#define SI_I2_MASK (0xff << 16)
{ 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"},
/* The B1 base register field in an SI form instruction. */
#define SI_B1 (SI_I2 + 1)
#define SI_B1_MASK (0xf << 12)
{ 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" },
/* The D1 displacement field in an SI form instruction. */
#define SI_D1 (SI_B1 + 1)
#define SI_D1_MASK (0xfff)
{ 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" },
/* The B2 base register field in an S form instruction. */
#define S_B2 (SI_D1 + 1)
#define S_B2_MASK (0xf << 12)
{ 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" },
/* The D2 displacement field in an S form instruction. */
#define S_D2 (S_B2 + 1)
#define S_D2_MASK (0xfff)
{ 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },
/* The L length field in an SS form instruction. */
#define SS_L (S_D2 + 1)
#define SS_L_MASK (0xffff<<16)
{ 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },
/* The B1 base register field in an SS form instruction. */
#define SS_B1 (SS_L + 1)
#define SS_B1_MASK (0xf << 12)
{ 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" },
/* The D1 displacement field in an SS form instruction. */
#define SS_D1 (SS_B1 + 1)
#define SS_D1_MASK (0xfff)
{ 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" },
/* The B2 base register field in an SS form instruction. */
#define SS_B2 (SS_D1 + 1)
#define SS_B2_MASK (0xf << 12)
{ 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" },
/* The D2 displacement field in an SS form instruction. */
#define SS_D2 (SS_B2 + 1)
#define SS_D2_MASK (0xfff)
{ 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
};
/* Macros used to form opcodes. */
/* The short-instruction opcode. */
#define OPS(x) ((((unsigned short) (x)) & 0xff) << 8)
#define OPS_MASK OPS (0xff)
/* the extended instruction opcode */
#define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24)
#define XOPS_MASK XOPS (0xff)
/* the S instruction opcode */
#define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16)
#define SOPS_MASK SOPS (0xffff)
/* the E instruction opcode */
#define EOPS(x) (((unsigned short) (x)) & 0xffff)
#define EOPS_MASK EOPS (0xffff)
/* the RI instruction opcode */
#define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \
((((unsigned short) (x)) & 0x00f) << 16))
#define ROPS_MASK ROPS (0xfff)
/* An E form instruction. */
#define E(op) (EOPS (op))
#define E_MASK E (0xffff)
/* An RR form instruction. */
#define RR(op, r1, r2) \
(OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \
((((unsigned short) (r2)) & 0xf) ))
#define RR_MASK RR (0xff, 0x0, 0x0)
/* An SVC-style instruction. */
#define SVC(op, i) \
(OPS (op) | (((unsigned short) (i)) & 0xff))
#define SVC_MASK SVC (0xff, 0x0)
/* An RRE form instruction. */
#define RRE(op, r1, r2) \
(SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \
((((unsigned short) (r2)) & 0xf) ))
#define RRE_MASK RRE (0xffff, 0x0, 0x0)
/* An RRF form instruction. */
#define RRF(op, r3, r1, r2) \
(SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) | \
((((unsigned short) (r1)) & 0xf) << 4) | \
((((unsigned short) (r2)) & 0xf) ))
#define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
/* An RX form instruction. */
#define RX(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (x2)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
/* An RXE form instruction high word. */
#define RXEH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (x2)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
/* An RXE form instruction low word. */
#define RXEL(op) \
((((unsigned short) (op)) & 0xff) << 16 )
#define RXEL_MASK RXEL (0xff)
/* An RXF form instruction high word. */
#define RXFH(op, r1, x2, b2, d2) \
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (x2)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
/* An RXF form instruction low word. */
#define RXFL(op, r3) \
(((((unsigned short) (r3)) & 0xf) << 28 ) | \
((((unsigned short) (op)) & 0xff) << 16 ))
#define RXFL_MASK RXFL (0xff, 0)
/* An RS form instruction. */
#define RS(op, r1, b3, b2, d2) \
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (b3)) & 0xf) << 16) | \
((((unsigned short) (b2)) & 0xf) << 12) | \
((((unsigned short) (d2)) & 0xfff)))
#define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
/* An RSI form instruction. */
#define RSI(op, r1, r3, i2) \
(XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (r3)) & 0xf) << 16) | \
((((unsigned short) (i2)) & 0xffff)))
#define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
/* An RI form instruction. */
#define RI(op, r1, i2) \
(ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \
((((unsigned short) (i2)) & 0xffff)))
#define RI_MASK RI (0xfff, 0x0, 0x0)
/* An SI form instruction. */
#define SI(op, i2, b1, d1) \
(XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) | \
((((unsigned short) (b1)) & 0xf) << 12) | \
((((unsigned short) (d1)) & 0xfff)))
#define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
/* An S form instruction. */
#define S(op, b2, d2) \
(SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) | \
((((unsigned short)(d2)) & 0xfff)))
#define S_MASK S (0xffff, 0x0, 0x0)
/* An SS form instruction high word. */
#define SSH(op, l, b1, d1) \
(XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) | \
((((unsigned short) (b1)) & 0xf) << 12) | \
((((unsigned short) (d1)) & 0xfff)))
/* An SS form instruction low word. */
#define SSL(b2, d2) \
( ((((unsigned short) (b1)) & 0xf) << 28) | \
((((unsigned short) (d1)) & 0xfff) << 16 ))
#define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
/* An SSE form instruction high word. */
#define SSEH(op, b1, d1) \
(SOPS(op) | ((((unsigned short) (b1)) & 0xf) << 12) | \
((((unsigned short) (d1)) & 0xfff)))
/* An SSE form instruction low word. */
#define SSEL(b2, d2) \
( ((((unsigned short) (b1)) & 0xf) << 28) | \
((((unsigned short) (d1)) & 0xfff) << 16 ))
#define SSE_MASK SSEH (0xffff, 0x0, 0x0)
/* Smaller names for the flags so each entry in the opcodes table will
fit on a single line. These flags are set up so that e.g. IXA means
the insn is supported on the 370/XA or newer architecture.
Note that 370 or older obsolete insn's are not supported ... */
#define IBF I370_OPCODE_ESA390_BF
#define IBS I370_OPCODE_ESA390_BS
#define ICK I370_OPCODE_ESA390_CK
#define ICM I370_OPCODE_ESA390_CM
#define IFX I370_OPCODE_ESA390_FX
#define IHX I370_OPCODE_ESA390_HX
#define IIR I370_OPCODE_ESA390_IR
#define IMI I370_OPCODE_ESA390_MI
#define IPC I370_OPCODE_ESA390_PC
#define IPL I370_OPCODE_ESA390_PL
#define IQR I370_OPCODE_ESA390_QR
#define IRP I370_OPCODE_ESA390_RP
#define ISA I370_OPCODE_ESA390_SA
#define ISG I370_OPCODE_ESA390_SG
#define ISR I370_OPCODE_ESA390_SR
#define ITR I370_OPCODE_ESA390_SR
#define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
#define IESA I390 | I370_OPCODE_ESA370
#define IXA IESA | I370_OPCODE_370_XA
#define I370 IXA | I370_OPCODE_370
#define I360 I370 | I370_OPCODE_360
/* The opcode table.
The format of the opcode table is:
NAME LEN OPCODE_HI OPCODE_LO MASK_HI MASK_LO FLAGS { OPERANDS }
NAME is the name of the instruction.
OPCODE is the instruction opcode.
MASK is the opcode mask; this is used to tell the disassembler
which bits in the actual opcode must match OPCODE.
FLAGS are flags indicated what processors support the instruction.
OPERANDS is the list of operands.
The disassembler reads the table in order and prints the first
instruction which matches, so this table is sorted to put more
specific instructions before more general instructions. It is also
sorted by major opcode. */
const struct i370_opcode i370_opcodes[] =
{
/* E form instructions */
{ "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} },
{ "trap2", 2, {{E(0x01FF), 0}}, {{E_MASK, 0}}, ITR, {0} },
{ "upt", 2, {{E(0x0102), 0}}, {{E_MASK, 0}}, IXA, {0} },
/* RR form instructions */
{ "ar", 2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "adr", 2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "aer", 2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "alr", 2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "aur", 2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "awr", 2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "axr", 2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "balr", 2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "basr", 2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
{ "bassm", 2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
{ "bsm", 2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA, {RR_R1, RR_R2} },
{ "bcr", 2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "bctr", 2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "cdr", 2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "cer", 2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "clr", 2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "clcl", 2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "cr", 2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ddr", 2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "der", 2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "dr", 2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "hdr", 2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "her", 2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lcdr", 2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lcer", 2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lcr", 2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ldr", 2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ler", 2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lndr", 2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lner", 2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lnr", 2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lpdr", 2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lper", 2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lpr", 2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lr", 2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lrdr", 2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lrer", 2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ltdr", 2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "lter", 2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ltr", 2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mdr", 2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mer", 2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mr", 2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mvcl", 2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mxdr", 2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "mxr", 2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "nr", 2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "or", 2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "sdr", 2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "ser", 2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "slr", 2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "spm", 2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1} },
{ "sr", 2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "sur", 2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "swr", 2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
{ "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} },
/* Unusual RR formats. */
{ "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} },
/* RRE form instructions. */
{ "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "bakr", 4, {{RRE(0xb240,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "bsa", 4, {{RRE(0xb25a,0,0), 0}}, {{RRE_MASK, 0}}, IBS, {RRE_R1, RRE_R2} },
{ "bsg", 4, {{RRE(0xb258,0,0), 0}}, {{RRE_MASK, 0}}, ISG, {RRE_R1, RRE_R2} },
{ "cdbr", 4, {{RRE(0xb319,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cdfbr", 4, {{RRE(0xb395,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cdfr", 4, {{RRE(0xb3b5,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "cebr", 4, {{RRE(0xb309,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cefbr", 4, {{RRE(0xb394,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cefr", 4, {{RRE(0xb3b4,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "cksm", 4, {{RRE(0xb241,0,0), 0}}, {{RRE_MASK, 0}}, ICK, {RRE_R1, RRE_R2} },
{ "clst", 4, {{RRE(0xb25d,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
{ "cpya", 4, {{RRE(0xb24d,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "cuse", 4, {{RRE(0xb257,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "cxbr", 4, {{RRE(0xb349,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cxfbr", 4, {{RRE(0xb396,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "cxfr", 4, {{RRE(0xb3b6,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "cxr", 4, {{RRE(0xb369,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "ddbr", 4, {{RRE(0xb31d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "debr", 4, {{RRE(0xb30d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "dxbr", 4, {{RRE(0xb34d,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "dxr", 4, {{RRE(0xb22d,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "ear", 4, {{RRE(0xb24f,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "efpc", 4, {{RRE(0xb38c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "epar", 4, {{RRE(0xb226,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "ereg", 4, {{RRE(0xb249,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "esar", 4, {{RRE(0xb227,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "esta", 4, {{RRE(0xb24a,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "fidr", 4, {{RRE(0xb37f,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "fier", 4, {{RRE(0xb377,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "fixr", 4, {{RRE(0xb367,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "iac", 4, {{RRE(0xb224,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "ipm", 4, {{RRE(0xb222,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "ipte", 4, {{RRE(0xb221,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "iske", 4, {{RRE(0xb229,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "ivsk", 4, {{RRE(0xb223,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "kdbr", 4, {{RRE(0xb318,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "kebr", 4, {{RRE(0xb308,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "kxbr", 4, {{RRE(0xb348,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcdbr", 4, {{RRE(0xb313,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcebr", 4, {{RRE(0xb303,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcxbr", 4, {{RRE(0xb343,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lcxr", 4, {{RRE(0xb363,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lder", 4, {{RRE(0xb324,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "ldxbr", 4, {{RRE(0xb345,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ledbr", 4, {{RRE(0xb344,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lexbr", 4, {{RRE(0xb346,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lexr", 4, {{RRE(0xb366,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lndbr", 4, {{RRE(0xb311,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lnebr", 4, {{RRE(0xb301,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lnxbr", 4, {{RRE(0xb341,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lnxr", 4, {{RRE(0xb361,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lpdbr", 4, {{RRE(0xb310,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lpebr", 4, {{RRE(0xb300,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lpxbr", 4, {{RRE(0xb340,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "lpxr", 4, {{RRE(0xb360,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "ltdbr", 4, {{RRE(0xb312,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ltebr", 4, {{RRE(0xb302,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ltxbr", 4, {{RRE(0xb342,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "ltxr", 4, {{RRE(0xb362,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lura", 4, {{RRE(0xb24b,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "lxdr", 4, {{RRE(0xb325,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lxer", 4, {{RRE(0xb326,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "lxr", 4, {{RRE(0xb365,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "lzdr", 4, {{RRE(0xb375,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "lzer", 4, {{RRE(0xb374,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "lzxr", 4, {{RRE(0xb376,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "mdbr", 4, {{RRE(0xb31c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "mdebr", 4, {{RRE(0xb30c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "meebr", 4, {{RRE(0xb317,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "meer", 4, {{RRE(0xb337,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "msr", 4, {{RRE(0xb252,0,0), 0}}, {{RRE_MASK, 0}}, IIR, {RRE_R1, RRE_R2} },
{ "msta", 4, {{RRE(0xb247,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} },
{ "mvpg", 4, {{RRE(0xb254,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "mvst", 4, {{RRE(0xb255,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
{ "mxbr", 4, {{RRE(0xb34c,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "mxdbr", 4, {{RRE(0xb307,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "palb", 4, {{RRE(0xb248,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {0} },
{ "prbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} },
{ "pt", 4, {{RRE(0xb228,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "rrbe", 4, {{RRE(0xb22a,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "sar", 4, {{RRE(0xb24e,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "sdbr", 4, {{RRE(0xb31b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sebr", 4, {{RRE(0xb30b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "servc", 4, {{RRE(0xb220,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "sfpc", 4, {{RRE(0xb384,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqdbr", 4, {{RRE(0xb315,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqdr", 4, {{RRE(0xb244,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
{ "sqebr", 4, {{RRE(0xb314,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqer", 4, {{RRE(0xb245,0,0), 0}}, {{RRE_MASK, 0}}, IQR, {RRE_R1, RRE_R2} },
{ "sqxbr", 4, {{RRE(0xb316,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "sqxr", 4, {{RRE(0xb336,0,0), 0}}, {{RRE_MASK, 0}}, IHX, {RRE_R1, RRE_R2} },
{ "srst", 4, {{RRE(0xb25e,0,0), 0}}, {{RRE_MASK, 0}}, ISR, {RRE_R1, RRE_R2} },
{ "ssar", 4, {{RRE(0xb225,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1} },
{ "sske", 4, {{RRE(0xb22b,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "stura", 4, {{RRE(0xb246,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "sxbr", 4, {{RRE(0xb34b,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} },
{ "tar", 4, {{RRE(0xb24c,0,0), 0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
{ "tb", 4, {{RRE(0xb22c,0,0), 0}}, {{RRE_MASK, 0}}, IXA, {RRE_R1, RRE_R2} },
{ "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
{ "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} },
/* RRF form instructions. */
{ "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfer", 4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfxbr", 4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "cfxr", 4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} },
{ "didbr", 4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "diebr", 4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "fidbr", 4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "fiebr", 4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "fixbr", 4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "madbr", 4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "maebr", 4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "msdbr", 4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "msebr", 4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} },
{ "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
{ "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} },
/* RX form instructions. */
{ "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ah", 4, {{RX(0x4a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "al", 4, {{RX(0x5e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "au", 4, {{RX(0x7e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "aw", 4, {{RX(0x6e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bal", 4, {{RX(0x45,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bas", 4, {{RX(0x4d,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bc", 4, {{RX(0x47,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "bct", 4, {{RX(0x46,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "c", 4, {{RX(0x59,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cd", 4, {{RX(0x69,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ce", 4, {{RX(0x79,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ch", 4, {{RX(0x49,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cl", 4, {{RX(0x55,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cvb", 4, {{RX(0x4f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cvd", 4, {{RX(0x4e,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "d", 4, {{RX(0x5d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "dd", 4, {{RX(0x6d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "de", 4, {{RX(0x7d,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ex", 4, {{RX(0x44,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ic", 4, {{RX(0x43,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "l", 4, {{RX(0x58,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "la", 4, {{RX(0x41,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lae", 4, {{RX(0x51,0,0,0,0), 0}}, {{RX_MASK, 0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ld", 4, {{RX(0x68,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "le", 4, {{RX(0x78,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lh", 4, {{RX(0x48,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lra", 4, {{RX(0xb1,0,0,0,0), 0}}, {{RX_MASK, 0}}, IXA, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "m", 4, {{RX(0x5c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "md", 4, {{RX(0x6c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "me", 4, {{RX(0x7c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mh", 4, {{RX(0x4c,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ms", 4, {{RX(0x71,0,0,0,0), 0}}, {{RX_MASK, 0}}, IIR, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mxd", 4, {{RX(0x67,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "n", 4, {{RX(0x54,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "o", 4, {{RX(0x56,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "s", 4, {{RX(0x5b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sd", 4, {{RX(0x6b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "se", 4, {{RX(0x7b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sh", 4, {{RX(0x4b,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sl", 4, {{RX(0x5f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "st", 4, {{RX(0x50,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "stc", 4, {{RX(0x42,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "std", 4, {{RX(0x60,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ste", 4, {{RX(0x70,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sth", 4, {{RX(0x40,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "su", 4, {{RX(0x7f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXE form instructions. */
{ "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ddb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "deb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "kdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "keb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lde", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "ldeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "lxeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mdeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mee", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "meeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "mxdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqd", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqe", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sqeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "sdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "seb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "tcdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
{ "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
/* RXF form instructions. */
{ "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
{ "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
/* RS form instructions. */
{ "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "clcle", 4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "clm", 4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "cs", 4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "icm", 4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "lam", 4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "lctl", 4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "lm", 4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "mvcle", 4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "sigp", 4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stam", 4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stcm", 4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stctl", 4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
{ "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} },
/* RS form instructions with blank R3 and optional B2 (shift left/right). */
{ "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "sll", 4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "sra", 4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "srda", 4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
{ "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
/* RSI form instructions. */
{ "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
{ "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} },
/* RI form instructions. */
{ "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "brct", 4, {{RI(0xa76,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "chi", 4, {{RI(0xa7e,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "lhi", 4, {{RI(0xa78,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "mhi", 4, {{RI(0xa7c,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
{ "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} },
/* SI form instructions. */
{ "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
{ "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
{ "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
{ "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
/* S form instructions. */
{ "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "ipk", 4, {{S(0xb20b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "lfpc", 4, {{S(0xb29d,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
{ "lpsw", 4, {{S(0x8200,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "msch", 4, {{S(0xb232,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "pc", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "pcf", 4, {{S(0xb218,0,0), 0}}, {{S_MASK, 0}}, IPC, {S_D2, S_B2} },
{ "ptlb", 4, {{S(0xb20d,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "rchp", 4, {{S(0xb23b,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "rp", 4, {{S(0xb277,0,0), 0}}, {{S_MASK, 0}}, IRP, {0} },
{ "rsch", 4, {{S(0xb238,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "sac", 4, {{S(0xb219,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "sacf", 4, {{S(0xb279,0,0), 0}}, {{S_MASK, 0}}, ISA, {S_D2, S_B2} },
{ "sal", 4, {{S(0xb237,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "schm", 4, {{S(0xb23c,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} },
{ "sck", 4, {{S(0xb204,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "sckc", 4, {{S(0xb206,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "spka", 4, {{S(0xb20a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "spt", 4, {{S(0xb208,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "spx", 4, {{S(0xb210,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "srnm", 4, {{S(0xb299,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
{ "ssch", 4, {{S(0xb233,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "ssm", 4, {{S(0x8000,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "stap", 4, {{S(0xb212,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stck", 4, {{S(0xb205,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stckc", 4, {{S(0xb207,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "stcps", 4, {{S(0xb23a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stcrw", 4, {{S(0xb239,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stfpc", 4, {{S(0xb29c,0,0), 0}}, {{S_MASK, 0}}, IBF, {S_D2, S_B2} },
{ "stidp", 4, {{S(0xb202,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "stpt", 4, {{S(0xb209,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stpx", 4, {{S(0xb211,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "stsch", 4, {{S(0xb234,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "tpi", 4, {{S(0xb236,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
{ "trap4", 4, {{S(0xb2ff,0,0), 0}}, {{S_MASK, 0}}, ITR, {S_D2, S_B2} },
{ "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} },
{ "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} },
/* SS form instructions. */
{ "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "dp", 6, {{SSH(0xfd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "ed", 6, {{SSH(0xde,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "edmk", 6, {{SSH(0xdf,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvc", 6, {{SSH(0xd2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvcin", 6, {{SSH(0xe8,0,0,0), 0}}, {{SS_MASK, 0}}, IMI, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvck", 6, {{SSH(0xd9,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvcp", 6, {{SSH(0xda,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvcs", 6, {{SSH(0xdb,0,0,0), 0}}, {{SS_MASK, 0}}, IXA, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvn", 6, {{SSH(0xd1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvo", 6, {{SSH(0xf1,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "mvz", 6, {{SSH(0xd3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "nc", 6, {{SSH(0xd4,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "oc", 6, {{SSH(0xd6,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "pack", 6, {{SSH(0xf2,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "plo", 6, {{SSH(0xee,0,0,0), 0}}, {{SS_MASK, 0}}, IPL, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "sp", 6, {{SSH(0xfb,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "srp", 6, {{SSH(0xf0,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "tr", 6, {{SSH(0xdc,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "trt", 6, {{SSH(0xdd,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "unpk", 6, {{SSH(0xf3,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
{ "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
/* SSE form instructions. */
{ "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
{ "tprot", 6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} },
/* */
};
const int i370_num_opcodes =
sizeof (i370_opcodes) / sizeof (i370_opcodes[0]);
/* The macro table. This is only used by the assembler. */
const struct i370_macro i370_macros[] =
{
{ "b", 1, I370, "bc 15,%0" },
{ "br", 1, I370, "bcr 15,%0" },
{ "nop", 1, I370, "bc 0,%0" },
{ "nopr", 1, I370, "bcr 0,%0" },
{ "bh", 1, I370, "bc 2,%0" },
{ "bhr", 1, I370, "bcr 2,%0" },
{ "bl", 1, I370, "bc 4,%0" },
{ "blr", 1, I370, "bcr 4,%0" },
{ "be", 1, I370, "bc 8,%0" },
{ "ber", 1, I370, "bcr 8,%0" },
{ "bnh", 1, I370, "bc 13,%0" },
{ "bnhr", 1, I370, "bcr 13,%0" },
{ "bnl", 1, I370, "bc 11,%0" },
{ "bnlr", 1, I370, "bcr 11,%0" },
{ "bne", 1, I370, "bc 7,%0" },
{ "bner", 1, I370, "bcr 7,%0" },
{ "bp", 1, I370, "bc 2,%0" },
{ "bpr", 1, I370, "bcr 2,%0" },
{ "bm", 1, I370, "bc 4,%0" },
{ "bmr", 1, I370, "bcr 4,%0" },
{ "bz", 1, I370, "bc 8,%0" },
{ "bzr", 1, I370, "bcr 8,%0" },
{ "bo", 1, I370, "bc 1,%0" },
{ "bor", 1, I370, "bcr 1,%0" },
{ "bnp", 1, I370, "bc 13,%0" },
{ "bnpr", 1, I370, "bcr 13,%0" },
{ "bnm", 1, I370, "bc 11,%0" },
{ "bnmr", 1, I370, "bcr 11,%0" },
{ "bnz", 1, I370, "bc 7,%0" },
{ "bnzr", 1, I370, "bcr 7,%0" },
{ "bno", 1, I370, "bc 14,%0" },
{ "bnor", 1, I370, "bcr 14,%0" },
{ "sync", 0, I370, "bcr 15,0" },
};
const int i370_num_macros =
sizeof (i370_macros) / sizeof (i370_macros[0]);

2
opcodes/po/POTFILES.in
View File

@ -60,8 +60,6 @@ ft32-dis.c
ft32-opc.c
h8300-dis.c
hppa-dis.c
i370-dis.c
i370-opc.c
i386-dis.c
i386-gen.c
i386-init.h