Even more instruction tests
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@ -1,5 +1,16 @@
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Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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* sim/m32r/bl24.cgs: Test long BL instruction.
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* sim/m32r/bl8.cgs: Test short BL instruction.
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* sim/m32r/blez.cgs: Test BLEZ instruction.
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* sim/m32r/bltz.cgs: Test BLTZ instruction.
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* sim/m32r/bne.cgs: Test BNE instruction.
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* sim/m32r/bnez.cgs: Test BNEZ instruction.
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* sim/m32r/bra24.cgs: Test long BRA instruction.
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* sim/m32r/bra8.cgs: Test short BRA instruction.
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* sim/m32r/jl.cgs: Test JL instruction.
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* sim/m32r/or.cgs: Test OR instruction.
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* sim/m32r/jmp.cgs: Test JMP instruction.
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* sim/m32r/and.cgs: Test AND instruction.
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* sim/m32r/and.cgs: Test AND instruction.
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* sim/m32r/and3.cgs: Test AND3 instruction.
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* sim/m32r/and3.cgs: Test AND3 instruction.
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* sim/m32r/beq.cgs: Test BEQ instruction.
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* sim/m32r/beq.cgs: Test BEQ instruction.
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@ -11,17 +22,11 @@ Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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* sim/m32r/cmpu.cgs: Test CMPU instruction.
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* sim/m32r/cmpu.cgs: Test CMPU instruction.
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* sim/m32r/cmpui.cgs: Test CMPUI instruction.
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* sim/m32r/cmpui.cgs: Test CMPUI instruction.
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* sim/m32r/div.cgs: Test DIV instruction.
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* sim/m32r/div.cgs: Test DIV instruction.
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* sim/m32r/divh.cgs: Test DIVH instruction.
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* sim/m32r/divu.cgs: Test DIVU instruction.
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* sim/m32r/bcl8.cgs: Test short BCL instruction.
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* sim/m32r/bncl24.cgs: Test long BNCL instruction.
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* sim/m32r/bncl8.cgs: Test short BNCL instruction.
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* sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
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* sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
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* sim/m32r/cmpz.cgs: Test CMPZ instruction.
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* sim/m32r/sll.cgs: Test SLL instruction.
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* sim/m32r/sll.cgs: Test SLL instruction.
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* sim/m32r/sll3.cgs: Test SLL3 instruction.
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* sim/m32r/sll3.cgs: Test SLL3 instruction.
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* sim/m32r/slli.cgs: Test SLLI instruction.
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* sim/m32r/slli.cgs: Test SLLI instruction.
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* sim/m32r/bcl24.cgs: Test long version of BCL instruction
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* sim/m32r/sra.cgs: Test SRA instruction.
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* sim/m32r/sra.cgs: Test SRA instruction.
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* sim/m32r/sra3.cgs: Test SRA3 instruction.
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* sim/m32r/sra3.cgs: Test SRA3 instruction.
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* sim/m32r/srai.cgs: Test SRAI instruction.
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* sim/m32r/srai.cgs: Test SRAI instruction.
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@ -30,7 +35,16 @@ Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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* sim/m32r/srli.cgs: Test SRLI instruction.
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* sim/m32r/srli.cgs: Test SRLI instruction.
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* sim/m32r/xor3.cgs: Test XOR3 instruction.
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* sim/m32r/xor3.cgs: Test XOR3 instruction.
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* sim/m32r/xor.cgs: Test XOR instruction.
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* sim/m32r/xor.cgs: Test XOR instruction.
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start-sanitize-m342rx
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* sim/m32r/jnc.cgs: Test JNC instruction.
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* sim/m32r/jc.cgs: Test JC instruction.
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* sim/m32r/cmpz.cgs: Test CMPZ instruction.
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* sim/m32r/bcl24.cgs: Test long version of BCL instruction
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* sim/m32r/bcl8.cgs: Test short BCL instruction.
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* sim/m32r/bncl24.cgs: Test long BNCL instruction.
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* sim/m32r/bncl8.cgs: Test short BNCL instruction.
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* sim/m32r/divh.cgs: Test DIVH instruction.
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end-sanitize-m342rx
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Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
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Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
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* config/default.exp: New file.
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* config/default.exp: New file.
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# m32r testcase for bl $disp24
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# mach(): m32r m32rx
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.include "testutils.inc"
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start
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.global bl24
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bl24:
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bl.l test0pass
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test1fail:
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fail
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test0pass:
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seth r4, high (test1fail)
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or3 r4, r4, low (test1fail)
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bne r4, r14, test1fail
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pass
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# m32r testcase for bl $disp8
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# mach(): m32r m32rx
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.include "testutils.inc"
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start
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.global bl8
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bl8:
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bl.s test0pass
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test1fail:
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fail
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test0pass:
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seth r4, high (test1fail)
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or3 r4, r4, low (test1fail)
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bne r4, r14, test1fail
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pass
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# m32r testcase for jl $sr
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# mach(): m32r m32rx
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.include "testutils.inc"
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start
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.global jl
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jl:
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seth r4, high (ok)
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or3 r4, r4, low (ok)
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jl r4
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not_ok:
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fail
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ok:
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seth r4, high (not_ok)
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or3 r4, r4, low (not_ok)
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bne r4, r14, not_ok
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pass
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# m32r testcase for jmp $sr
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# mach(): m32r m32rx
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.include "testutils.inc"
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start
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.global jmp
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jmp:
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seth r4, high (ok)
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or3 r4, r4, low (ok)
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jmp r4
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fail
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ok:
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pass
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