gas/
* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. gas/testsuite/ * gas/aarch64/alias.s: Add tests. * gas/aarch64/alias.d: Update. * gas/aarch64/no-aliases.d: Update. * gas/aarch64/diagnostic.s: Add tests. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/illegal.s: Add tests. * gas/aarch64/illegal.l: Update. include/opcode/ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. opcodes/ * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'. (convert_from_csel): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1. (aarch64_print_operand): Handle AARCH64_OPND_COND1. * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of COND for cinc, cset, cinv, csetm and cneg. (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1. * aarch64-asm-2.c: Re-generated. * aarch64-dis-2.c: Ditto. * aarch64-opc-2.c: Ditto.
This commit is contained in:
Yufeng Zhang
parent
4e50d5f863
commit
68a6428382
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@ -1,3 +1,7 @@
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2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1.
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2013-11-05 Will Newton <will.newton@linaro.org>
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PR gas/16103
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@ -4969,6 +4969,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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break;
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case AARCH64_OPND_COND:
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case AARCH64_OPND_COND1:
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info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
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str += 2;
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if (info->cond == NULL)
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@ -4976,6 +4977,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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set_syntax_error (_("invalid condition"));
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goto failure;
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}
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else if (operands[i] == AARCH64_OPND_COND1
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&& (info->cond->value & 0xe) == 0xe)
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{
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/* Not allow AL or NV. */
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set_default_error ();
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goto failure;
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}
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break;
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case AARCH64_OPND_ADDR_ADRP:
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@ -1,3 +1,13 @@
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2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/alias.s: Add tests.
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* gas/aarch64/alias.d: Update.
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* gas/aarch64/no-aliases.d: Update.
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* gas/aarch64/diagnostic.s: Add tests.
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* gas/aarch64/diagnostic.l: Update.
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* gas/aarch64/illegal.s: Add tests.
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* gas/aarch64/illegal.l: Update.
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2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/diagnostic.s: Add tests of ldp/stp.
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@ -96,3 +96,13 @@ Disassembly of section \.text:
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160: 2f20a448 uxtl v8.2d, v2.2s
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164: 6f20a448 uxtl2 v8.2d, v2.4s
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168: 6f20a448 uxtl2 v8.2d, v2.4s
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16c: 1a81f420 csinc w0, w1, w1, nv
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170: 1a81e420 csinc w0, w1, w1, al
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174: 1a9ff7e0 csinc w0, wzr, wzr, nv
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178: 1a9fe7e0 csinc w0, wzr, wzr, al
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17c: 5a81f020 csinv w0, w1, w1, nv
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180: 5a81e020 csinv w0, w1, w1, al
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184: 5a9ff3e0 csinv w0, wzr, wzr, nv
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188: 5a9fe3e0 csinv w0, wzr, wzr, al
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18c: 5a81f420 csneg w0, w1, w1, nv
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190: 5a81e420 csneg w0, w1, w1, al
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@ -117,3 +117,14 @@
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asimdshll s
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asimdshll u
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csinc w0, w1, w1, nv
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csinc w0, w1, w1, al
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csinc w0, wzr, wzr, nv
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csinc w0, wzr, wzr, al
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csinv w0, w1, w1, nv
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csinv w0, w1, w1, al
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csinv w0, wzr, wzr, nv
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csinv w0, wzr, wzr, al
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csneg w0, w1, w1, nv
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csneg w0, w1, w1, al
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@ -93,3 +93,7 @@
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[^:]*:95: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2,#3\]'
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[^:]*:96: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2,#2\]!'
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[^:]*:97: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2\],#1'
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[^:]*:98: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,al'
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[^:]*:99: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
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[^:]*:100: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
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[^:]*:101: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
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@ -95,3 +95,7 @@
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stp w0, w1, [x2, #3]
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stp w0, w1, [x2, #2]!
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stp w0, w1, [x2], #1
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cinc w0, w1, al
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cinc w0, w1, nv
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cset w0, al
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cset w0, nv
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@ -552,4 +552,14 @@
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[^:]*:544: Error: .*`fmov s0,#0xC0280000C1400000'
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[^:]*:545: Error: .*`fmov d0,#0xC02f800000000000'
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[^:]*:550: Error: .*`ands w0,w24,#0xffeefffffffffffd'
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[^:]*:553: Error: .*
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[^:]*:554: Error: .*`cinc w0,w1,al'
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[^:]*:555: Error: .*`cinc w0,w1,nv'
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[^:]*:556: Error: .*`cset w0,al'
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[^:]*:557: Error: .*`cset w0,nv'
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[^:]*:558: Error: .*`cinv w0,w1,al'
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[^:]*:559: Error: .*`cinv w0,w1,nv'
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[^:]*:560: Error: .*`csetm w0,al'
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[^:]*:561: Error: .*`csetm w0,nv'
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[^:]*:562: Error: .*`cneg w0,w1,al'
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[^:]*:563: Error: .*`cneg w0,w1,nv'
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[^:]*:563: Error: .*
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@ -550,4 +550,14 @@
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ands w0, w24, #0xffeefffffffffffd
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one_label:
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cinc w0, w1, al
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cinc w0, w1, nv
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cset w0, al
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cset w0, nv
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cinv w0, w1, al
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cinv w0, w1, nv
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csetm w0, al
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csetm w0, nv
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cneg w0, w1, al
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cneg w0, w1, nv
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@ -97,3 +97,13 @@ Disassembly of section \.text:
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160: 2f20a448 ushll v8.2d, v2.2s, #0
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164: 6f20a448 ushll2 v8.2d, v2.4s, #0
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168: 6f20a448 ushll2 v8.2d, v2.4s, #0
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16c: 1a81f420 csinc w0, w1, w1, nv
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170: 1a81e420 csinc w0, w1, w1, al
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174: 1a9ff7e0 csinc w0, wzr, wzr, nv
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178: 1a9fe7e0 csinc w0, wzr, wzr, al
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17c: 5a81f020 csinv w0, w1, w1, nv
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180: 5a81e020 csinv w0, w1, w1, al
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184: 5a9ff3e0 csinv w0, wzr, wzr, nv
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188: 5a9fe3e0 csinv w0, wzr, wzr, al
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18c: 5a81f420 csneg w0, w1, w1, nv
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190: 5a81e420 csneg w0, w1, w1, al
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@ -1,3 +1,8 @@
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2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
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(enum aarch64_opnd): Add AARCH64_OPND_COND1.
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2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
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* mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
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@ -85,6 +85,7 @@ enum aarch64_operand_class
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AARCH64_OPND_CLASS_ADDRESS,
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AARCH64_OPND_CLASS_IMMEDIATE,
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AARCH64_OPND_CLASS_SYSTEM,
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AARCH64_OPND_CLASS_COND,
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};
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/* Operand code that helps both parsing and coding.
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@ -168,6 +169,7 @@ enum aarch64_opnd
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AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
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AARCH64_OPND_COND, /* Standard condition as the last operand. */
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AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
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AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
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AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
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@ -1,3 +1,17 @@
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2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
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(convert_from_csel): Likewise.
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* aarch64-opc.c (operand_general_constraint_met_p): Handle
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AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
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(aarch64_print_operand): Handle AARCH64_OPND_COND1.
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* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
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COND for cinc, cset, cinv, csetm and cneg.
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(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
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* aarch64-asm-2.c: Re-generated.
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* aarch64-dis-2.c: Ditto.
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* aarch64-opc-2.c: Ditto.
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2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-opc.c (set_syntax_error): New function.
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@ -303,10 +303,10 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 55:
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case 56:
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case 57:
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case 65:
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case 66:
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case 67:
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case 68:
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case 69:
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return aarch64_ins_imm (self, info, code, inst);
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case 37:
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case 38:
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@ -324,33 +324,34 @@ aarch64_insert_operand (const aarch64_operand *self,
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case 61:
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return aarch64_ins_fbits (self, info, code, inst);
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case 63:
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case 64:
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return aarch64_ins_cond (self, info, code, inst);
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case 69:
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case 75:
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return aarch64_ins_addr_simple (self, info, code, inst);
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case 70:
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return aarch64_ins_addr_regoff (self, info, code, inst);
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case 76:
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return aarch64_ins_addr_simple (self, info, code, inst);
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case 71:
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return aarch64_ins_addr_regoff (self, info, code, inst);
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case 72:
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case 73:
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return aarch64_ins_addr_simm (self, info, code, inst);
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case 74:
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return aarch64_ins_addr_simm (self, info, code, inst);
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case 75:
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return aarch64_ins_addr_uimm12 (self, info, code, inst);
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case 76:
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return aarch64_ins_simd_addr_post (self, info, code, inst);
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case 77:
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return aarch64_ins_sysreg (self, info, code, inst);
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return aarch64_ins_simd_addr_post (self, info, code, inst);
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case 78:
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return aarch64_ins_pstatefield (self, info, code, inst);
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return aarch64_ins_sysreg (self, info, code, inst);
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case 79:
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return aarch64_ins_pstatefield (self, info, code, inst);
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case 80:
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case 81:
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case 82:
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return aarch64_ins_sysins_op (self, info, code, inst);
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case 83:
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return aarch64_ins_sysins_op (self, info, code, inst);
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case 84:
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return aarch64_ins_barrier (self, info, code, inst);
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case 85:
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return aarch64_ins_barrier (self, info, code, inst);
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case 86:
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return aarch64_ins_prfop (self, info, code, inst);
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default: assert (0); abort ();
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}
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|
|
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@ -7690,11 +7690,11 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 55:
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case 56:
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case 57:
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case 64:
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case 65:
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case 66:
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case 67:
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case 68:
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case 69:
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return aarch64_ext_imm (self, info, code, inst);
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case 37:
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case 38:
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@ -7714,33 +7714,34 @@ aarch64_extract_operand (const aarch64_operand *self,
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case 61:
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return aarch64_ext_fbits (self, info, code, inst);
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case 63:
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case 64:
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return aarch64_ext_cond (self, info, code, inst);
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case 69:
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case 75:
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return aarch64_ext_addr_simple (self, info, code, inst);
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case 70:
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return aarch64_ext_addr_regoff (self, info, code, inst);
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case 76:
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return aarch64_ext_addr_simple (self, info, code, inst);
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case 71:
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return aarch64_ext_addr_regoff (self, info, code, inst);
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case 72:
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case 73:
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return aarch64_ext_addr_simm (self, info, code, inst);
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case 74:
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return aarch64_ext_addr_simm (self, info, code, inst);
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case 75:
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return aarch64_ext_addr_uimm12 (self, info, code, inst);
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case 76:
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return aarch64_ext_simd_addr_post (self, info, code, inst);
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case 77:
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return aarch64_ext_sysreg (self, info, code, inst);
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return aarch64_ext_simd_addr_post (self, info, code, inst);
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case 78:
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return aarch64_ext_pstatefield (self, info, code, inst);
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return aarch64_ext_sysreg (self, info, code, inst);
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case 79:
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return aarch64_ext_pstatefield (self, info, code, inst);
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case 80:
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case 81:
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case 82:
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return aarch64_ext_sysins_op (self, info, code, inst);
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case 83:
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return aarch64_ext_sysins_op (self, info, code, inst);
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case 84:
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return aarch64_ext_barrier (self, info, code, inst);
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case 85:
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return aarch64_ext_barrier (self, info, code, inst);
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case 86:
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return aarch64_ext_prfop (self, info, code, inst);
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default: assert (0); abort ();
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}
|
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|
|
|
|||
|
|
@ -1601,12 +1601,14 @@ convert_ubfm_to_lsl (aarch64_inst *inst)
|
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|
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/* CINC <Wd>, <Wn>, <cond>
|
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is equivalent to:
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CSINC <Wd>, <Wn>, <Wn>, invert(<cond>). */
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CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
|
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where <cond> is not AL or NV. */
|
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|
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static int
|
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convert_from_csel (aarch64_inst *inst)
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{
|
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if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
|
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if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
|
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&& (inst->operands[3].cond->value & 0xe) != 0xe)
|
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{
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copy_operand_info (inst, 2, 3);
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inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
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|
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@ -1618,13 +1620,15 @@ convert_from_csel (aarch64_inst *inst)
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|
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/* CSET <Wd>, <cond>
|
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is equivalent to:
|
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CSINC <Wd>, WZR, WZR, invert(<cond>). */
|
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CSINC <Wd>, WZR, WZR, invert(<cond>)
|
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where <cond> is not AL or NV. */
|
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|
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static int
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convert_csinc_to_cset (aarch64_inst *inst)
|
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{
|
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if (inst->operands[1].reg.regno == 0x1f
|
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&& inst->operands[2].reg.regno == 0x1f)
|
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&& inst->operands[2].reg.regno == 0x1f
|
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&& (inst->operands[3].cond->value & 0xe) != 0xe)
|
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{
|
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copy_operand_info (inst, 1, 3);
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inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
|
||||
|
|
|
|||
|
|
@ -87,7 +87,8 @@ const struct aarch64_operand aarch64_operands[] =
|
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{AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
|
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{AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
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||||
{AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
|
||||
{AARCH64_OPND_CLASS_NIL, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
|
||||
{AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
|
||||
{AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},
|
||||
|
|
|
|||
|
|
@ -1286,6 +1286,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_CLASS_COND:
|
||||
if (type == AARCH64_OPND_COND1
|
||||
&& (opnds[idx].cond->value & 0xe) == 0xe)
|
||||
{
|
||||
/* Not allow AL or NV. */
|
||||
set_syntax_error (mismatch_detail, idx, NULL);
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_CLASS_ADDRESS:
|
||||
/* Check writeback. */
|
||||
switch (opcode->iclass)
|
||||
|
|
@ -2524,6 +2533,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
break;
|
||||
|
||||
case AARCH64_OPND_COND:
|
||||
case AARCH64_OPND_COND1:
|
||||
snprintf (buf, size, "%s", opnd->cond->names[0]);
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -1782,13 +1782,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
/* Conditional select. */
|
||||
{"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
|
||||
{"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
|
||||
{"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
|
||||
{"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
|
||||
{"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
|
||||
{"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
|
||||
{"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
|
||||
{"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
|
||||
{"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
|
||||
{"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
|
||||
{"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
|
||||
{"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
|
||||
{"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
|
||||
{"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
|
||||
/* Crypto AES. */
|
||||
{"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
|
||||
{"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
|
||||
|
|
@ -2235,7 +2235,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
|
||||
"the number of bits after the binary point in the fixed-point value")\
|
||||
X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \
|
||||
Y(NIL, cond, "COND", 0, F(), "a condition") \
|
||||
Y(COND, cond, "COND", 0, F(), "a condition") \
|
||||
Y(COND, cond, "COND1", 0, F(), \
|
||||
"one of the standard conditions, excluding AL and NV.") \
|
||||
X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
|
||||
"21-bit PC-relative address of a 4KB page") \
|
||||
Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
|
||||
|
|
|
|||
Loading…
Reference in New Issue