[BFD, AArch64] Improve bti/pac plts.
This patch aims to improve the definitions of BTI and PAC based PLTs.
The following changes are made:
* PLT0 does not need PAC instructions since the PLTGOT[2] (and PLTGOT[1])
are readonly so they cannot be corrupted at runtime. Thus both PAC plt0
and BTI+PAC plt0 are removed and we can use basic plt0 and BTI plt0
instead, respectively.
* We can remove the extra padding nops when we add the new bti instructions.
BTI plt0 and BTI TLSDESC plt are updated.
* For better performance PLTn could be padded to 24bytes. Both BTI pltn and
PAC pltn are updated.
*** bfd/ChangeLog ***
2019-04-25 Sudakshina Das <sudi.das@arm.com>
* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove.
(PLT_BTI_TLSDESC_ENTRY_SIZE): Remove.
(PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove.
(PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update.
(elfNN_aarch64_small_plt0_pac_entry): Remove.
(elfNN_aarch64_small_plt0_bti_pac_entry): Remove.
(elfNN_aarch64_small_plt0_bti_entry): Update.
(elfNN_aarch64_small_plt_bti_entry): Update.
(elfNN_aarch64_small_plt_pac_entry): Update.
(elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update.
(setup_plt_values): Setup new entries.
(elfNN_aarch64_finish_dynamic_sections): Remove size change.
(elfNN_aarch64_plt_sym_val): Likewise.
*** ld/ChangeLog ***
2019-04-25 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-aarch64/bti-pac-plt-1.d: Update.
* testsuite/ld-aarch64/bti-pac-plt-2.d: Update.
* testsuite/ld-aarch64/bti-plt-1.d: Update.
* testsuite/ld-aarch64/bti-plt-3.d: Update.
* testsuite/ld-aarch64/bti-plt-5.d: Update.
* testsuite/ld-aarch64/pac-plt-1.d: Update.
* testsuite/ld-aarch64/pac-plt-2.d: Update.
This commit is contained in:
Sudakshina Das
parent
cd0923370b
commit
68bb0359ee
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@ -1,3 +1,19 @@
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2019-04-25 Sudakshina Das <sudi.das@arm.com>
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* elfnn-aarch64.c (PLT_BTI_ENTRY_SIZE): Remove.
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(PLT_BTI_TLSDESC_ENTRY_SIZE): Remove.
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(PLT_PAC_ENTRY_SIZE, PLT_BTI_PAC_ENTRY_SIZE): Remove.
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(PLT_BTI_SMALL_ENTRY_SIZE, PLT_PAC_SMALL_ENTRY_SIZE): Update.
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(elfNN_aarch64_small_plt0_pac_entry): Remove.
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(elfNN_aarch64_small_plt0_bti_pac_entry): Remove.
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(elfNN_aarch64_small_plt0_bti_entry): Update.
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(elfNN_aarch64_small_plt_bti_entry): Update.
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(elfNN_aarch64_small_plt_pac_entry): Update.
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(elfNN_aarch64_tlsdesc_small_plt_bti_entry): Update.
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(setup_plt_values): Setup new entries.
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(elfNN_aarch64_finish_dynamic_sections): Remove size change.
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(elfNN_aarch64_plt_sym_val): Likewise.
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2019-04-22 Jim Wilson <jimw@sifive.com>
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* elfnn-riscv.c (PRSTATUS_SIZE) [ARCH_SIZE==32]: Change from 0 to 204.
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@ -268,14 +268,10 @@
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#define PLT_SMALL_ENTRY_SIZE (16)
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#define PLT_TLSDESC_ENTRY_SIZE (32)
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/* PLT sizes with BTI insn. */
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#define PLT_BTI_ENTRY_SIZE (36)
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#define PLT_BTI_SMALL_ENTRY_SIZE (20)
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#define PLT_BTI_TLSDESC_ENTRY_SIZE (36)
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#define PLT_BTI_SMALL_ENTRY_SIZE (24)
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/* PLT sizes with PAC insn. */
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#define PLT_PAC_ENTRY_SIZE (36)
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#define PLT_PAC_SMALL_ENTRY_SIZE (20)
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#define PLT_PAC_SMALL_ENTRY_SIZE (24)
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/* PLT sizes with BTI and PAC insn. */
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#define PLT_BTI_PAC_ENTRY_SIZE (40)
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#define PLT_BTI_PAC_SMALL_ENTRY_SIZE (24)
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/* Encoding of the nop instruction. */
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@ -307,7 +303,7 @@ static const bfd_byte elfNN_aarch64_small_plt0_entry[PLT_ENTRY_SIZE] =
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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};
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static const bfd_byte elfNN_aarch64_small_plt0_bti_entry[PLT_BTI_ENTRY_SIZE] =
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static const bfd_byte elfNN_aarch64_small_plt0_bti_entry[PLT_ENTRY_SIZE] =
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{
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0x5f, 0x24, 0x03, 0xd5, /* bti c. */
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0xf0, 0x7b, 0xbf, 0xa9, /* stp x16, x30, [sp, #-16]! */
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@ -322,45 +318,6 @@ static const bfd_byte elfNN_aarch64_small_plt0_bti_entry[PLT_BTI_ENTRY_SIZE] =
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0x20, 0x02, 0x1f, 0xd6, /* br x17 */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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};
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static const bfd_byte elfNN_aarch64_small_plt0_pac_entry[PLT_PAC_ENTRY_SIZE] =
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{
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0xf0, 0x7b, 0xbf, 0xa9, /* stp x16, x30, [sp, #-16]! */
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0x10, 0x00, 0x00, 0x90, /* adrp x16, (GOT+16) */
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#if ARCH_SIZE == 64
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0x11, 0x0A, 0x40, 0xf9, /* ldr x17, [x16, #PLT_GOT+0x10] */
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0x10, 0x42, 0x00, 0x91, /* add x16, x16,#PLT_GOT+0x10 */
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#else
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0x11, 0x0A, 0x40, 0xb9, /* ldr w17, [x16, #PLT_GOT+0x8] */
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0x10, 0x22, 0x00, 0x11, /* add w16, w16,#PLT_GOT+0x8 */
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#endif
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0x9f, 0x21, 0x03, 0xd5, /* autia1716 */
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0x20, 0x02, 0x1f, 0xd6, /* br x17 */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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};
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static const bfd_byte
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elfNN_aarch64_small_plt0_bti_pac_entry[PLT_BTI_PAC_ENTRY_SIZE] =
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{
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0x5f, 0x24, 0x03, 0xd5, /* bti c. */
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0xf0, 0x7b, 0xbf, 0xa9, /* stp x16, x30, [sp, #-16]! */
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0x10, 0x00, 0x00, 0x90, /* adrp x16, (GOT+16) */
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#if ARCH_SIZE == 64
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0x11, 0x0A, 0x40, 0xf9, /* ldr x17, [x16, #PLT_GOT+0x10] */
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0x10, 0x42, 0x00, 0x91, /* add x16, x16,#PLT_GOT+0x10 */
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#else
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0x11, 0x0A, 0x40, 0xb9, /* ldr w17, [x16, #PLT_GOT+0x8] */
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0x10, 0x22, 0x00, 0x11, /* add w16, w16,#PLT_GOT+0x8 */
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#endif
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0x9f, 0x21, 0x03, 0xd5, /* autia1716 */
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0x20, 0x02, 0x1f, 0xd6, /* br x17 */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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};
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/* Per function entry in a procedure linkage table looks like this
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@ -392,6 +349,7 @@ elfNN_aarch64_small_plt_bti_entry[PLT_BTI_SMALL_ENTRY_SIZE] =
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0x10, 0x02, 0x00, 0x11, /* add w16, w16, :lo12:PLTGOT + n * 4 */
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#endif
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0x20, 0x02, 0x1f, 0xd6, /* br x17. */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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};
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static const bfd_byte
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@ -407,6 +365,7 @@ elfNN_aarch64_small_plt_pac_entry[PLT_PAC_SMALL_ENTRY_SIZE] =
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#endif
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0x9f, 0x21, 0x03, 0xd5, /* autia1716 */
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0x20, 0x02, 0x1f, 0xd6, /* br x17. */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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};
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static const bfd_byte
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@ -444,7 +403,7 @@ elfNN_aarch64_tlsdesc_small_plt_entry[PLT_TLSDESC_ENTRY_SIZE] =
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};
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static const bfd_byte
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elfNN_aarch64_tlsdesc_small_plt_bti_entry[PLT_BTI_TLSDESC_ENTRY_SIZE] =
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elfNN_aarch64_tlsdesc_small_plt_bti_entry[PLT_TLSDESC_ENTRY_SIZE] =
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{
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0x5f, 0x24, 0x03, 0xd5, /* bti c. */
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0xe2, 0x0f, 0xbf, 0xa9, /* stp x2, x3, [sp, #-16]! */
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@ -459,7 +418,6 @@ elfNN_aarch64_tlsdesc_small_plt_bti_entry[PLT_BTI_TLSDESC_ENTRY_SIZE] =
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#endif
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0x40, 0x00, 0x1f, 0xd6, /* br x2 */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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0x1f, 0x20, 0x03, 0xd5, /* nop */
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};
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#define elf_info_to_howto elfNN_aarch64_info_to_howto
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@ -4758,9 +4716,7 @@ setup_plt_values (struct bfd_link_info *link_info,
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if (plt_type == PLT_BTI_PAC)
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{
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globals->plt_header_size = PLT_BTI_PAC_ENTRY_SIZE;
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globals->plt0_entry = elfNN_aarch64_small_plt0_bti_pac_entry;
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globals->tlsdesc_plt_entry_size = PLT_BTI_TLSDESC_ENTRY_SIZE;
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globals->plt0_entry = elfNN_aarch64_small_plt0_bti_entry;
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/* Only in ET_EXEC we need PLTn with BTI. */
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if (bfd_link_pde (link_info))
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@ -4776,9 +4732,7 @@ setup_plt_values (struct bfd_link_info *link_info,
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}
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else if (plt_type == PLT_BTI)
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{
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globals->plt_header_size = PLT_BTI_ENTRY_SIZE;
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globals->plt0_entry = elfNN_aarch64_small_plt0_bti_entry;
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globals->tlsdesc_plt_entry_size = PLT_BTI_TLSDESC_ENTRY_SIZE;
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/* Only in ET_EXEC we need PLTn with BTI. */
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if (bfd_link_pde (link_info))
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@ -4789,9 +4743,6 @@ setup_plt_values (struct bfd_link_info *link_info,
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}
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else if (plt_type == PLT_PAC)
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{
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globals->plt_header_size = PLT_PAC_ENTRY_SIZE;
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globals->plt0_entry = elfNN_aarch64_small_plt0_pac_entry;
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globals->tlsdesc_plt_entry_size = PLT_TLSDESC_ENTRY_SIZE;
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globals->plt_entry_size = PLT_PAC_SMALL_ENTRY_SIZE;
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globals->plt_entry = elfNN_aarch64_small_plt_pac_entry;
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}
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@ -9720,7 +9671,6 @@ elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
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if (type == PLT_BTI || type == PLT_BTI_PAC)
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{
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entry = elfNN_aarch64_tlsdesc_small_plt_bti_entry;
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htab->tlsdesc_plt_entry_size = PLT_BTI_TLSDESC_ENTRY_SIZE;
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}
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memcpy (htab->root.splt->contents + htab->tlsdesc_plt,
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@ -9896,7 +9846,6 @@ elfNN_aarch64_plt_sym_val (bfd_vma i, const asection *plt,
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if (elf_aarch64_tdata (plt->owner)->plt_type == PLT_BTI_PAC)
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{
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plt0_size = PLT_BTI_PAC_ENTRY_SIZE;
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if (elf_elfheader (plt->owner)->e_type == ET_EXEC)
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pltn_size = PLT_BTI_PAC_SMALL_ENTRY_SIZE;
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else
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@ -9904,13 +9853,11 @@ elfNN_aarch64_plt_sym_val (bfd_vma i, const asection *plt,
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}
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else if (elf_aarch64_tdata (plt->owner)->plt_type == PLT_BTI)
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{
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plt0_size = PLT_BTI_ENTRY_SIZE;
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if (elf_elfheader (plt->owner)->e_type == ET_EXEC)
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pltn_size = PLT_BTI_SMALL_ENTRY_SIZE;
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}
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else if (elf_aarch64_tdata (plt->owner)->plt_type == PLT_PAC)
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{
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plt0_size = PLT_PAC_ENTRY_SIZE;
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pltn_size = PLT_PAC_SMALL_ENTRY_SIZE;
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}
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10
ld/ChangeLog
10
ld/ChangeLog
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@ -1,3 +1,13 @@
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2019-04-25 Sudakshina Das <sudi.das@arm.com>
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* testsuite/ld-aarch64/bti-pac-plt-1.d: Update.
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* testsuite/ld-aarch64/bti-pac-plt-2.d: Update.
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* testsuite/ld-aarch64/bti-plt-1.d: Update.
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* testsuite/ld-aarch64/bti-plt-3.d: Update.
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* testsuite/ld-aarch64/bti-plt-5.d: Update.
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* testsuite/ld-aarch64/pac-plt-1.d: Update.
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* testsuite/ld-aarch64/pac-plt-2.d: Update.
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2019-04-24 Sandra Loosemore <sandra@codesourcery.com>
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* testsuite/config/default.exp: Use [check_compiler_available]
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@ -13,11 +13,9 @@ Disassembly of section \.plt:
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.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
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.*: f9400e11 ldr x17, \[x16, #24\]
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.*: 91006210 add x16, x16, #0x18
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.*: d503219f autia1716
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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.*: d503201f nop
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[0-9a-f]+ <.*>:
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.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
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@ -25,6 +23,7 @@ Disassembly of section \.plt:
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.*: 91008210 add x16, x16, #0x20
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.*: d503219f autia1716
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.*: d61f0220 br x17
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.*: d503201f nop
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[0-9a-f]+ <.*>:
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.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
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@ -32,3 +31,4 @@ Disassembly of section \.plt:
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.*: 9100a210 add x16, x16, #0x28
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.*: d503219f autia1716
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.*: d61f0220 br x17
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.*: d503201f nop
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@ -13,11 +13,9 @@ Disassembly of section \.plt:
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.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
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.*: f9400e11 ldr x17, \[x16, #24\]
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.*: 91006210 add x16, x16, #0x18
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.*: d503219f autia1716
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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.*: d503201f nop
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[0-9]+ <.*>:
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.*: d503245f bti c
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@ -17,7 +17,6 @@ Disassembly of section \.plt:
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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.*: d503201f nop
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[0-9]+ <.*>:
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.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
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@ -17,7 +17,6 @@ Disassembly of section \.plt:
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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.*: d503201f nop
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[0-9]+ <.*>:
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.*: d503245f bti c
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@ -25,6 +24,7 @@ Disassembly of section \.plt:
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.*: f9401211 ldr x17, \[x16, #32\]
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.*: 91008210 add x16, x16, #0x20
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.*: d61f0220 br x17
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.*: d503201f nop
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[0-9]+ <.*>:
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.*: d503245f bti c
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@ -32,3 +32,4 @@ Disassembly of section \.plt:
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.*: f9401611 ldr x17, \[x16, #40\]
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.*: 9100a210 add x16, x16, #0x28
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.*: d61f0220 br x17
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.*: d503201f nop
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@ -12,17 +12,17 @@ Disassembly of section \.plt:
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[0-9a-f]+ <.*>:
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.*: d503245f bti c
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.*: a9bf7bf0 stp x16, x30, \[sp, #-16\]!
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.*: 90000090 adrp x16, 410000 <_start\+0xfd28>
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.*: 90000090 adrp x16, 410000 <.*>
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.*: f9421611 ldr x17, \[x16, #1064\]
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.*: 9110a210 add x16, x16, #0x428
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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.*: d503201f nop
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[0-9a-f]+ <.*>:
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.*: d503245f bti c
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.*: 90000090 adrp x16, 410000 <_start\+0xfd28>
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.*: 90000090 adrp x16, 410000 <.*>
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.*: f9421a11 ldr x17, \[x16, #1072\]
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.*: 9110c210 add x16, x16, #0x430
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.*: d61f0220 br x17
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.*: d503201f nop
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@ -12,7 +12,6 @@ Disassembly of section \.plt:
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.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
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.*: f9400e11 ldr x17, \[x16, #24\]
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.*: 91006210 add x16, x16, #0x18
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.*: d503219f autia1716
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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@ -24,6 +23,7 @@ Disassembly of section \.plt:
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.*: 91008210 add x16, x16, #0x20
|
||||
.*: d503219f autia1716
|
||||
.*: d61f0220 br x17
|
||||
.*: d503201f nop
|
||||
|
||||
[0-9]+ <.*>:
|
||||
.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
|
||||
|
|
@ -31,3 +31,4 @@ Disassembly of section \.plt:
|
|||
.*: 9100a210 add x16, x16, #0x28
|
||||
.*: d503219f autia1716
|
||||
.*: d61f0220 br x17
|
||||
.*: d503201f nop
|
||||
|
|
|
|||
|
|
@ -4,21 +4,21 @@
|
|||
#...
|
||||
Disassembly of section .plt:
|
||||
|
||||
0000000000018000 \<.plt\>:
|
||||
.* \<.plt\>:
|
||||
.*: a9bf7bf0 stp x16, x30, \[sp, #-16\]!
|
||||
.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
|
||||
.*: f9401a11 ldr x17, \[x16, #48\]
|
||||
.*: 9100c210 add x16, x16, #0x30
|
||||
.*: d503219f autia1716
|
||||
.*: d61f0220 br x17
|
||||
.*: d503201f nop
|
||||
.*: d503201f nop
|
||||
.*: d503201f nop
|
||||
|
||||
|
||||
0000000000018024 \<__tls_get_addr@plt\>:
|
||||
.* \<__tls_get_addr@plt\>:
|
||||
.*: 90000090 adrp x16, 28000 <_GLOBAL_OFFSET_TABLE_>
|
||||
.*: f9401e11 ldr x17, \[x16, #56\]
|
||||
.*: 9100e210 add x16, x16, #0x38
|
||||
.*: d503219f autia1716
|
||||
.*: d61f0220 br x17
|
||||
.*: d503201f nop
|
||||
|
|
|
|||
Loading…
Reference in New Issue