* tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd",
"vsub", "vst", "xnor", and "xor" instructions.
(V_a1): Renamed from V_a, msb of accumulator reg number.
(V_a0): Add macro, lsb of accumulator reg number.
This commit is contained in:
Fred Fish
parent
102b9af5f9
commit
68c7761c42
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@ -1,4 +1,11 @@
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start-sanitize-tic80
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Sat Jan 18 15:15:05 1997 Fred Fish <fnf@cygnus.com>
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* tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd",
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"vsub", "vst", "xnor", and "xor" instructions.
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(V_a1): Renamed from V_a, msb of accumulator reg number.
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(V_a0): Add macro, lsb of accumulator reg number.
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Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com>
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* tic80-dis.c (print_insn_tic80): Broke excessively long
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@ -240,7 +240,10 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
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#define P1(x) ((x) << 5)
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/* The 'a' field at bit 16 in vector instructions */
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#define V_a(x) ((x) << 16)
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#define V_a1(x) ((x) << 16)
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/* The 'a' field at bit 11 in vector instructions */
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#define V_a0(x) ((x) << 11)
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/* The 'm' field at bit 10 in vector instructions */
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#define V_m(x) ((x) << 10)
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@ -810,6 +813,13 @@ const struct tic80_opcode tic80_opcodes[] = {
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{"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
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{"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} },
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/* Write Control Register
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Is a special form of the "swcr" instruction so comes before it in the table. */
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{"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} },
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{"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} },
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{"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} },
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/* Swap Control Register */
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{"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} },
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@ -824,30 +834,83 @@ const struct tic80_opcode tic80_opcodes[] = {
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/* Vector Floating-Point Add */
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{"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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{"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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{"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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{"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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/* Vector Floating-Point Multiply and Add to Accumulator */
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/* Vector Floating-Point Multiply and Add to Accumulator
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FIXME! This is not yet implemented. From the documentation there appears to be no way to
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tell the difference between the opcodes for instructions that have register destinations
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and instructions that have accumulator destinations. Further investigation is necessary.
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Since this isn't critical to getting a TIC80 toolchain up and running, it is defered
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until later. */
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/* Vector Load Data Into Register - Note that this comes after all the other
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vector instructions so that the disassembler will always print the load instruction
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second for vector instructions that have two instructions in the same opcode. */
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/* Vector Floating-Point Multiply
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Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */
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{"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
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{"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
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{"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
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{"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
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{"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
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/* Vector Floating-Point Multiply and Subtract from Accumulator
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FIXME: See note above for vmac instruction */
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/* Vector Floating-Point Subtract Accumulator From Source
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FIXME: See note above for vmac instruction */
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/* Vector Round With Floating-Point Input
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FIXME: See note above for vmac instruction */
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/* Vector Round with Integer Input */
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{"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
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{"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
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{"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
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{"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}},
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{"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}},
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{"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}},
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{"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}},
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{"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}},
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/* Vector Floating-Point Subtract */
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{"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} },
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{"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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{"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} },
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/* Vector Load Data Into Register - Note that the vector load/store instructions come after the other
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vector instructions so that the disassembler will always print the load/store instruction second for
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vector instructions that have two instructions in the same opcode. */
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{"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
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{"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
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{"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
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{"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
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{"xnor", OP_LI(0x333), MASK_LI, 0, FIXME},
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{"xnor", OP_REG(0x332), MASK_REG, 0, FIXME},
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{"xnor", OP_SI(0x19), MASK_SI, 0, FIXME},
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{"xor", OP_LI(0x32D), MASK_LI, 0, FIXME},
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{"xor", OP_REG(0x32C), MASK_REG, 0, FIXME},
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{"xor", OP_SI(0x16), MASK_SI, 0, FIXME},
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/* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other
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vector instructions so that the disassembler will always print the load/store instruction second for
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vector instructions that have two instructions in the same opcode. */
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{"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
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{"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
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{"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
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{"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
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{"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
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{"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} },
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{"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} },
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{"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} },
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};
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