AArch64: Update encodings for stg, st2g, stzg and st2zg.
This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch updates the st*g instructions to use a previously reserved field for a new register operand. Thus the new versions of the instructions are as follows: - STG Xt, [<Xn|SP>, #<simm>] - STG Xt, [<Xn|SP>, #<simm>]! - STG Xt, [<Xn|SP>], #<simm> - STZG Xt, [<Xn|SP>, #<simm>] - STZG Xt, [<Xn|SP>, #<simm>]! - STZG Xt, [<Xn|SP>], #<simm> - ST2G Xt, [<Xn|SP>, #<simm>] - ST2G Xt, [<Xn|SP>, #<simm>]! - ST2G Xt, [<Xn|SP>], #<simm> - STZ2G Xt, [<Xn|SP>, #<simm>] - STZ2G Xt, [<Xn|SP>, #<simm>]! - STZ2G Xt, [<Xn|SP>], #<simm> Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (warn_unpredictable_ldst): Exempt stg, st2g, stzg and stz2g from Xt == Xn with writeback warning. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for stg, stzg, st2g and stz2g. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-tbl.h (QL_LDST_AT): Update macro. (aarch64_opcode): Change encoding for stg, stzg st2g and st2zg. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
This commit is contained in:
Sudi Das
Tamar Christina
parent
20a4ca5524
commit
69105ce4c4
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@ -6772,6 +6772,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
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== AARCH64_OPND_CLASS_INT_REG)
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&& opnds[0].reg.regno == opnds[1].addr.base_regno
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&& opnds[1].addr.base_regno != REG_SP
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/* Exempt STG/STZG/ST2G/STZ2G. */
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&& !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13)
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&& opnds[1].addr.writeback)
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as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
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break;
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@ -55,50 +55,66 @@ Disassembly of section \.text:
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.*: badb037f cmpp x27, x27
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.*: bac003ff cmpp sp, x0
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.*: badf001f cmpp x0, sp
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.*: d920081f stg \[x0\]
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.*: d9200b7f stg \[x27\]
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.*: d93fb81f stg \[x0, #-80\]
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.*: d9200c1f stg \[x0, #0\]!
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.*: d920ac1f stg \[x0, #160\]!
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.*: d920041f stg \[x0\], #0
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.*: d93a641f stg \[x0\], #-1440
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.*: d92ffbff stg \[sp, #4080\]
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.*: d9300bff stg \[sp, #-4096\]
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.*: d92fffff stg \[sp, #4080\]!
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.*: d93007ff stg \[sp\], #-4096
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.*: d960081f stzg \[x0\]
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.*: d9600b7f stzg \[x27\]
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.*: d97fb81f stzg \[x0, #-80\]
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.*: d9600c1f stzg \[x0, #0\]!
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.*: d960ac1f stzg \[x0, #160\]!
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.*: d960041f stzg \[x0\], #0
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.*: d97a641f stzg \[x0\], #-1440
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.*: d96ffbff stzg \[sp, #4080\]
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.*: d9700bff stzg \[sp, #-4096\]
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.*: d96fffff stzg \[sp, #4080\]!
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.*: d97007ff stzg \[sp\], #-4096
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.*: d9a0081f st2g \[x0\]
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.*: d9a00b7f st2g \[x27\]
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.*: d9bfb81f st2g \[x0, #-80\]
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.*: d9a00c1f st2g \[x0, #0\]!
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.*: d9a0ac1f st2g \[x0, #160\]!
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.*: d9a0041f st2g \[x0\], #0
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.*: d9ba641f st2g \[x0\], #-1440
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.*: d9affbff st2g \[sp, #4080\]
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.*: d9b00bff st2g \[sp, #-4096\]
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.*: d9afffff st2g \[sp, #4080\]!
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.*: d9b007ff st2g \[sp\], #-4096
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.*: d9e0081f stz2g \[x0\]
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.*: d9e00b7f stz2g \[x27\]
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.*: d9ffb81f stz2g \[x0, #-80\]
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.*: d9e00c1f stz2g \[x0, #0\]!
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.*: d9e0ac1f stz2g \[x0, #160\]!
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.*: d9e0041f stz2g \[x0\], #0
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.*: d9fa641f stz2g \[x0\], #-1440
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.*: d9effbff stz2g \[sp, #4080\]
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.*: d9f00bff stz2g \[sp, #-4096\]
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.*: d9efffff stz2g \[sp, #4080\]!
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.*: d9f007ff stz2g \[sp\], #-4096
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.*: d9200800 stg x0, \[x0\]
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.*: d9200b60 stg x0, \[x27\]
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.*: d920081f stg xzr, \[x0\]
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.*: d93fb81b stg x27, \[x0, #-80\]
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.*: d9200c00 stg x0, \[x0, #0\]!
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.*: d9200c1f stg xzr, \[x0, #0\]!
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.*: d920ac1b stg x27, \[x0, #160\]!
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.*: d9200400 stg x0, \[x0\], #0
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.*: d920041f stg xzr, \[x0\], #0
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.*: d93a641b stg x27, \[x0\], #-1440
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.*: d92ffbe0 stg x0, \[sp, #4080\]
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.*: d92ffbff stg xzr, \[sp, #4080\]
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.*: d9300bfb stg x27, \[sp, #-4096\]
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.*: d92fffe0 stg x0, \[sp, #4080\]!
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.*: d93007ff stg xzr, \[sp\], #-4096
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.*: d9600800 stzg x0, \[x0\]
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.*: d9600b60 stzg x0, \[x27\]
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.*: d960081f stzg xzr, \[x0\]
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.*: d97fb81b stzg x27, \[x0, #-80\]
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.*: d9600c00 stzg x0, \[x0, #0\]!
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.*: d9600c1f stzg xzr, \[x0, #0\]!
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.*: d960ac1b stzg x27, \[x0, #160\]!
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.*: d9600400 stzg x0, \[x0\], #0
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.*: d960041f stzg xzr, \[x0\], #0
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.*: d97a641b stzg x27, \[x0\], #-1440
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.*: d96ffbe0 stzg x0, \[sp, #4080\]
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.*: d96ffbff stzg xzr, \[sp, #4080\]
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.*: d9700bfb stzg x27, \[sp, #-4096\]
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.*: d96fffe0 stzg x0, \[sp, #4080\]!
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.*: d97007ff stzg xzr, \[sp\], #-4096
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.*: d9a00800 st2g x0, \[x0\]
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.*: d9a00b60 st2g x0, \[x27\]
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.*: d9a0081f st2g xzr, \[x0\]
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.*: d9bfb81b st2g x27, \[x0, #-80\]
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.*: d9a00c00 st2g x0, \[x0, #0\]!
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.*: d9a00c1f st2g xzr, \[x0, #0\]!
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.*: d9a0ac1b st2g x27, \[x0, #160\]!
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.*: d9a00400 st2g x0, \[x0\], #0
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.*: d9a0041f st2g xzr, \[x0\], #0
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.*: d9ba641b st2g x27, \[x0\], #-1440
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.*: d9affbe0 st2g x0, \[sp, #4080\]
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.*: d9affbff st2g xzr, \[sp, #4080\]
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.*: d9b00bfb st2g x27, \[sp, #-4096\]
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.*: d9afffe0 st2g x0, \[sp, #4080\]!
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.*: d9b007ff st2g xzr, \[sp\], #-4096
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.*: d9e00800 stz2g x0, \[x0\]
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.*: d9e00b60 stz2g x0, \[x27\]
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.*: d9e0081f stz2g xzr, \[x0\]
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.*: d9ffb81b stz2g x27, \[x0, #-80\]
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.*: d9e00c00 stz2g x0, \[x0, #0\]!
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.*: d9e00c1f stz2g xzr, \[x0, #0\]!
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.*: d9e0ac1b stz2g x27, \[x0, #160\]!
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.*: d9e00400 stz2g x0, \[x0\], #0
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.*: d9e0041f stz2g xzr, \[x0\], #0
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.*: d9fa641b stz2g x27, \[x0\], #-1440
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.*: d9effbe0 stz2g x0, \[sp, #4080\]
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.*: d9effbff stz2g xzr, \[sp, #4080\]
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.*: d9f00bfb stz2g x27, \[sp, #-4096\]
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.*: d9efffe0 stz2g x0, \[sp, #4080\]!
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.*: d9f007ff stz2g xzr, \[sp\], #-4096
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.*: 69000000 stgp x0, x0, \[x0\]
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.*: 69006c00 stgp x0, x27, \[x0\]
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.*: 6900001b stgp x27, x0, \[x0\]
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@ -17,17 +17,21 @@ func:
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.endm
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.macro expand_stg op
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\op [x0, #0]
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\op [x27, #0]
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\op [x0, #-80]
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\op [x0, #0]!
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\op [x0, #160]!
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\op [x0], #0
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\op [x0], #-1440
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\op [sp, #4080]
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\op [sp, #-4096]
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\op [sp, #4080]!
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\op [sp], #-4096
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\op x0, [x0, #0]
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\op x0, [x27, #0]
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\op xzr, [x0, #0]
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\op x27, [x0, #-80]
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\op x0, [x0, #0]!
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\op xzr, [x0, #0]!
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\op x27, [x0, #160]!
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\op x0, [x0], #0
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\op xzr, [x0], #0
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\op x27, [x0], #-1440
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\op x0, [sp, #4080]
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\op xzr, [sp, #4080]
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\op x27, [sp, #-4096]
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\op x0, [sp, #4080]!
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\op xzr, [sp], #-4096
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.endm
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.macro expand_ldg_bulk op
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@ -4,9 +4,9 @@
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10'
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[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4'
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[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 1 -- `stg \[x1,#15\]'
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[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `stzg \[x1,#-4097]!'
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[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `st2g \[x1],#4096'
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[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 2 -- `stg x2,\[x1,#15\]'
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[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `stzg x2,\[x1,#-4097\]!'
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[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `st2g x2,\[x1\],#4096'
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[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 2 -- `ldg x1,\[x2,#33\]'
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[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `ldg x1,\[x2,#4112\]'
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[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
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@ -30,10 +30,14 @@
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[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
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[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
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[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stg \[xzr,#0\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `st2g \[xzr,#0]!'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stzg \[xzr],#0'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stz2g \[xzr,#0\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stg x2,\[xzr,#0\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stg sp,\[x2,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `st2g sp,\[x2,#0\]!'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzg sp,\[x2\],#0'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stz2g sp,\[x2,#0\]'
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[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
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[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
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[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
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@ -9,9 +9,9 @@ func:
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subg x1, x2, #0x3f0, -4
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# STG/STZG/ST2G/LDG : Fail imm
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stg [x1, #15]
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stzg [x1, #-4097]!
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st2g [x1], #4096
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stg x2, [x1, #15]
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stzg x2, [x1, #-4097]!
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st2g x2, [x1], #4096
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ldg x1, [x2, #33]
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ldg x1, [x2, #4112]
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@ -41,10 +41,14 @@ func:
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subps x1, x2, xzr
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cmpp xzr, x2
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cmpp x2, xzr
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stg [xzr, #0]
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st2g [xzr, #0]!
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stzg [xzr], #0
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stz2g [xzr, #0]
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stg x2, [xzr, #0]
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st2g x2, [xzr, #0]!
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stzg x2, [xzr], #0
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stz2g x2, [xzr, #0]
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stg sp, [x2, #0]
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st2g sp, [x2, #0]!
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stzg sp, [x2], #0
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stz2g sp, [x2, #0]
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stgp sp, x2, [x3]
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stgp x1, sp, [x3]
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stgp x0, x0, [xzr]
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@ -52,3 +56,6 @@ func:
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ldg x0, [xzr, #16]
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stzgm x0, [xzr]
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stzgm sp, [x3]
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# Xt == Xn with writeback should not complain
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st2g x2, [x2, #0]!
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stzg x2, [x2], #0
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@ -125,10 +125,10 @@
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QLF1(X), \
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}
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/* e.g. STG [<Xn|SP>, #<imm9>]. */
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/* e.g. STG Xt, [<Xn|SP>, #<imm9>]. */
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#define QL_LDST_AT \
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{ \
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QLF1(imm_tag), \
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QLF2(X, imm_tag), \
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}
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/* e.g. RBIT <Wd>, <Wn>. */
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@ -3237,14 +3237,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
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CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
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/* Load/store Allocation Tag instructions. */
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MEMTAG_INSN ("stg", 0xd920081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stzg", 0xd960081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("st2g", 0xd9a0081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stz2g",0xd9e0081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stg", 0xd920041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stzg", 0xd960041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("st2g", 0xd9a0041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stz2g",0xd9e0041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt, ADDR_SIMM13), QL_LDST_AT, 0),
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/* Load/store register (unsigned immediate). */
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CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
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CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
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|
|
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Reference in New Issue