* gas/config/tc-arm.c (md_pseduo_table): Add .arch_extension directive.
(arm_option_extension_value_table): Add. (arm_extensions): Change type. (arm_option_cpu_table): Rename... (arm_option_fpu_table): ...to this. (arm_fpus): Change type. (arm_parse_extension): Enforce alphabetical order. Allow extensions to be removed. (arm_parse_arch): Allow extensions to be specified with -march. (s_arm_arch_extension): Add. (s_arm_fpu): Update for type changes. * gas/doc/c-arm.texi: Document changes to infrastructure.
This commit is contained in:
Matthew Gretton-Dann
parent
78336cd61f
commit
6913386316
@ -1,3 +1,18 @@
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (md_pseduo_table): Add .arch_extension directive.
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(arm_option_extension_value_table): Add.
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(arm_extensions): Change type.
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(arm_option_cpu_table): Rename...
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(arm_option_fpu_table): ...to this.
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(arm_fpus): Change type.
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(arm_parse_extension): Enforce alphabetical order. Allow
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extensions to be removed.
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(arm_parse_arch): Allow extensions to be specified with -march.
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(s_arm_arch_extension): Add.
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(s_arm_fpu): Update for type changes.
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* doc/c-arm.texi: Document changes to infrastructure.
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2010-09-23 Alan Modra <amodra@gmail.com>
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* config/tc-mn10300.c (tc_gen_reloc): Replace absolute symbols
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@ -4270,6 +4270,7 @@ static void s_arm_arch (int);
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static void s_arm_object_arch (int);
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static void s_arm_cpu (int);
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static void s_arm_fpu (int);
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static void s_arm_arch_extension (int);
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#ifdef TE_PE
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@ -4323,6 +4324,7 @@ const pseudo_typeS md_pseudo_table[] =
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{ "arch", s_arm_arch, 0 },
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{ "object_arch", s_arm_object_arch, 0 },
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{ "fpu", s_arm_fpu, 0 },
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{ "arch_extension", s_arm_arch_extension, 0 },
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#ifdef OBJ_ELF
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{ "word", s_arm_elf_cons, 4 },
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{ "long", s_arm_elf_cons, 4 },
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@ -22451,25 +22453,35 @@ static const struct arm_arch_option_table arm_archs[] =
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{NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
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};
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/* ISA extensions in the co-processor space. */
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struct arm_option_cpu_value_table
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/* ISA extensions in the co-processor and main instruction set space. */
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struct arm_option_extension_value_table
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{
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char *name;
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const arm_feature_set value;
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const arm_feature_set allowed_archs;
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};
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/* The following table must be in alphabetical order with a NULL last entry.
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*/
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static const struct arm_option_extension_value_table arm_extensions[] =
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{
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{"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
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{"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
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{"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
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{"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
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{NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
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};
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/* ISA floating-point and Advanced SIMD extensions. */
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struct arm_option_fpu_value_table
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{
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char *name;
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const arm_feature_set value;
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};
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static const struct arm_option_cpu_value_table arm_extensions[] =
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{
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{"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
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{"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
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{"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
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{"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
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{NULL, ARM_ARCH_NONE}
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};
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/* This list should, at a minimum, contain all the fpu names
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recognized by GCC. */
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static const struct arm_option_cpu_value_table arm_fpus[] =
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static const struct arm_option_fpu_value_table arm_fpus[] =
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{
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{"softfpa", FPU_NONE},
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{"fpe", FPU_ARCH_FPE},
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@ -22547,15 +22559,23 @@ arm_parse_extension (char * str, const arm_feature_set **opt_p)
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arm_feature_set *ext_set = (arm_feature_set *)
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xmalloc (sizeof (arm_feature_set));
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/* We insist on extensions being specified in alphabetical order, and with
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extensions being added before being removed. We achieve this by having
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the global ARM_EXTENSIONS table in alphabetical order, and using the
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ADDING_VALUE variable to indicate whether we are adding an extension (1)
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or removing it (0) and only allowing it to change in the order
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-1 -> 1 -> 0. */
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const struct arm_option_extension_value_table * opt = NULL;
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int adding_value = -1;
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/* Copy the feature set, so that we can modify it. */
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*ext_set = **opt_p;
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*opt_p = ext_set;
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while (str != NULL && *str != 0)
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{
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const struct arm_option_cpu_value_table * opt;
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char * ext;
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int optlen;
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size_t optlen;
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if (*str != '+')
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{
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@ -22571,24 +22591,86 @@ arm_parse_extension (char * str, const arm_feature_set **opt_p)
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else
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optlen = strlen (str);
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if (optlen >= 2
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&& strncmp (str, "no", 2) == 0)
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{
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if (adding_value != 0)
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{
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adding_value = 0;
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opt = arm_extensions;
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}
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optlen -= 2;
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str += 2;
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}
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else if (optlen > 0)
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{
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if (adding_value == -1)
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{
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adding_value = 1;
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opt = arm_extensions;
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}
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else if (adding_value != 1)
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{
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as_bad (_("must specify extensions to add before specifying "
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"those to remove"));
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return FALSE;
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}
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}
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if (optlen == 0)
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{
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as_bad (_("missing architectural extension"));
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return FALSE;
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}
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for (opt = arm_extensions; opt->name != NULL; opt++)
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if (strncmp (opt->name, str, optlen) == 0)
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gas_assert (adding_value != -1);
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gas_assert (opt != NULL);
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/* Scan over the options table trying to find an exact match. */
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for (; opt->name != NULL; opt++)
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if (strncmp (opt->name, str, optlen) == 0
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&& strlen (opt->name) == optlen)
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{
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ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
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/* Check we can apply the extension to this architecture. */
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if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
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{
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as_bad (_("extension does not apply to the base architecture"));
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return FALSE;
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}
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/* Add or remove the extension. */
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if (adding_value)
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ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
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else
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ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
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break;
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}
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if (opt->name == NULL)
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{
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as_bad (_("unknown architectural extension `%s'"), str);
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/* Did we fail to find an extension because it wasn't specified in
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alphabetical order, or because it does not exist? */
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for (opt = arm_extensions; opt->name != NULL; opt++)
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if (strncmp (opt->name, str, optlen) == 0)
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break;
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if (opt->name == NULL)
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as_bad (_("unknown architectural extension `%s'"), str);
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else
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as_bad (_("architectural extensions must be specified in "
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"alphabetical order"));
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return FALSE;
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}
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else
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{
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/* We should skip the extension we've just matched the next time
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round. */
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opt++;
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}
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str = ext;
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};
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@ -22659,7 +22741,7 @@ arm_parse_arch (char * str)
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}
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for (opt = arm_archs; opt->name != NULL; opt++)
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if (streq (opt->name, str))
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if (strncmp (opt->name, str, optlen) == 0)
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{
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march_cpu_opt = &opt->value;
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march_fpu_opt = &opt->default_fpu;
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@ -22678,7 +22760,7 @@ arm_parse_arch (char * str)
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static bfd_boolean
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arm_parse_fpu (char * str)
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{
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const struct arm_option_cpu_value_table * opt;
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const struct arm_option_fpu_value_table * opt;
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for (opt = arm_fpus; opt->name != NULL; opt++)
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if (streq (opt->name, str))
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@ -23183,12 +23265,64 @@ s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
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ignore_rest_of_line ();
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}
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/* Parse a .arch_extension directive. */
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static void
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s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
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{
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const struct arm_option_extension_value_table *opt;
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char saved_char;
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char *name;
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int adding_value = 1;
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name = input_line_pointer;
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while (*input_line_pointer && !ISSPACE (*input_line_pointer))
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input_line_pointer++;
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saved_char = *input_line_pointer;
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*input_line_pointer = 0;
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if (strlen (name) >= 2
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&& strncmp (name, "no", 2) == 0)
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{
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adding_value = 0;
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name += 2;
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}
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for (opt = arm_extensions; opt->name != NULL; opt++)
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if (streq (opt->name, name))
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{
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if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
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{
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as_bad (_("architectural extension `%s' is not allowed for the "
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"current base architecture"), name);
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break;
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}
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if (adding_value)
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ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
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else
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ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
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mcpu_cpu_opt = &selected_cpu;
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ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
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*input_line_pointer = saved_char;
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demand_empty_rest_of_line ();
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return;
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}
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if (opt->name == NULL)
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as_bad (_("unknown architecture `%s'\n"), name);
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*input_line_pointer = saved_char;
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ignore_rest_of_line ();
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}
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/* Parse a .fpu directive. */
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static void
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s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
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{
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const struct arm_option_cpu_value_table *opt;
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const struct arm_option_fpu_value_table *opt;
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char saved_char;
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char *name;
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@ -133,12 +133,24 @@ assembler to accept instructions valid for any ARM processor.
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In addition to the basic instruction set, the assembler can be told to
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accept various extension mnemonics that extend the processor using the
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co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
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is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
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are currently supported:
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@code{+maverick}
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@code{+iwmmxt}
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is equivalent to specifying @code{-mcpu=ep9312}.
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Multiple extensions may be specified, separated by a @code{+}. The
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extensions should be specified in ascending alphabetical order.
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Extension mnemonics may also be removed from those the assembler accepts.
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This is done be prepending @code{no} to the option that adds the extension.
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Extensions that are removed should be listed after all extensions which have
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been added, again in ascending alphabetical order. For example,
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@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
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The following extensions are currently supported:
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@code{iwmmxt},
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@code{iwmmxt2},
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@code{maverick},
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and
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@code{+xscale}.
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@code{xscale}.
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@cindex @code{-march=} command line option, ARM
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@item -march=@var{architecture}[+@var{extension}@dots{}]
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@ -503,6 +515,18 @@ boundary). This is for compatibility with ARM's own assembler.
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Select the target architecture. Valid values for @var{name} are the same as
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for the @option{-march} commandline option.
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Specifying @code{.arch} clears any previously selected architecture
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extensions.
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@cindex @code{.arch_extension} directive, ARM
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@item .arch_extension @var{name}
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Add or remove an architecture extension to the target architecture. Valid
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values for @var{name} are the same as those accepted as architectural
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extensions by the @option{-mcpu} commandline option.
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@code{.arch_extension} may be used multiple times to add or remove extensions
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incrementally to the architecture being compiled for.
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@cindex @code{.arm} directive, ARM
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@item .arm
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This performs the same action as @var{.code 32}.
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@ -537,6 +561,9 @@ selects Thumb, with the value 32 selecting ARM.
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Select the target processor. Valid values for @var{name} are the same as
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for the @option{-mcpu} commandline option.
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Specifying @code{.cpu} clears any previously selected architecture
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extensions.
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@c DDDDDDDDDDDDDDDDDDDDDDDDDD
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@cindex @code{.dn} and @code{.qn} directives, ARM
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